Lines Matching +full:0 +full:xf800

39 	interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 	interrupts = <24 0x2 0 0>;
47 	bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 	bus-range = <0 255>;
61 	interrupts = <25 2 0 0>;
63 	pcie@0 {
64 		reg = <0 0 0 0 0>;
69 		interrupts = <25 2 0 0>;
70 		interrupt-map-mask = <0xf800 0 0 7>;
73 			/* IDSEL 0x0 */
74 			0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 			0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 			0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 			0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
82 /* controller at 0xa000 */
88 	bus-range = <0 255>;
90 	interrupts = <26 2 0 0>;
92 	pcie@0 {
93 		reg = <0 0 0 0 0>;
98 		interrupts = <26 2 0 0>;
99 		interrupt-map-mask = <0xf800 0 0 7>;
101 			/* IDSEL 0x0 */
102 			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
110 /* controller at 0xb000 */
116 	bus-range = <0 255>;
118 	interrupts = <27 2 0 0>;
120 	pcie@0 {
121 		reg = <0 0 0 0 0>;
126 		interrupts = <27 2 0 0>;
127 		interrupt-map-mask = <0xf800 0 0 7>;
129 			/* IDSEL 0x0 */
130 			0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 			0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 			0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 			0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
143 	bus-frequency = <0>;		// Filled out by uboot.
145 	ecm-law@0 {
147 		reg = <0x0 0x1000>;
153 		reg = <0x1000 0x1000>;
154 		interrupts = <17 2 0 0>;
159 		reg = <0x2000 0x1000>;
160 		interrupts = <18 2 0 0>;
163 /include/ "pq3-i2c-0.dtsi"
165 /include/ "pq3-duart-0.dtsi"
169 		reg = <0x20000 0x1000>;
171 		cache-size = <0x40000>; // L2, 256K
172 		interrupts = <16 2 0 0>;
175 /include/ "pq3-dma-0.dtsi"
176 /include/ "pq3-etsec1-0.dtsi"
183 /include/ "pq3-sec2.1-0.dtsi"
188 		reg = <0xe0000 0x1000>;