377 	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;  in handle_unaligned()
394 				regs->iaoq[0], regs->iir);  in handle_unaligned()
405 	switch (MAJOR_OP(regs->iir))  in handle_unaligned()
410 		if (regs->iir&0x20)  in handle_unaligned()
413 			if (regs->iir&0x1000)		/* short loads */  in handle_unaligned()
414 				if (regs->iir&0x200)  in handle_unaligned()
415 					newbase += IM5_3(regs->iir);  in handle_unaligned()
417 					newbase += IM5_2(regs->iir);  in handle_unaligned()
418 			else if (regs->iir&0x2000)	/* scaled indexed */  in handle_unaligned()
421 				switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
431 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;  in handle_unaligned()
433 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);  in handle_unaligned()
439 		newbase += IM14(regs->iir);  in handle_unaligned()
443 		if (regs->iir&8)  in handle_unaligned()
446 			newbase += IM14(regs->iir&~0xe);  in handle_unaligned()
452 		newbase += IM14(regs->iir&6);  in handle_unaligned()
456 		if (regs->iir&4)  in handle_unaligned()
459 			newbase += IM14(regs->iir&~4);  in handle_unaligned()
465 	switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
469 		ret = emulate_ldh(regs, R3(regs->iir));  in handle_unaligned()
476 		ret = emulate_ldw(regs, R3(regs->iir), 0);  in handle_unaligned()
480 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
485 		ret = emulate_stw(regs, R2(regs->iir), 0);  in handle_unaligned()
493 		ret = emulate_ldd(regs, R3(regs->iir), 0);  in handle_unaligned()
498 		ret = emulate_std(regs, R2(regs->iir), 0);  in handle_unaligned()
506 		ret = emulate_ldw(regs, FR3(regs->iir), 1);  in handle_unaligned()
511 		ret = emulate_ldd(regs, R3(regs->iir), 1);  in handle_unaligned()
518 		ret = emulate_stw(regs, FR3(regs->iir), 1);  in handle_unaligned()
523 		ret = emulate_std(regs, R3(regs->iir), 1);  in handle_unaligned()
533 	switch (regs->iir & OPCODE2_MASK)  in handle_unaligned()
536 		ret = emulate_ldd(regs,R2(regs->iir),1);  in handle_unaligned()
539 		ret = emulate_std(regs, R2(regs->iir),1);  in handle_unaligned()
543 		ret = emulate_ldd(regs, R2(regs->iir),0);  in handle_unaligned()
546 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
550 	switch (regs->iir & OPCODE3_MASK)  in handle_unaligned()
553 		ret = emulate_ldw(regs, R2(regs->iir), 1);  in handle_unaligned()
556 		ret = emulate_ldw(regs, R2(regs->iir), 0);  in handle_unaligned()
560 		ret = emulate_stw(regs, R2(regs->iir),1);  in handle_unaligned()
563 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
566 	switch (regs->iir & OPCODE4_MASK)  in handle_unaligned()
569 		ret = emulate_ldh(regs, R2(regs->iir));  in handle_unaligned()
573 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
576 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
580 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
584 	if (ret == 0 && modify && R1(regs->iir))  in handle_unaligned()
585 		regs->gr[R1(regs->iir)] = newbase;  in handle_unaligned()
589 		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);  in handle_unaligned()
639 	switch (regs->iir & OPCODE1_MASK) {  in check_unaligned()
657 		switch (regs->iir & OPCODE4_MASK) {  in check_unaligned()