Lines Matching +full:0 +full:x1b00
48 l.addi r2,r1,0 /* move sp to fp */ ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
224 l.addi r3,r1,0 ;\
236 l.sw 0(reg),r0
248 /* ---[ 0x100: RESET exception ]----------------------------------------- */
252 l.andi r0,r0,0
254 /* ---[ 0x200: BUS exception ]------------------------------------------- */
260 l.addi r3,r1,0 /* pt_regs */
265 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
275 l.ori r5,r0,0x300 // exception vector
277 l.addi r3,r1,0 // pt_regs
282 l.lwz r6,0(r6) // instruction that caused pf
285 l.sfeqi r6,0 // l.j
293 l.sfeqi r6,0x11 // l.jr
295 l.sfeqi r6,0x12 // l.jalr
305 l.lwz r6,0(r6) // instruction that caused pf
319 l.lwz r6,0(r6) // instruction that caused pf
323 l.sfgeui r6,0x33 // check opcode for write access
325 l.sfleui r6,0x37
327 l.ori r6,r0,0x1 // write access
330 1: l.ori r6,r0,0x0 // !write access
339 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
349 l.ori r5,r0,0x400 // exception vector
351 l.addi r3,r1,0 // pt_regs
353 l.ori r6,r0,0x0 // !write access
362 /* ---[ 0x500: Timer exception ]----------------------------------------- */
367 l.addi r3,r1,0 /* pt_regs */
372 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
378 l.addi r3,r1,0 /* pt_regs */
383 #if 0
386 l.addi r2,r4,0
390 l.lwz r3,0(r5) /* Load insn */
393 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
395 l.sfeqi r4,0x01
397 l.sfeqi r4,0x03
399 l.sfeqi r4,0x04
401 l.sfeqi r4,0x11
403 l.sfeqi r4,0x12
422 l.andi r4,r4,0x7c
427 l.lwz r5,0(r4)
436 l.sfeqi r4,0x26
438 l.sfeqi r4,0x25
440 l.sfeqi r4,0x22
442 l.sfeqi r4,0x21
444 l.sfeqi r4,0x37
446 l.sfeqi r4,0x35
453 lhs: l.lbs r5,0(r2)
458 l.andi r4,r4,0x7c
461 l.sw 0(r4),r5
463 lhz: l.lbz r5,0(r2)
468 l.andi r4,r4,0x7c
471 l.sw 0(r4),r5
473 lws: l.lbs r5,0(r2)
484 l.andi r4,r4,0x7c
487 l.sw 0(r4),r5
489 lwz: l.lbz r5,0(r2)
500 l.andi r4,r4,0x7c
503 l.sw 0(r4),r5
507 l.andi r4,r4,0x7c
509 l.lwz r5,0(r4)
513 l.sb 0(r2),r5
517 l.andi r4,r4,0x7c
519 l.lwz r5,0(r4)
527 l.sb 0(r2),r5
534 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
539 l.addi r3,r1,0 /* pt_regs */
544 /* ---[ 0x800: External interrupt exception ]---------------------------- */
550 l.sfeqi r4,0
555 l.addi r1,r1,-0x8
558 l.sw 0x0(r1),r3
560 l.sw 0x4(r1),r4
561 l.addi r1,r1,0x8
575 l.addi r3,r1,0
583 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
586 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
589 /* ---[ 0xb00: Range exception ]----------------------------------------- */
591 UNHANDLED_EXCEPTION(_vector_0xb00,0xb00)
593 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
608 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
671 l.lwz r29,0(r29)
682 #if 0
699 #if 0
817 l.addi r3,r1,0
835 l.addi r3,r1,0
851 /* ---[ 0xd00: Floating Point exception ]-------------------------------- */
857 l.addi r3,r1,0 /* pt_regs */
862 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
868 l.addi r3,r1,0 /* pt_regs */
873 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
875 UNHANDLED_EXCEPTION(_vector_0xf00,0xf00)
877 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
879 UNHANDLED_EXCEPTION(_vector_0x1000,0x1000)
881 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
883 UNHANDLED_EXCEPTION(_vector_0x1100,0x1100)
885 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
887 UNHANDLED_EXCEPTION(_vector_0x1200,0x1200)
889 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
891 UNHANDLED_EXCEPTION(_vector_0x1300,0x1300)
893 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
895 UNHANDLED_EXCEPTION(_vector_0x1400,0x1400)
897 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
899 UNHANDLED_EXCEPTION(_vector_0x1500,0x1500)
901 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
903 UNHANDLED_EXCEPTION(_vector_0x1600,0x1600)
905 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
907 UNHANDLED_EXCEPTION(_vector_0x1700,0x1700)
909 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
911 UNHANDLED_EXCEPTION(_vector_0x1800,0x1800)
913 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
915 UNHANDLED_EXCEPTION(_vector_0x1900,0x1900)
917 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
919 UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00)
921 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
923 UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00)
925 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
927 UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00)
929 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
931 UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00)
933 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
935 UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00)
937 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
939 UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
948 l.sfeqi r13,0
954 l.sfltsi r5,0
957 l.andi r5,r5,0
960 l.ori r3,r1,0 /* pt_regs */
962 l.sfeqi r11,0
965 l.sfltsi r11,0
1001 l.sfeqi r3,0
1012 l.sfeqi r20,0
1080 .align 0x400
1107 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1209 l.addi r3,r1,0
1214 l.addi r3,r1,0
1236 l.lwz r29,0(r4)
1237 l.lwz r27,0(r5)
1238 l.sw 0(r4),r27
1239 l.sw 0(r5),r29