Lines Matching full:have
81 bool "Have write through data caches"
98 bool "Have instruction l.ff1"
104 bool "Have instruction l.fl1"
110 bool "Have instruction l.mul for hardware multiply"
116 bool "Have instruction l.div for hardware divide"
122 bool "Have instruction l.cmov for conditional move"
135 bool "Have instruction l.ror for rotate right"
148 bool "Have instruction l.rori for rotate right with immediate"
161 bool "Have instructions l.ext* for sign extension"
184 This enables support for systems with more than one CPU. If you have
185 a system with only one CPU, say N. If you have a system with more
199 OpenRISC architecture makes it optional to have it implemented
200 in hardware and the OR1200 does not have it.
232 your kernel crashes this doesn't have any influence.