701 	union cvmx_npei_mem_access_subidx mem_access_subid;  in __cvmx_pcie_rc_initialize_gen1()  local
889 	mem_access_subid.u64 = 0;  in __cvmx_pcie_rc_initialize_gen1()
890 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */  in __cvmx_pcie_rc_initialize_gen1()
891 	mem_access_subid.s.nmerge = 1;	/* Due to an errata on pass 1 chips, no merging is allowed. */  in __cvmx_pcie_rc_initialize_gen1()
892 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */  in __cvmx_pcie_rc_initialize_gen1()
893 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */  in __cvmx_pcie_rc_initialize_gen1()
894 …mem_access_subid.s.nsr = 0;	/* Enable Snooping for Reads. Octeon doesn't care, but devices might w…  in __cvmx_pcie_rc_initialize_gen1()
895 	mem_access_subid.s.nsw = 0;	/* Enable Snoop for Writes. */  in __cvmx_pcie_rc_initialize_gen1()
896 	mem_access_subid.s.ror = 0;	/* Disable Relaxed Ordering for Reads. */  in __cvmx_pcie_rc_initialize_gen1()
897 	mem_access_subid.s.row = 0;	/* Disable Relaxed Ordering for Writes. */  in __cvmx_pcie_rc_initialize_gen1()
898 	mem_access_subid.s.ba = 0;	/* PCIe Address Bits <63:34>. */  in __cvmx_pcie_rc_initialize_gen1()
905 		cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);  in __cvmx_pcie_rc_initialize_gen1()
906 		mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */  in __cvmx_pcie_rc_initialize_gen1()
1160 	union cvmx_sli_mem_access_subidx mem_access_subid;  in __cvmx_pcie_rc_initialize_gen2()  local
1341 	mem_access_subid.u64 = 0;  in __cvmx_pcie_rc_initialize_gen2()
1342 	mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */  in __cvmx_pcie_rc_initialize_gen2()
1343 	mem_access_subid.s.nmerge = 0;	/* Allow merging as it works on CN6XXX. */  in __cvmx_pcie_rc_initialize_gen2()
1344 	mem_access_subid.s.esr = 1;	/* Endian-swap for Reads. */  in __cvmx_pcie_rc_initialize_gen2()
1345 	mem_access_subid.s.esw = 1;	/* Endian-swap for Writes. */  in __cvmx_pcie_rc_initialize_gen2()
1346 	mem_access_subid.s.wtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */  in __cvmx_pcie_rc_initialize_gen2()
1347 	mem_access_subid.s.rtype = 0;	/* "No snoop" and "Relaxed ordering" are not set */  in __cvmx_pcie_rc_initialize_gen2()
1350 		mem_access_subid.cn68xx.ba = 0;  in __cvmx_pcie_rc_initialize_gen2()
1352 		mem_access_subid.s.ba = 0;  in __cvmx_pcie_rc_initialize_gen2()
1359 		cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);  in __cvmx_pcie_rc_initialize_gen2()
1361 		__cvmx_increment_ba(&mem_access_subid);  in __cvmx_pcie_rc_initialize_gen2()