Lines Matching +full:64 +full:- +full:bit
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
96 #include "access-helper.h"
120 orig31 = regs->regs[31]; in emulate_load_store_insn()
132 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
176 regs->regs[insn.mxu_lx_format.rd] = value; in emulate_load_store_insn()
185 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
194 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
214 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
223 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
244 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
253 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
262 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
268 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
277 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
300 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
315 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
330 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
336 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
337 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
338 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
339 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
340 * instructions on 32-bit kernels. in emulate_load_store_insn()
349 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
353 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
359 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
360 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
361 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
362 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
363 * instructions on 32-bit kernels. in emulate_load_store_insn()
372 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
376 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
384 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
400 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
414 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
415 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
416 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
417 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
418 * instructions on 32-bit kernels. in emulate_load_store_insn()
424 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
431 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
446 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
478 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
585 regs->cp0_epc = origpc; in emulate_load_store_insn()
586 regs->regs[31] = orig31; in emulate_load_store_insn()
608 /* Recode table from 16-bit register notation to 32-bit GPR. */
611 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
630 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
631 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
638 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
641 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
648 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
698 regs->regs[reg] = value; in emulate_load_store_microMIPS()
703 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
714 value = regs->regs[reg]; in emulate_load_store_microMIPS()
719 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
737 regs->regs[reg] = value; in emulate_load_store_microMIPS()
742 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
757 value = regs->regs[reg]; in emulate_load_store_microMIPS()
762 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
785 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
790 regs->regs[i] = value; in emulate_load_store_microMIPS()
797 regs->regs[30] = value; in emulate_load_store_microMIPS()
803 regs->regs[31] = value; in emulate_load_store_microMIPS()
821 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
822 value = regs->regs[i]; in emulate_load_store_microMIPS()
829 value = regs->regs[30]; in emulate_load_store_microMIPS()
836 value = regs->regs[31]; in emulate_load_store_microMIPS()
859 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
864 regs->regs[i] = value; in emulate_load_store_microMIPS()
871 regs->regs[30] = value; in emulate_load_store_microMIPS()
877 regs->regs[31] = value; in emulate_load_store_microMIPS()
900 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
901 value = regs->regs[i]; in emulate_load_store_microMIPS()
908 value = regs->regs[30]; in emulate_load_store_microMIPS()
915 value = regs->regs[31]; in emulate_load_store_microMIPS()
960 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
961 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
967 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
1016 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1021 regs->regs[i] = value; in emulate_load_store_microMIPS()
1026 regs->regs[31] = value; in emulate_load_store_microMIPS()
1036 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1037 value = regs->regs[i]; in emulate_load_store_microMIPS()
1043 value = regs->regs[31]; in emulate_load_store_microMIPS()
1093 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1103 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1113 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1119 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1120 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1121 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1122 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1123 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1131 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1135 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1141 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1142 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1143 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1144 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1145 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1153 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1157 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1164 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1174 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1183 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1184 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1185 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1186 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1187 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1192 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1199 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1203 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1212 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1213 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1248 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1249 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1355 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1366 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1379 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1385 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1386 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1387 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1388 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1389 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1398 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1402 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1409 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1410 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1411 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1412 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1413 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1422 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1426 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1434 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1442 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1447 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1457 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1458 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1459 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1460 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1461 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1467 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1474 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1493 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1494 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1523 1, regs, regs->cp0_badvaddr); in do_ade()
1528 * virtual user address and 64bit maximum virtual user address in do_ade()
1531 if ((regs->cp0_badvaddr >= (1UL << cpu_vmbits)) && in do_ade()
1532 (regs->cp0_badvaddr < XKSSEG)) { in do_ade()
1534 current->thread.cp0_baduaddr = regs->cp0_badvaddr; in do_ade()
1544 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1560 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1563 * 16-bit mode? in do_ade()
1565 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1572 (void __user *)regs->cp0_badvaddr); in do_ade()
1578 (void __user *)regs->cp0_badvaddr); in do_ade()
1589 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()