1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
64 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {  in cps_smp_setup()
88 	/* Core 0 is powered up (we're running on it) */  in cps_smp_setup()
103 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_setup()
117 	/* Detect whether the CCA is unsuited to multi-core SMP */  in cps_prepare_cpus()
122 		/* The CCA is coherent, multi-core is fine */  in cps_prepare_cpus()
127 		/* CCA is not coherent, multi-core is not usable */  in cps_prepare_cpus()
131 	/* Warn the user if the CCA prevents multi-core */  in cps_prepare_cpus()
160 		     (void *)entry_code - (void *)&mips_cps_core_entry);  in cps_prepare_cpus()
257 				timeout--;  in boot_core()
275 	/* The core is now powered up */  in boot_core()
292 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];  in cps_boot_secondary()
299 		return -ENOSYS;  in cps_boot_secondary()
301 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;  in cps_boot_secondary()
302 	vpe_cfg->sp = __KSTK_TOS(idle);  in cps_boot_secondary()
303 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);  in cps_boot_secondary()
305 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);  in cps_boot_secondary()
310 		/* Boot a VPE on a powered down core */  in cps_boot_secondary()
323 		/* Boot a VPE on another powered up core */  in cps_boot_secondary()
356 	/* Disable MT - we only want to run 1 TC per VPE */  in cps_init_secondary()
387 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_finish()
454 		return -EINVAL;  in cps_cpu_disable()
457 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);  in cps_cpu_disable()
532 	 *   - Onlining the CPU again.  in cps_cleanup_dead_cpu()
533 	 *   - Powering down the core if another VPE within it is offlined.  in cps_cleanup_dead_cpu()
534 	 *   - A sibling VPE entering a non-coherent state.  in cps_cleanup_dead_cpu()
536 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing  in cps_cleanup_dead_cpu()
541 		 * Wait for the core to enter a powered down or clock gated  in cps_cleanup_dead_cpu()
561 			 * The core ought to have powered down, but didn't &  in cps_cleanup_dead_cpu()
564 			 * 1 & it powered back up as soon as we powered it  in cps_cleanup_dead_cpu()
572 				 "CPU%u hasn't powered down, seq. state %u\n",  in cps_cleanup_dead_cpu()
577 		/* Indicate the core is powered off */  in cps_cleanup_dead_cpu()
628 		return -ENODEV;  in register_cps_smp_ops()
631 	/* check we have a GIC - we need one for IPIs */  in register_cps_smp_ops()
634 		return -ENODEV;  in register_cps_smp_ops()