Lines Matching +full:0 +full:xbfdf0000
30 #define SNI_CPU_M8021 0x01
31 #define SNI_CPU_M8030 0x04
32 #define SNI_CPU_M8031 0x06
33 #define SNI_CPU_M8034 0x0f
34 #define SNI_CPU_M8037 0x07
35 #define SNI_CPU_M8040 0x05
36 #define SNI_CPU_M8043 0x09
37 #define SNI_CPU_M8050 0x0b
38 #define SNI_CPU_M8053 0x0d
40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
46 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
47 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
48 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
49 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
50 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
51 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
52 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
53 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
54 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
55 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
56 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
57 #define IT_INT2 0x01
58 #define IT_INTD 0x02
59 #define IT_INTC 0x04
60 #define IT_INTB 0x08
61 #define IT_INTA 0x10
62 #define IT_EISA 0x20
63 #define IT_SCSI 0x40
64 #define IT_ETH 0x80
65 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
66 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
67 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
68 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
69 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
70 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
71 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
72 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
73 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
74 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
75 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
80 #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
81 #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
82 #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
83 #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
84 #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
85 #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
86 #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
87 #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
88 #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
89 #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
90 #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
91 #define IT_INT2 0x01
92 #define IT_INTD 0x02
93 #define IT_INTC 0x04
94 #define IT_INTB 0x08
95 #define IT_INTA 0x10
96 #define IT_EISA 0x20
97 #define IT_SCSI 0x40
98 #define IT_ETH 0x80
99 #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
100 #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
101 #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
102 #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
103 #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
104 #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
105 #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
106 #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
107 #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
108 #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
109 #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
112 #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
117 #define PCIMT_CONFIG_DATA 0x0cfc
122 #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
123 #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
124 #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
125 #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
126 #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
127 #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
128 #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
129 #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
130 #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
131 #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
132 #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
133 #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
134 #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
135 #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
136 #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
137 #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
142 #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
143 #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
144 #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
149 #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
155 #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
164 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
181 #if 0
191 #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
194 #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
204 #define __SNI_END 0
209 #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
210 #define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
211 #define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
212 #define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
214 #define SNI_IDPROM_SIZE 0x1000
235 return 0; in sni_eisa_root_init()