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19 #include <asm-generic/pgtable-nopmd.h>
26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails):
28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size,
29 * our 2-level table layout would normally have a PGD entry cover a contiguous
30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t
32 * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page
37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly.
39 * NOTE: We don't yet support huge pages if extended-addressing is enabled
40 * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic).
46 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
56 * Basically we have the same two-level (which is the logical three level
63 /* PGDIR_SHIFT determines what a third-level page table entry can map */
65 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2 - 1)
67 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2)
71 #define PGDIR_MASK (~(PGDIR_SIZE-1))
74 * Entries per page directory level: we use two-level, so
78 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1)
80 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
87 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
89 # define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t) / 2)
98 #define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
99 #define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
102 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
104 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
203 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
204 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
205 * <----------- offset ------------> < type -> V G E 0 0 0 0 0 0 P
227 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
228 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
229 * 0 0 0 0 0 0 E P <------------------ zeroes ------------------->
231 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
232 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
233 * <----------------- offset ------------------> < type -> V G 0 0
256 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
257 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
258 * <------------------ zeroes -------------------> E P 0 0 0 0 0 0
260 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
261 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
262 * <------------------- offset --------------------> < type -> V G
268 #define __swp_type(x) (((x).val >> 2) & 0x1f)
270 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 2) | ((offset) << 7) })
284 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
285 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
286 * <------------- offset --------------> < type -> 0 0 0 0 0 0 E P