Lines Matching +full:6 +full:a
25 * Note that these should only be used in cases where a kernel built for an
26 * older ISA *cannot* run on a CPU which supports the feature in question. For
27 * example this may be used for features introduced with MIPSr6, since a kernel
28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
39 * These are for use with features that are optional up until a particular ISA
49 * These are for use with features that are optional up until a particular ISA
71 * SMP assumption: Options of CPU 0 are a superset of all processors.
96 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
102 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
210 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16)
213 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
216 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX)
219 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
222 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
226 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI)
266 * I-cache has a chance to see the new data at all. Then we have to flush the
281 # define cpu_has_mips_1 (MIPS_ISA_REV < 6)
284 # define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II)
287 # define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III)
290 # define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
293 # define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V)
296 # define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
299 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
302 # define cpu_has_mips32r5 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
305 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
309 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
313 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
317 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
320 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
355 /* MIPSR2 - MIPSR6 have a lot of similarities */
395 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
405 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
406 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
443 #define cpu_has_mipsmt __isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
447 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP)
451 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI)
555 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
558 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
566 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
570 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
595 * Some systems share FTLB RAMs between threads within a core (siblings in
597 * any point when an entry is evicted due to a sibling thread writing an entry
606 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
610 * Some systems take this a step further & share FTLB entries between siblings.
612 * written by a sibling exists in the shared FTLB for a translation which would
613 * otherwise cause a TLB refill exception then the CPU will use the entry
614 * written by its sibling rather than triggering a refill & writing a matching
617 * This is naturally only valid if a TLB entry is known to be suitable for use
618 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
619 * rather than ASIDs or when a TLB entry is marked global.
623 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
636 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
650 # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID)
681 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6))