68 	{ AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
69 	{ AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },
70 	{ AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
71 	{ AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8, 0x11400000, 0, 0 },
74 	{ AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
75 	{ AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
76 	{ AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
77 	{ AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
80 	{ AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN,  4, 8, 0x10200000, 0, 0 },
81 	{ AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
82 	{ AU1550_DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
83 	{ AU1550_DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
84 	{ AU1550_DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN,  4, 8, 0x10200010, 0, 0 },
85 	{ AU1550_DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN,  4, 8, 0x10200014, 0, 0 },
88 	{ AU1550_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
89 	{ AU1550_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,  0, 0, 0x11a0001c, 0, 0 },
90 	{ AU1550_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
91 	{ AU1550_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,  0, 0, 0x11b0001c, 0, 0 },
92 	{ AU1550_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
93 	{ AU1550_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,  0, 0, 0x10a0001c, 0, 0 },
94 	{ AU1550_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
95 	{ AU1550_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,  0, 0, 0x10b0001c, 0, 0 },
97 	{ AU1550_DSCR_CMD0_PCI_WRITE,  0, 0, 0, 0x00000000, 0, 0 },  /* PCI */
98 	{ AU1550_DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
100 	/* MAC 0 */
101 	{ AU1550_DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },
102 	{ AU1550_DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
105 	{ AU1550_DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN,  0, 0, 0x00000000, 0, 0 },
106 	{ AU1550_DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
108 	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
109 	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
113 	{ AU1200_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
114 	{ AU1200_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8, 0x11100000, 0, 0 },
115 	{ AU1200_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
116 	{ AU1200_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8, 0x11200000, 0, 0 },
118 	{ AU1200_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
119 	{ AU1200_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
121 	{ AU1200_DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
122 	{ AU1200_DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
123 	{ AU1200_DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
124 	{ AU1200_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
126 	{ AU1200_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
127 	{ AU1200_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8, 0x10600004, 0, 0 },
128 	{ AU1200_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
129 	{ AU1200_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  4, 8, 0x10680004, 0, 0 },
131 	{ AU1200_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
132 	{ AU1200_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
134 	{ AU1200_DSCR_CMD0_PSC0_TX,   DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 },
135 	{ AU1200_DSCR_CMD0_PSC0_RX,   DEV_FLAGS_IN,  0, 16, 0x11a0001c, 0, 0 },
136 	{ AU1200_DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
137 	{ AU1200_DSCR_CMD0_PSC1_TX,   DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 },
138 	{ AU1200_DSCR_CMD0_PSC1_RX,   DEV_FLAGS_IN,  0, 16, 0x11b0001c, 0, 0 },
139 	{ AU1200_DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
141 	{ AU1200_DSCR_CMD0_CIM_RXA,  DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
142 	{ AU1200_DSCR_CMD0_CIM_RXB,  DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
143 	{ AU1200_DSCR_CMD0_CIM_RXC,  DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
144 	{ AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
146 	{ AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
148 	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149 	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
153 	{ AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8,  0x10100004, 0, 0 },
154 	{ AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN,  0, 8,  0x10100000, 0, 0 },
155 	{ AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8,  0x10101004, 0, 0 },
156 	{ AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN,  0, 8,  0x10101000, 0, 0 },
157 	{ AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8,  0x10102004, 0, 0 },
158 	{ AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN,  0, 8,  0x10102000, 0, 0 },
159 	{ AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8,  0x10103004, 0, 0 },
160 	{ AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN,  0, 8,  0x10103000, 0, 0 },
162 	{ AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8,  0x10600000, 0, 0 },
163 	{ AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN,  4, 8,  0x10600004, 0, 0 },
164 	{ AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8,  0x10601000, 0, 0 },
165 	{ AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN,  8, 8,  0x10601004, 0, 0 },
167 	{ AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN ,   4, 32, 0x10300008, 0, 0 },
168 	{ AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT,   4, 32, 0x10300004, 0, 0 },
170 	{ AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0001c, 0, 0 },
171 	{ AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN,   0, 16, 0x10a0001c, 0, 0 },
172 	{ AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0101c, 0, 0 },
173 	{ AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN,   0, 16, 0x10a0101c, 0, 0 },
174 	{ AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0201c, 0, 0 },
175 	{ AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN,   0, 16, 0x10a0201c, 0, 0 },
176 	{ AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT,  0, 16, 0x10a0301c, 0, 0 },
177 	{ AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN,   0, 16, 0x10a0301c, 0, 0 },
179 	{ AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE,   0, 0,  0x00000000, 0, 0 },
180 	{ AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
182 	{ AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8,  0x10602000, 0, 0 },
183 	{ AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN,  4, 8,  0x10602004, 0, 0 },
185 	{ AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
187 	{ AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE,  0, 32, 0x14001810, 0, 0 },
189 	{ AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
190 	{ AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
192 	{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
193 	{ DSCR_CMD0_ALWAYS,   DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
205 	for (i = 0; i < DBDEV_TAB_SIZE; ++i) {  in find_dbdev_id()
221 	u32 ret = 0;  in au1xxx_ddma_add_device()
223 	static u16 new_id = 0x1000;  in au1xxx_ddma_add_device()
225 	p = find_dbdev_id(~0);  in au1xxx_ddma_add_device()
231 #if 0  in au1xxx_ddma_add_device()
246 		memset(p, 0, sizeof(dbdev_tab_t));  in au1xxx_ddma_del_device()
247 		p->dev_id = ~0;  in au1xxx_ddma_del_device()
270 		return 0;  in au1xxx_dbdma_chan_alloc()
274 		return 0;  in au1xxx_dbdma_chan_alloc()
277 		return 0;  in au1xxx_dbdma_chan_alloc()
279 	used = 0;  in au1xxx_dbdma_chan_alloc()
301 		return 0;  in au1xxx_dbdma_chan_alloc()
305 	chan = 0;  in au1xxx_dbdma_chan_alloc()
307 	for (i = 0; i < NUM_DBDMA_CHANS; i++)  in au1xxx_dbdma_chan_alloc()
320 		memset(ctp, 0, sizeof(chan_tab_t));  in au1xxx_dbdma_chan_alloc()
323 		dcp += (0x0100 * chan);  in au1xxx_dbdma_chan_alloc()
332 		i = 0;  in au1xxx_dbdma_chan_alloc()
358 	return 0;  in au1xxx_dbdma_chan_alloc()
375 	rv = 0;  in au1xxx_dbdma_set_devwidth()
417 	if (desc_base == 0)  in au1xxx_dbdma_ring_alloc()
418 		return 0;  in au1xxx_dbdma_ring_alloc()
420 	if (desc_base & 0x1f) {  in au1xxx_dbdma_ring_alloc()
429 		if (desc_base == 0)  in au1xxx_dbdma_ring_alloc()
430 			return 0;  in au1xxx_dbdma_ring_alloc()
446 	cmd0 = cmd1 = src1 = dest1 = 0;  in au1xxx_dbdma_ring_alloc()
447 	src0 = dest0 = 0;  in au1xxx_dbdma_ring_alloc()
558 #if 0  in au1xxx_dbdma_ring_alloc()
564 	for (i = 0; i < entries; i++) {  in au1xxx_dbdma_ring_alloc()
571 		dp->dscr_stat = 0;  in au1xxx_dbdma_ring_alloc()
572 		dp->sw_context = 0;  in au1xxx_dbdma_ring_alloc()
573 		dp->sw_status = 0;  in au1xxx_dbdma_ring_alloc()
615 		return 0;  in au1xxx_dbdma_put_source()
618 	dp->dscr_source0 = buf & ~0UL;  in au1xxx_dbdma_put_source()
637 	ctp->chan_ptr->ddma_dbell = 0;  in au1xxx_dbdma_put_source()
672 		return 0;  in au1xxx_dbdma_put_dest()
682 	dp->dscr_dest0 = buf & ~0UL;  in au1xxx_dbdma_put_dest()
684 #if 0  in au1xxx_dbdma_put_dest()
700 	ctp->chan_ptr->ddma_dbell = 0;  in au1xxx_dbdma_put_dest()
741 		return 0;  in au1xxx_dbdma_get_dest()
760 	int halt_timeout = 0;  in au1xxx_dbdma_stop()
796 	cp->ddma_dbell = 0;  in au1xxx_dbdma_start()
821 		dp->sw_status = 0;  in au1xxx_dbdma_reset()
882 	cp->ddma_irq = 0;  in dbdma_interrupt()
898 	u32 i		 = 0;  in au1xxx_dbdma_dump()
941 	u32 nbytes = 0;  in au1xxx_dbdma_put_dscr()
961 		return 0;  in au1xxx_dbdma_put_dscr()
973 	ctp->chan_ptr->ddma_dbell = 0;  in au1xxx_dbdma_put_dscr()
991 	alchemy_dbdma_pm_data[0][0] = __raw_readl(addr + 0x00);  in alchemy_dbdma_suspend()
992 	alchemy_dbdma_pm_data[0][1] = __raw_readl(addr + 0x04);  in alchemy_dbdma_suspend()
993 	alchemy_dbdma_pm_data[0][2] = __raw_readl(addr + 0x08);  in alchemy_dbdma_suspend()
994 	alchemy_dbdma_pm_data[0][3] = __raw_readl(addr + 0x0c);  in alchemy_dbdma_suspend()
999 		alchemy_dbdma_pm_data[i][0] = __raw_readl(addr + 0x00);  in alchemy_dbdma_suspend()
1000 		alchemy_dbdma_pm_data[i][1] = __raw_readl(addr + 0x04);  in alchemy_dbdma_suspend()
1001 		alchemy_dbdma_pm_data[i][2] = __raw_readl(addr + 0x08);  in alchemy_dbdma_suspend()
1002 		alchemy_dbdma_pm_data[i][3] = __raw_readl(addr + 0x0c);  in alchemy_dbdma_suspend()
1003 		alchemy_dbdma_pm_data[i][4] = __raw_readl(addr + 0x10);  in alchemy_dbdma_suspend()
1004 		alchemy_dbdma_pm_data[i][5] = __raw_readl(addr + 0x14);  in alchemy_dbdma_suspend()
1007 		__raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00);  in alchemy_dbdma_suspend()
1009 		while (!(__raw_readl(addr + 0x14) & 1))  in alchemy_dbdma_suspend()
1012 		addr += 0x100;	/* next channel base */  in alchemy_dbdma_suspend()
1016 	__raw_writel(0, addr + 0x0c);  in alchemy_dbdma_suspend()
1019 	return 0;  in alchemy_dbdma_suspend()
1028 	__raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00);  in alchemy_dbdma_resume()
1029 	__raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04);  in alchemy_dbdma_resume()
1030 	__raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08);  in alchemy_dbdma_resume()
1031 	__raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c);  in alchemy_dbdma_resume()
1036 		__raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00);  in alchemy_dbdma_resume()
1037 		__raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04);  in alchemy_dbdma_resume()
1038 		__raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08);  in alchemy_dbdma_resume()
1039 		__raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c);  in alchemy_dbdma_resume()
1040 		__raw_writel(alchemy_dbdma_pm_data[i][4], addr + 0x10);  in alchemy_dbdma_resume()
1041 		__raw_writel(alchemy_dbdma_pm_data[i][5], addr + 0x14);  in alchemy_dbdma_resume()
1043 		addr += 0x100;	/* next channel base */  in alchemy_dbdma_resume()
1062 		dbdev_tab[ret].dev_id = ~0;  in dbdma_setup()
1064 	dbdma_gptr->ddma_config = 0;  in dbdma_setup()
1065 	dbdma_gptr->ddma_throttle = 0;  in dbdma_setup()
1066 	dbdma_gptr->ddma_inten = 0xffff;  in dbdma_setup()
1069 	ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);  in dbdma_setup()
1090 	return 0;  in alchemy_dbdma_init()