253 static int loongarch_pmu_alloc_counter(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)  in loongarch_pmu_alloc_counter()  argument
300 				    struct hw_perf_event *hwc,  in loongarch_pmu_event_set_period()  argument
304 	u64 left = local64_read(&hwc->period_left);  in loongarch_pmu_event_set_period()
305 	u64 period = hwc->sample_period;  in loongarch_pmu_event_set_period()
310 		local64_set(&hwc->period_left, left);  in loongarch_pmu_event_set_period()
311 		hwc->last_period = period;  in loongarch_pmu_event_set_period()
316 		local64_set(&hwc->period_left, left);  in loongarch_pmu_event_set_period()
317 		hwc->last_period = period;  in loongarch_pmu_event_set_period()
323 		local64_set(&hwc->period_left, left);  in loongarch_pmu_event_set_period()
326 	local64_set(&hwc->prev_count, loongarch_pmu.overflow - left);  in loongarch_pmu_event_set_period()
336 				 struct hw_perf_event *hwc,  in loongarch_pmu_event_update()  argument
343 	prev_raw_count = local64_read(&hwc->prev_count);  in loongarch_pmu_event_update()
346 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,  in loongarch_pmu_event_update()
353 	local64_sub(delta, &hwc->period_left);  in loongarch_pmu_event_update()
358 	struct hw_perf_event *hwc = &event->hw;  in loongarch_pmu_start()  local
361 		WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));  in loongarch_pmu_start()
363 	hwc->state = 0;  in loongarch_pmu_start()
366 	loongarch_pmu_event_set_period(event, hwc, hwc->idx);  in loongarch_pmu_start()
369 	loongarch_pmu_enable_event(hwc, hwc->idx);  in loongarch_pmu_start()
374 	struct hw_perf_event *hwc = &event->hw;  in loongarch_pmu_stop()  local
376 	if (!(hwc->state & PERF_HES_STOPPED)) {  in loongarch_pmu_stop()
378 		loongarch_pmu_disable_event(hwc->idx);  in loongarch_pmu_stop()
380 		loongarch_pmu_event_update(event, hwc, hwc->idx);  in loongarch_pmu_stop()
381 		hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;  in loongarch_pmu_stop()
389 	struct hw_perf_event *hwc = &event->hw;  in loongarch_pmu_add()  local
394 	idx = loongarch_pmu_alloc_counter(cpuc, hwc);  in loongarch_pmu_add()
408 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;  in loongarch_pmu_add()
423 	struct hw_perf_event *hwc = &event->hw;  in loongarch_pmu_del()  local
424 	int idx = hwc->idx;  in loongarch_pmu_del()
437 	struct hw_perf_event *hwc = &event->hw;  in loongarch_pmu_read()  local
440 	if (hwc->idx < 0)  in loongarch_pmu_read()
443 	loongarch_pmu_event_update(event, hwc, hwc->idx);  in loongarch_pmu_read()
485 	struct hw_perf_event *hwc = &event->hw;  in handle_associated_event()  local
487 	loongarch_pmu_event_update(event, hwc, idx);  in handle_associated_event()
489 	if (!loongarch_pmu_event_set_period(event, hwc, idx))  in handle_associated_event()
750 	struct hw_perf_event *hwc = &event->hw;  in __hw_perf_event_init()  local
780 	hwc->config_base = CSR_PERFCTRL_IE;  in __hw_perf_event_init()
782 	hwc->event_base = loongarch_pmu_perf_event_encode(pev);  in __hw_perf_event_init()
787 		hwc->config_base |= CSR_PERFCTRL_PLV3;  in __hw_perf_event_init()
788 		hwc->config_base |= CSR_PERFCTRL_PLV2;  in __hw_perf_event_init()
791 		hwc->config_base |= CSR_PERFCTRL_PLV0;  in __hw_perf_event_init()
794 		hwc->config_base |= CSR_PERFCTRL_PLV1;  in __hw_perf_event_init()
797 	hwc->config_base &= M_PERFCTL_CONFIG_MASK;  in __hw_perf_event_init()
802 	hwc->idx = -1;  in __hw_perf_event_init()
803 	hwc->config = 0;  in __hw_perf_event_init()
805 	if (!hwc->sample_period) {  in __hw_perf_event_init()
806 		hwc->sample_period  = loongarch_pmu.max_period;  in __hw_perf_event_init()
807 		hwc->last_period    = hwc->sample_period;  in __hw_perf_event_init()
808 		local64_set(&hwc->period_left, hwc->sample_period);  in __hw_perf_event_init()