13 void simu_pc(struct pt_regs *regs, union loongarch_instruction insn)  in simu_pc()  argument
16 	unsigned int rd = insn.reg1i20_format.rd;  in simu_pc()
17 	unsigned int imm = insn.reg1i20_format.immediate;  in simu_pc()
24 	switch (insn.reg1i20_format.opcode) {  in simu_pc()
46 void simu_branch(struct pt_regs *regs, union loongarch_instruction insn)  in simu_branch()  argument
56 	imm_l = insn.reg0i26_format.immediate_l;  in simu_branch()
57 	imm_h = insn.reg0i26_format.immediate_h;  in simu_branch()
58 	switch (insn.reg0i26_format.opcode) {  in simu_branch()
68 	imm_l = insn.reg1i21_format.immediate_l;  in simu_branch()
69 	imm_h = insn.reg1i21_format.immediate_h;  in simu_branch()
70 	rj = insn.reg1i21_format.rj;  in simu_branch()
71 	switch (insn.reg1i21_format.opcode) {  in simu_branch()
86 	imm = insn.reg2i16_format.immediate;  in simu_branch()
87 	rj = insn.reg2i16_format.rj;  in simu_branch()
88 	rd = insn.reg2i16_format.rd;  in simu_branch()
89 	switch (insn.reg2i16_format.opcode) {  in simu_branch()
136 bool insns_not_supported(union loongarch_instruction insn)  in insns_not_supported()  argument
138 	switch (insn.reg3_format.opcode) {  in insns_not_supported()
144 	switch (insn.reg2i14_format.opcode) {  in insns_not_supported()
153 	switch (insn.reg1i21_format.opcode) {  in insns_not_supported()
162 bool insns_need_simulation(union loongarch_instruction insn)  in insns_need_simulation()  argument
164 	if (is_pc_ins(&insn))  in insns_need_simulation()
167 	if (is_branch_ins(&insn))  in insns_need_simulation()
173 void arch_simulate_insn(union loongarch_instruction insn, struct pt_regs *regs)  in arch_simulate_insn()  argument
175 	if (is_pc_ins(&insn))  in arch_simulate_insn()
176 		simu_pc(regs, insn);  in arch_simulate_insn()
177 	else if (is_branch_ins(&insn))  in arch_simulate_insn()
178 		simu_branch(regs, insn);  in arch_simulate_insn()
193 int larch_insn_write(void *addr, u32 insn)  in larch_insn_write()  argument
199 	ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);  in larch_insn_write()
205 int larch_insn_patch_text(void *addr, u32 insn)  in larch_insn_patch_text()  argument
213 	ret = larch_insn_write(tp, insn);  in larch_insn_patch_text()
229 	union loongarch_instruction insn;  in larch_insn_gen_b()  local
236 	emit_b(&insn, offset >> 2);  in larch_insn_gen_b()
238 	return insn.word;  in larch_insn_gen_b()
244 	union loongarch_instruction insn;  in larch_insn_gen_bl()  local
251 	emit_bl(&insn, offset >> 2);  in larch_insn_gen_bl()
253 	return insn.word;  in larch_insn_gen_bl()
258 	union loongarch_instruction insn;  in larch_insn_gen_break()  local
265 	emit_break(&insn, imm);  in larch_insn_gen_break()
267 	return insn.word;  in larch_insn_gen_break()
272 	union loongarch_instruction insn;  in larch_insn_gen_or()  local
274 	emit_or(&insn, rd, rj, rk);  in larch_insn_gen_or()
276 	return insn.word;  in larch_insn_gen_or()
286 	union loongarch_instruction insn;  in larch_insn_gen_lu12iw()  local
293 	emit_lu12iw(&insn, rd, imm);  in larch_insn_gen_lu12iw()
295 	return insn.word;  in larch_insn_gen_lu12iw()
300 	union loongarch_instruction insn;  in larch_insn_gen_lu32id()  local
307 	emit_lu32id(&insn, rd, imm);  in larch_insn_gen_lu32id()
309 	return insn.word;  in larch_insn_gen_lu32id()
314 	union loongarch_instruction insn;  in larch_insn_gen_lu52id()  local
321 	emit_lu52id(&insn, rd, rj, imm);  in larch_insn_gen_lu52id()
323 	return insn.word;  in larch_insn_gen_lu52id()
328 	union loongarch_instruction insn;  in larch_insn_gen_jirl()  local
335 	emit_jirl(&insn, rj, rd, imm >> 2);  in larch_insn_gen_jirl()
337 	return insn.word;  in larch_insn_gen_jirl()