Lines Matching +full:3 +full:d
32 * the prefetches. The four relevant points in the pipelined are called A, B, C, D:
35 * into L1D and p[D] is TRUE if a cacheline needs to be copied.
98 #define D (C + 3) macro
99 #define N (D + 1)
106 .rotr v[2*PREFETCH_DIST], n[D-C+1]
125 add src1 = 3*8, in1 // first t3 src
127 add dst1 = 3*8, in0 // first t3 dst
143 (p[D]) ld8 t2 = [src0], 3*8 // M0
144 (p[D]) ld8 t4 = [src1], 3*8 // M1
146 (p[D]) st8 [dst_pre_l2] = n[D-C], 128 // M3 prefetch dst from L2
150 (p[D]) st8 [dst0] = t1, 8 // M2
151 (p[D]) st8 [dst1] = t3, 8 // M3
153 (p[D]) ld8 t5 = [src0], 8
154 (p[D]) ld8 t7 = [src1], 3*8
155 (p[D]) st8 [dst0] = t2, 3*8
156 (p[D]) st8 [dst1] = t4, 3*8
158 (p[D]) ld8 t6 = [src0], 3*8
159 (p[D]) ld8 t10 = [src1], 8
160 (p[D]) st8 [dst0] = t5, 8
161 (p[D]) st8 [dst1] = t7, 3*8
163 (p[D]) ld8 t9 = [src0], 3*8
164 (p[D]) ld8 t11 = [src1], 3*8
165 (p[D]) st8 [dst0] = t6, 3*8
166 (p[D]) st8 [dst1] = t10, 8
168 (p[D]) ld8 t12 = [src0], 8
169 (p[D]) ld8 t14 = [src1], 8
170 (p[D]) st8 [dst0] = t9, 3*8
171 (p[D]) st8 [dst1] = t11, 3*8
173 (p[D]) ld8 t13 = [src0], 4*8
174 (p[D]) ld8 t15 = [src1], 4*8
175 (p[D]) st8 [dst0] = t12, 8
176 (p[D]) st8 [dst1] = t14, 8
178 (p[D-1])ld8 t1 = [src0], 8
179 (p[D-1])ld8 t3 = [src1], 8
180 (p[D]) st8 [dst0] = t13, 4*8
181 (p[D]) st8 [dst1] = t15, 4*8