Lines Matching refs:temp1
412 #define temp1 r2 /* careful, it overlaps with input registers */ macro
464 add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack
467 mov regs=temp1 // save the start of sos
468 st8 [temp1]=r1,16 // os_gp
471 st8 [temp1]=r9,16 // sal_proc
475 st8 [temp1]=r18 // proc_state_param
478 add temp1=SOS(SAL_RA), regs
481 st8 [temp1]=r12,16 // sal_ra
485 st8 [temp1]=r17,16 // pal_min_state
489 st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK
493 st8 [temp1]=r12,16 // cr.isr
497 st8 [temp1]=r12,16 // cr.itir
501 st8 [temp1]=r12 // cr.iim
505 add temp1=SOS(OS_STATUS), regs
509 st8 [temp1]=r12 // os_status, default is cold boot
518 add temp1=PT(B6), regs
523 st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6
529 st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd
534 st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat
539 st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat
548 st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs
552 st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv
555 stf.spill [temp1]=f7,PT(F9)-PT(F7)
558 stf.spill [temp1]=f9,PT(F11)-PT(F9)
561 stf.spill [temp1]=f11
567 add temp1=SW(F2), regs
570 stf.spill [temp1]=f2,32
573 stf.spill [temp1]=f4,32
576 stf.spill [temp1]=f12,32
579 stf.spill [temp1]=f14,32
582 stf.spill [temp1]=f16,32
585 stf.spill [temp1]=f18,32
588 stf.spill [temp1]=f20,32
591 stf.spill [temp1]=f22,32
594 stf.spill [temp1]=f24,32
597 stf.spill [temp1]=f26,32
600 stf.spill [temp1]=f28,32
603 stf.spill [temp1]=f30,SW(B2)-SW(F30)
608 st8 [temp1]=temp3,16 // save b2
613 st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4
617 st8 [temp1]=temp3 // save ar.lc
726 add temp1=SW(F2), regs
729 ldf.fill f2=[temp1],32
732 ldf.fill f4=[temp1],32
735 ldf.fill f12=[temp1],32
738 ldf.fill f14=[temp1],32
741 ldf.fill f16=[temp1],32
744 ldf.fill f18=[temp1],32
747 ldf.fill f20=[temp1],32
750 ldf.fill f22=[temp1],32
753 ldf.fill f24=[temp1],32
756 ldf.fill f26=[temp1],32
759 ldf.fill f28=[temp1],32
762 ldf.fill f30=[temp1],SW(B2)-SW(F30)
765 ld8 temp3=[temp1],16 // restore b2
770 ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4
775 ld8 temp3=[temp1] // restore ar.lc
783 add temp1=PT(B6), regs
786 ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6
791 ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd
796 ld8 temp3=[temp1] // restore ar.unat
797 add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1
803 ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv
808 ldf.fill f6=[temp1],PT(F8)-PT(F6)
811 ldf.fill f8=[temp1],PT(F10)-PT(F8)
814 ldf.fill f10=[temp1]
820 add temp1=SOS(SAL_RA), regs
823 ld8 r12=[temp1],16 // sal_ra
826 ld8 r22=[temp1],16 // pal_min_state, virtual
829 ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK
832 ld8 temp3=[temp1],16 // cr.isr
837 ld8 temp3=[temp1],16 // cr.itir
842 ld8 temp3=[temp1] // cr.iim
844 add temp1=SOS(OS_STATUS), regs
851 ld8 r8=[temp1] // os_status
920 GET_IA64_MCA_DATA(temp1)
923 add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack
924 add regs=regs, temp1 // struct pt_regs on MCA or INIT stack
930 dep temp1=-1,ms,62,2 // set region 6
933 st8 [temp2]=temp1 // pal_min_state, virtual
974 LOAD_PHYSICAL(p0,temp1,1f)
978 mov cr.iip=temp1
986 add temp1=PT(LOADRS), regs
988 ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs
990 ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore
994 ld8 temp4=[temp1] // restore ar.rnat
1023 GET_IA64_MCA_DATA(temp1)
1025 add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack
1026 add r13=temp1, r3 // set current to start of MCA/INIT stack
1027 add r20=temp1, r3 // physical start of MCA/INIT stack
1074 #undef temp1