Lines Matching +full:0 +full:x21
33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
41 .if \el == 0
65 tbnz x0, #THREAD_SHIFT, 0f
70 0:
126 nop // Patched to SMC/HVC #0
199 .if \el == 0
205 stp x0, x1, [sp, #16 * 0]
215 stp x20, x21, [sp, #16 * 10]
221 .if \el == 0
223 mrs x21, sp_el0
279 add x21, sp, #PT_REGS_SIZE
281 .endif /* \el == 0 */
284 stp lr, x21, [sp, #S_LR]
291 .if \el == 0
307 .if \el == 0
329 * x21 - aborted SP
336 .if \el != 0
356 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
364 .if \el == 0
409 apply_ssbd 0, x0, x1
412 msr elr_el1, x21 // set up the return data
414 ldp x0, x1, [sp, #16 * 0]
424 ldp x20, x21, [sp, #16 * 10]
430 .if \el == 0
472 mrs x21, ttbr0_el1
473 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
478 __uaccess_ttbr0_disable x21
489 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
527 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
528 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
529 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
530 kernel_ventry 0, t, 64, error // Error 64-bit EL0
532 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
533 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
534 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
535 kernel_ventry 0, t, 32, error // Error 32-bit EL0
574 .if \el == 0
595 entry_handler 0, t, 64, sync
596 entry_handler 0, t, 64, irq
597 entry_handler 0, t, 64, fiq
598 entry_handler 0, t, 64, error
600 entry_handler 0, t, 32, sync
601 entry_handler 0, t, 32, irq
602 entry_handler 0, t, 32, fiq
603 entry_handler 0, t, 32, error
615 kernel_exit 0
670 * instruction to load the upper 16 bits (which must be 0xFFFF).
678 #define BHB_MITIGATION_NONE 0
741 .space 0x400
794 tramp_ventry .Lvector_start\@, 64, 0, \bhb
797 tramp_ventry .Lvector_start\@, 32, 0, \bhb
827 stp x21, x22, [x8], #16
835 ldp x21, x22, [x8], #16
908 smc #0
910 99: hvc #0
983 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1034 and x0, x3, #0xc