Lines Matching full:4
86 * Op0 = 0, CRn = 4
95 #define PSTATE_PAN pstate_field(0, 4)
99 #define PSTATE_TCO pstate_field(3, 4)
118 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
121 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
124 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
154 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
170 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
171 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
172 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
174 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
180 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
186 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
187 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
192 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
195 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
221 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
224 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
229 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
246 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
249 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
251 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
252 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
253 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
271 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
298 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
299 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
301 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
309 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
310 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
311 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
312 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
313 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
314 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
315 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
323 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
331 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
366 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
385 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
396 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
397 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
403 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
419 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
425 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
444 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
482 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
483 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
485 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
486 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
487 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
488 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
489 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
490 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
491 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
493 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
494 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
495 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
496 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
497 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
499 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
500 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
501 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
502 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
503 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
504 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
505 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
506 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
507 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
508 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
509 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
510 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
512 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
513 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
515 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
516 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
518 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
519 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
520 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
521 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
522 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
528 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
534 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
536 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
537 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
538 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
539 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
540 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
541 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
543 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
548 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
553 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
558 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
563 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
564 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
566 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
567 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
574 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
575 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
591 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
603 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
604 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
605 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
606 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
607 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
608 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
671 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
672 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
673 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
674 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
675 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
676 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
677 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
678 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
679 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
680 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
681 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
682 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
683 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
684 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
685 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
686 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
687 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
688 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
689 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
690 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
691 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
692 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
693 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
694 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
695 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
696 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
697 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
698 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
699 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
700 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
701 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
702 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
703 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
704 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
705 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
707 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
708 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
709 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
710 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
712 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
713 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
715 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
716 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
717 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
719 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
720 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
721 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
722 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
723 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
724 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
726 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
727 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
730 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
739 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
741 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
773 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
951 #define ICH_VMCR_CBPR_SHIFT 4
995 #define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
997 #define ARM64_FEATURE_FIELD_BITS 4