Lines Matching +full:3 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
97 #define PSTATE_SSBS pstate_field(3, 1)
98 #define PSTATE_DIT pstate_field(3, 2)
99 #define PSTATE_TCO pstate_field(3, 4)
113 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
129 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
132 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
135 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
136 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
137 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
139 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
141 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
142 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
143 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
145 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
146 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
147 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
149 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
150 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
151 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
154 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
164 #include "asm/sysreg-defs.h"
170 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
171 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
172 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
181 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
183 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
186 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
189 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
191 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
192 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
193 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
200 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
202 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
203 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
205 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
206 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
207 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
209 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
210 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
211 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
216 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
217 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
218 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
219 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
221 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
228 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
229 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
232 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
235 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
251 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
256 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
258 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
264 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
266 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
267 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
268 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
273 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
274 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
275 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
277 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
278 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
279 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
281 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
283 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
285 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
286 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
287 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
288 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
290 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
291 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
292 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
293 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
295 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
296 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
298 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
299 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
301 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
303 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
304 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
305 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
307 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
308 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
309 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
310 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
311 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
312 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
313 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
314 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
315 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
316 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
317 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
318 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
319 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
320 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
321 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
323 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
351 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
352 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
354 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
356 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
357 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
359 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
360 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
362 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
363 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
364 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
365 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
366 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
370 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
371 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
375 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
376 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
377 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
378 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
379 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
380 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
381 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
382 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
383 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
384 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
385 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
386 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
387 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
388 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
390 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
392 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
394 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
396 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
397 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
399 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
400 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
401 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
402 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
403 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
405 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
406 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
407 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
408 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
409 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
410 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
411 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
413 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
414 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
415 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
417 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
420 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
424 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
427 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
428 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
433 * Counter: 11 011 1101 010:n<3> n<2:0>
434 * Type: 11 011 1101 011:n<3> n<2:0>
435 * n: 0-15
439 * Counter: 11 011 1101 110:n<3> n<2:0>
440 * Type: 11 011 1101 111:n<3> n<2:0>
441 * n: 0-15
444 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
445 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
446 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
447 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
453 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
455 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
457 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
458 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
459 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
461 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
462 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
463 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
465 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
466 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
475 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
476 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
477 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
478 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
480 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
482 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
483 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
485 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
486 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
487 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
488 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
489 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
490 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
491 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
493 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
494 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
495 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
496 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
497 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
499 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
500 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
501 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
502 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
503 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
504 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
505 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
506 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
507 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
508 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
509 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
510 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
512 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
513 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
515 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
516 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
518 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
519 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
520 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
521 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
522 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
526 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
528 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
532 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
534 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
536 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
537 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
538 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
539 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
540 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
541 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
543 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
547 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
553 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
557 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
563 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
564 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
566 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
567 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
570 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
571 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
572 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
573 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
574 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
575 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
576 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
577 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
578 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
579 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
580 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
581 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
582 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
583 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
584 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
585 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
586 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
587 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
588 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
589 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
591 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
600 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
601 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
602 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
614 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
618 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
621 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
622 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
623 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
624 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
625 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
626 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
628 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
632 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
638 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
641 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
642 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
643 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
644 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
645 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
646 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
647 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
648 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
649 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
650 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
651 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
652 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
653 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
654 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
655 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
656 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
657 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
661 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
662 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
663 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
664 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
665 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
666 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
667 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
668 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
669 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
670 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
682 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
683 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
684 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
685 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
686 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
690 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
704 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
705 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
707 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
708 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
709 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
710 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
712 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
713 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
715 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
716 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
717 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
719 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
720 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
721 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
722 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
723 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
724 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
726 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
727 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
730 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
741 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
742 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
743 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
767 #define SCTLR_ELx_SA (BIT(3))
881 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
912 #define TRFCR_EL2_CX BIT(3)
922 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
927 #define ICH_LR_STATE (3ULL << 62)
938 #define ICH_HCR_NPIE (1 << 3)
949 #define ICH_VMCR_FIQ_EN_SHIFT 3
953 #define ICH_VMCR_EOIM_SHIFT 9
1090 * set mask are set. Other bits are left as-is.