Lines Matching refs:x1
53 __check_hvhe .LnVHE_\@, x1
61 mrs x1, id_aa64dfr0_el1
62 sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
71 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
87 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4
104 mrs x1, id_aa64mmfr1_el1
105 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
140 mrs x1, mpidr_el1
142 msr vmpidr_el2, x1
147 __check_hvhe .LnVHE_\@, x1
159 mrs x1, id_aa64mmfr0_el1
160 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
161 cbz x1, .Lskip_fgt_\@
164 mrs x1, id_aa64dfr0_el1
165 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
166 cmp x1, #3
176 mrs x1, id_aa64pfr1_el1
177 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
178 cbz x1, .Lset_pie_fgt_\@
185 mrs_s x1, SYS_ID_AA64MMFR3_EL1
186 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
187 cbz x1, .Lset_fgt_\@
198 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
199 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
200 cbz x1, .Lskip_fgt_\@
272 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2
275 __check_hvhe .Lcptr_nvhe_\@, x1
289 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector
290 msr_s SYS_ZCR_EL2, x1 // length for EL1.
293 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2
296 __check_hvhe .Lcptr_nvhe_sme_\@, x1
311 mrs x1, sctlr_el2
312 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
313 msr sctlr_el2, x1
319 mrs_s x1, SYS_ID_AA64SMFR0_EL1
320 …erride id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2
327 mrs_s x1, SYS_ID_AA64SMFR0_EL1
328 …erride id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2
336 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported?
337 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1
338 cbz x1, .Lskip_sme_\@