Lines Matching +full:sci +full:- +full:intr
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "mmio-mux";
37 #mux-control-cells = <1>;
38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
44 ti,qsgmii-main-ports = <1>;
46 #phy-cells = <1>;
49 usb_serdes_mux: mux-controller@4000 {
50 compatible = "mmio-mux";
51 #mux-control-cells = <1>;
52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
56 gic500: interrupt-controller@1800000 {
57 compatible = "arm,gic-v3";
58 #address-cells = <2>;
59 #size-cells = <2>;
61 #interrupt-cells = <3>;
62 interrupt-controller;
72 gic_its: msi-controller@1820000 {
73 compatible = "arm,gic-v3-its";
75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
76 msi-controller;
77 #msi-cells = <1>;
81 main_gpio_intr: interrupt-controller@a00000 {
82 compatible = "ti,sci-intr";
84 ti,intr-trigger-type = <1>;
85 interrupt-controller;
86 interrupt-parent = <&gic500>;
87 #interrupt-cells = <1>;
88 ti,sci = <&dmsc>;
89 ti,sci-dev-id = <131>;
90 ti,interrupt-ranges = <8 392 56>;
94 compatible = "simple-mfd";
95 #address-cells = <2>;
96 #size-cells = <2>;
98 ti,sci-dev-id = <199>;
99 dma-coherent;
100 dma-ranges;
102 main_navss_intr: interrupt-controller@310e0000 {
103 compatible = "ti,sci-intr";
105 ti,intr-trigger-type = <4>;
106 interrupt-controller;
107 interrupt-parent = <&gic500>;
108 #interrupt-cells = <1>;
109 ti,sci = <&dmsc>;
110 ti,sci-dev-id = <213>;
111 ti,interrupt-ranges = <0 64 64>,
116 main_udmass_inta: msi-controller@33d00000 {
117 compatible = "ti,sci-inta";
119 interrupt-controller;
120 #interrupt-cells = <0>;
121 interrupt-parent = <&main_navss_intr>;
122 msi-controller;
123 ti,sci = <&dmsc>;
124 ti,sci-dev-id = <209>;
125 ti,interrupt-ranges = <0 0 256>;
129 compatible = "ti,am654-secure-proxy";
130 #mbox-cells = <1>;
131 reg-names = "target_data", "rt", "scfg";
135 interrupt-names = "rx_011";
140 compatible = "ti,am654-hwspinlock";
142 #hwlock-cells = <1>;
146 compatible = "ti,am654-mailbox";
148 #mbox-cells = <1>;
149 ti,mbox-num-users = <4>;
150 ti,mbox-num-fifos = <16>;
151 interrupt-parent = <&main_navss_intr>;
156 compatible = "ti,am654-mailbox";
158 #mbox-cells = <1>;
159 ti,mbox-num-users = <4>;
160 ti,mbox-num-fifos = <16>;
161 interrupt-parent = <&main_navss_intr>;
166 compatible = "ti,am654-mailbox";
168 #mbox-cells = <1>;
169 ti,mbox-num-users = <4>;
170 ti,mbox-num-fifos = <16>;
171 interrupt-parent = <&main_navss_intr>;
176 compatible = "ti,am654-mailbox";
178 #mbox-cells = <1>;
179 ti,mbox-num-users = <4>;
180 ti,mbox-num-fifos = <16>;
181 interrupt-parent = <&main_navss_intr>;
186 compatible = "ti,am654-mailbox";
188 #mbox-cells = <1>;
189 ti,mbox-num-users = <4>;
190 ti,mbox-num-fifos = <16>;
191 interrupt-parent = <&main_navss_intr>;
196 compatible = "ti,am654-mailbox";
198 #mbox-cells = <1>;
199 ti,mbox-num-users = <4>;
200 ti,mbox-num-fifos = <16>;
201 interrupt-parent = <&main_navss_intr>;
206 compatible = "ti,am654-mailbox";
208 #mbox-cells = <1>;
209 ti,mbox-num-users = <4>;
210 ti,mbox-num-fifos = <16>;
211 interrupt-parent = <&main_navss_intr>;
216 compatible = "ti,am654-mailbox";
218 #mbox-cells = <1>;
219 ti,mbox-num-users = <4>;
220 ti,mbox-num-fifos = <16>;
221 interrupt-parent = <&main_navss_intr>;
226 compatible = "ti,am654-mailbox";
228 #mbox-cells = <1>;
229 ti,mbox-num-users = <4>;
230 ti,mbox-num-fifos = <16>;
231 interrupt-parent = <&main_navss_intr>;
236 compatible = "ti,am654-mailbox";
238 #mbox-cells = <1>;
239 ti,mbox-num-users = <4>;
240 ti,mbox-num-fifos = <16>;
241 interrupt-parent = <&main_navss_intr>;
246 compatible = "ti,am654-mailbox";
248 #mbox-cells = <1>;
249 ti,mbox-num-users = <4>;
250 ti,mbox-num-fifos = <16>;
251 interrupt-parent = <&main_navss_intr>;
256 compatible = "ti,am654-mailbox";
258 #mbox-cells = <1>;
259 ti,mbox-num-users = <4>;
260 ti,mbox-num-fifos = <16>;
261 interrupt-parent = <&main_navss_intr>;
266 compatible = "ti,am654-navss-ringacc";
272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
273 ti,num-rings = <1024>;
274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
275 ti,sci = <&dmsc>;
276 ti,sci-dev-id = <211>;
277 msi-parent = <&main_udmass_inta>;
280 main_udmap: dma-controller@31150000 {
281 compatible = "ti,j721e-navss-main-udmap";
285 reg-names = "gcfg", "rchanrt", "tchanrt";
286 msi-parent = <&main_udmass_inta>;
287 #dma-cells = <1>;
289 ti,sci = <&dmsc>;
290 ti,sci-dev-id = <212>;
293 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
296 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
299 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
303 compatible = "ti,j721e-cpts";
305 reg-names = "cpts";
307 clock-names = "cpts";
308 interrupts-extended = <&main_navss_intr 391>;
309 interrupt-names = "cpts";
310 ti,cpts-periodic-outputs = <6>;
311 ti,cpts-ext-ts-inputs = <8>;
316 compatible = "ti,j7200-cpswxg-nuss";
317 #address-cells = <2>;
318 #size-cells = <2>;
320 reg-names = "cpsw_nuss";
323 clock-names = "fck";
324 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
335 dma-names = "tx0", "tx1", "tx2", "tx3",
341 ethernet-ports {
342 #address-cells = <1>;
343 #size-cells = <0>;
346 ti,mac-only;
353 ti,mac-only;
360 ti,mac-only;
367 ti,mac-only;
374 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
376 #address-cells = <1>;
377 #size-cells = <0>;
379 clock-names = "fck";
385 compatible = "ti,j721e-cpts";
388 clock-names = "cpts";
389 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "cpts";
391 ti,cpts-ext-ts-inputs = <4>;
392 ti,cpts-periodic-outputs = <2>;
398 compatible = "pinctrl-single";
400 #pinctrl-cells = <1>;
401 pinctrl-single,register-width = <32>;
402 pinctrl-single,function-mask = <0x000001ff>;
407 compatible = "pinctrl-single";
409 #pinctrl-cells = <1>;
410 pinctrl-single,register-width = <32>;
411 pinctrl-single,function-mask = <0x0000001f>;
415 compatible = "pinctrl-single";
418 #pinctrl-cells = <1>;
419 pinctrl-single,register-width = <32>;
420 pinctrl-single,function-mask = <0xffffffff>;
424 compatible = "pinctrl-single";
427 #pinctrl-cells = <1>;
428 pinctrl-single,register-width = <32>;
429 pinctrl-single,function-mask = <0xffffffff>;
433 compatible = "ti,j721e-uart", "ti,am654-uart";
436 clock-frequency = <48000000>;
437 current-speed = <115200>;
438 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
440 clock-names = "fclk";
445 compatible = "ti,j721e-uart", "ti,am654-uart";
448 clock-frequency = <48000000>;
449 current-speed = <115200>;
450 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
452 clock-names = "fclk";
457 compatible = "ti,j721e-uart", "ti,am654-uart";
460 clock-frequency = <48000000>;
461 current-speed = <115200>;
462 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
464 clock-names = "fclk";
469 compatible = "ti,j721e-uart", "ti,am654-uart";
472 clock-frequency = <48000000>;
473 current-speed = <115200>;
474 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
476 clock-names = "fclk";
481 compatible = "ti,j721e-uart", "ti,am654-uart";
484 clock-frequency = <48000000>;
485 current-speed = <115200>;
486 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
488 clock-names = "fclk";
493 compatible = "ti,j721e-uart", "ti,am654-uart";
496 clock-frequency = <48000000>;
497 current-speed = <115200>;
498 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
500 clock-names = "fclk";
505 compatible = "ti,j721e-uart", "ti,am654-uart";
508 clock-frequency = <48000000>;
509 current-speed = <115200>;
510 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
512 clock-names = "fclk";
517 compatible = "ti,j721e-uart", "ti,am654-uart";
520 clock-frequency = <48000000>;
521 current-speed = <115200>;
522 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
524 clock-names = "fclk";
529 compatible = "ti,j721e-uart", "ti,am654-uart";
532 clock-frequency = <48000000>;
533 current-speed = <115200>;
534 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
536 clock-names = "fclk";
541 compatible = "ti,j721e-uart", "ti,am654-uart";
544 clock-frequency = <48000000>;
545 current-speed = <115200>;
546 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
548 clock-names = "fclk";
553 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
556 #address-cells = <1>;
557 #size-cells = <0>;
558 clock-names = "fck";
560 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
565 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
568 #address-cells = <1>;
569 #size-cells = <0>;
570 clock-names = "fck";
572 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
577 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
580 #address-cells = <1>;
581 #size-cells = <0>;
582 clock-names = "fck";
584 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
589 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 clock-names = "fck";
596 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
601 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
604 #address-cells = <1>;
605 #size-cells = <0>;
606 clock-names = "fck";
608 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
613 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 clock-names = "fck";
620 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
625 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 clock-names = "fck";
632 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
637 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
640 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
641 clock-names = "clk_ahb", "clk_xin";
643 ti,otap-del-sel-legacy = <0x0>;
644 ti,otap-del-sel-mmc-hs = <0x0>;
645 ti,otap-del-sel-ddr52 = <0x6>;
646 ti,otap-del-sel-hs200 = <0x8>;
647 ti,otap-del-sel-hs400 = <0x5>;
648 ti,itap-del-sel-legacy = <0x10>;
649 ti,itap-del-sel-mmc-hs = <0xa>;
650 ti,strobe-sel = <0x77>;
651 ti,clkbuf-sel = <0x7>;
652 ti,trm-icp = <0x8>;
653 bus-width = <8>;
654 mmc-ddr-1_8v;
655 mmc-hs200-1_8v;
656 mmc-hs400-1_8v;
657 dma-coherent;
662 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
665 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
666 clock-names = "clk_ahb", "clk_xin";
668 ti,otap-del-sel-legacy = <0x0>;
669 ti,otap-del-sel-sd-hs = <0x0>;
670 ti,otap-del-sel-sdr12 = <0xf>;
671 ti,otap-del-sel-sdr25 = <0xf>;
672 ti,otap-del-sel-sdr50 = <0xc>;
673 ti,otap-del-sel-sdr104 = <0x5>;
674 ti,otap-del-sel-ddr50 = <0xc>;
675 ti,itap-del-sel-legacy = <0x0>;
676 ti,itap-del-sel-sd-hs = <0x0>;
677 ti,itap-del-sel-sdr12 = <0x0>;
678 ti,itap-del-sel-sdr25 = <0x0>;
679 ti,clkbuf-sel = <0x7>;
680 ti,trm-icp = <0x8>;
681 dma-coherent;
686 compatible = "ti,j721e-wiz-10g";
687 #address-cells = <1>;
688 #size-cells = <1>;
689 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
691 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
692 num-lanes = <4>;
693 #reset-cells = <1>;
696 assigned-clocks = <&k3_clks 292 85>;
697 assigned-clock-parents = <&k3_clks 292 89>;
699 wiz0_pll0_refclk: pll0-refclk {
701 clock-output-names = "wiz0_pll0_refclk";
702 #clock-cells = <0>;
703 assigned-clocks = <&wiz0_pll0_refclk>;
704 assigned-clock-parents = <&k3_clks 292 85>;
707 wiz0_pll1_refclk: pll1-refclk {
709 clock-output-names = "wiz0_pll1_refclk";
710 #clock-cells = <0>;
711 assigned-clocks = <&wiz0_pll1_refclk>;
712 assigned-clock-parents = <&k3_clks 292 85>;
715 wiz0_refclk_dig: refclk-dig {
717 clock-output-names = "wiz0_refclk_dig";
718 #clock-cells = <0>;
719 assigned-clocks = <&wiz0_refclk_dig>;
720 assigned-clock-parents = <&k3_clks 292 85>;
723 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
725 #clock-cells = <0>;
729 compatible = "ti,j721e-serdes-10g";
731 reg-names = "torrent_phy";
733 reset-names = "torrent_reset";
735 clock-names = "refclk";
736 #address-cells = <1>;
737 #size-cells = <0>;
742 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
747 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
748 interrupt-names = "link_state";
751 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
752 max-link-speed = <3>;
753 num-lanes = <4>;
754 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
756 clock-names = "fck";
757 #address-cells = <3>;
758 #size-cells = <2>;
759 bus-range = <0x0 0xff>;
760 cdns,no-bar-match-nbits = <64>;
761 vendor-id = <0x104c>;
762 device-id = <0xb00f>;
763 msi-map = <0x0 &gic_its 0x0 0x10000>;
764 dma-coherent;
767 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
770 pcie1_ep: pcie-ep@2910000 {
771 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
776 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
777 interrupt-names = "link_state";
779 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
780 max-link-speed = <3>;
781 num-lanes = <4>;
782 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
784 clock-names = "fck";
785 max-functions = /bits/ 8 <6>;
786 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
787 dma-coherent;
790 usbss0: cdns-usb@4104000 {
791 compatible = "ti,j721e-usb";
793 dma-coherent;
794 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
796 clock-names = "ref", "lpm";
797 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
798 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
799 #address-cells = <2>;
800 #size-cells = <2>;
808 reg-names = "otg", "xhci", "dev";
812 interrupt-names = "host",
815 maximum-speed = "super-speed";
817 cdns,phyrst-a-enable;
822 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
824 gpio-controller;
825 #gpio-cells = <2>;
826 interrupt-parent = <&main_gpio_intr>;
829 interrupt-controller;
830 #interrupt-cells = <2>;
832 ti,davinci-gpio-unbanked = <0>;
833 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
835 clock-names = "gpio";
840 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
842 gpio-controller;
843 #gpio-cells = <2>;
844 interrupt-parent = <&main_gpio_intr>;
847 interrupt-controller;
848 #interrupt-cells = <2>;
850 ti,davinci-gpio-unbanked = <0>;
851 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
853 clock-names = "gpio";
858 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
860 gpio-controller;
861 #gpio-cells = <2>;
862 interrupt-parent = <&main_gpio_intr>;
865 interrupt-controller;
866 #interrupt-cells = <2>;
868 ti,davinci-gpio-unbanked = <0>;
869 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
871 clock-names = "gpio";
876 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
878 gpio-controller;
879 #gpio-cells = <2>;
880 interrupt-parent = <&main_gpio_intr>;
883 interrupt-controller;
884 #interrupt-cells = <2>;
886 ti,davinci-gpio-unbanked = <0>;
887 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
889 clock-names = "gpio";
894 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
897 #address-cells = <1>;
898 #size-cells = <0>;
899 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
905 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
908 #address-cells = <1>;
909 #size-cells = <0>;
910 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
916 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
919 #address-cells = <1>;
920 #size-cells = <0>;
921 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
927 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
930 #address-cells = <1>;
931 #size-cells = <0>;
932 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
938 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
941 #address-cells = <1>;
942 #size-cells = <0>;
943 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
949 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
952 #address-cells = <1>;
953 #size-cells = <0>;
954 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
960 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
963 #address-cells = <1>;
964 #size-cells = <0>;
965 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
971 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
974 #address-cells = <1>;
975 #size-cells = <0>;
976 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
982 compatible = "ti,j7-rti-wdt";
985 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
986 assigned-clocks = <&k3_clks 252 1>;
987 assigned-clock-parents = <&k3_clks 252 5>;
991 compatible = "ti,j7-rti-wdt";
994 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
995 assigned-clocks = <&k3_clks 253 1>;
996 assigned-clock-parents = <&k3_clks 253 5>;
1000 compatible = "ti,am654-timer";
1004 clock-names = "fck";
1005 assigned-clocks = <&k3_clks 49 1>;
1006 assigned-clock-parents = <&k3_clks 49 2>;
1007 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1008 ti,timer-pwm;
1012 compatible = "ti,am654-timer";
1016 clock-names = "fck";
1017 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1018 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1019 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1020 ti,timer-pwm;
1024 compatible = "ti,am654-timer";
1028 clock-names = "fck";
1029 assigned-clocks = <&k3_clks 51 1>;
1030 assigned-clock-parents = <&k3_clks 51 2>;
1031 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1032 ti,timer-pwm;
1036 compatible = "ti,am654-timer";
1040 clock-names = "fck";
1041 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1042 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1043 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1044 ti,timer-pwm;
1048 compatible = "ti,am654-timer";
1052 clock-names = "fck";
1053 assigned-clocks = <&k3_clks 53 1>;
1054 assigned-clock-parents = <&k3_clks 53 2>;
1055 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1056 ti,timer-pwm;
1060 compatible = "ti,am654-timer";
1064 clock-names = "fck";
1065 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1066 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1067 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1068 ti,timer-pwm;
1072 compatible = "ti,am654-timer";
1076 clock-names = "fck";
1077 assigned-clocks = <&k3_clks 55 1>;
1078 assigned-clock-parents = <&k3_clks 55 2>;
1079 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1080 ti,timer-pwm;
1084 compatible = "ti,am654-timer";
1088 clock-names = "fck";
1089 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1090 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1091 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1092 ti,timer-pwm;
1096 compatible = "ti,am654-timer";
1100 clock-names = "fck";
1101 assigned-clocks = <&k3_clks 58 1>;
1102 assigned-clock-parents = <&k3_clks 58 2>;
1103 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1104 ti,timer-pwm;
1108 compatible = "ti,am654-timer";
1112 clock-names = "fck";
1113 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1114 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1115 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1116 ti,timer-pwm;
1120 compatible = "ti,am654-timer";
1124 clock-names = "fck";
1125 assigned-clocks = <&k3_clks 60 1>;
1126 assigned-clock-parents = <&k3_clks 60 2>;
1127 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1128 ti,timer-pwm;
1132 compatible = "ti,am654-timer";
1136 clock-names = "fck";
1137 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1138 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1139 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1140 ti,timer-pwm;
1144 compatible = "ti,am654-timer";
1148 clock-names = "fck";
1149 assigned-clocks = <&k3_clks 63 1>;
1150 assigned-clock-parents = <&k3_clks 63 2>;
1151 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1152 ti,timer-pwm;
1156 compatible = "ti,am654-timer";
1160 clock-names = "fck";
1161 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1162 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1163 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1164 ti,timer-pwm;
1168 compatible = "ti,am654-timer";
1172 clock-names = "fck";
1173 assigned-clocks = <&k3_clks 65 1>;
1174 assigned-clock-parents = <&k3_clks 65 2>;
1175 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1176 ti,timer-pwm;
1180 compatible = "ti,am654-timer";
1184 clock-names = "fck";
1185 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1186 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1187 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1188 ti,timer-pwm;
1192 compatible = "ti,am654-timer";
1196 clock-names = "fck";
1197 assigned-clocks = <&k3_clks 67 1>;
1198 assigned-clock-parents = <&k3_clks 67 2>;
1199 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1200 ti,timer-pwm;
1204 compatible = "ti,am654-timer";
1208 clock-names = "fck";
1209 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1210 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1211 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1212 ti,timer-pwm;
1216 compatible = "ti,am654-timer";
1220 clock-names = "fck";
1221 assigned-clocks = <&k3_clks 69 1>;
1222 assigned-clock-parents = <&k3_clks 69 2>;
1223 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1224 ti,timer-pwm;
1228 compatible = "ti,am654-timer";
1232 clock-names = "fck";
1233 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1234 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1235 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1236 ti,timer-pwm;
1240 compatible = "ti,j7200-r5fss";
1241 ti,cluster-mode = <1>;
1242 #address-cells = <1>;
1243 #size-cells = <1>;
1246 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1249 compatible = "ti,j7200-r5f";
1252 reg-names = "atcm", "btcm";
1253 ti,sci = <&dmsc>;
1254 ti,sci-dev-id = <245>;
1255 ti,sci-proc-ids = <0x06 0xff>;
1257 firmware-name = "j7200-main-r5f0_0-fw";
1258 ti,atcm-enable = <1>;
1259 ti,btcm-enable = <1>;
1264 compatible = "ti,j7200-r5f";
1267 reg-names = "atcm", "btcm";
1268 ti,sci = <&dmsc>;
1269 ti,sci-dev-id = <246>;
1270 ti,sci-proc-ids = <0x07 0xff>;
1272 firmware-name = "j7200-main-r5f0_1-fw";
1273 ti,atcm-enable = <1>;
1274 ti,btcm-enable = <1>;
1280 compatible = "ti,j721e-esm";
1282 ti,esm-pins = <656>, <657>;