Lines Matching +full:0 +full:x3000
18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
122 arm,psci-suspend-param = <0x00010000>;
159 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
160 <0x0 0x12040000 0 0x100000>; /* GICR */
165 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
174 reg = <0 0x20100000 0 0x4000>;
177 ranges = <0 0 0x20100000 0x4000>;
179 apahb_gate: clock-controller@0 {
181 reg = <0x0 0x3000>;
191 reg = <0 0x31050000 0 0x9000>;
197 reg = <0 0x322a0000 0 0x8000>;
203 reg = <0 0x32310000 0 0x1000>;
209 reg = <0 0x32320000 0 0x1000>;
215 reg = <0 0x32330000 0 0x1000>;
221 reg = <0 0x32340000 0 0x1000>;
227 reg = <0 0x32350000 0 0x1000>;
233 reg = <0 0x32360000 0 0x1000>;
239 reg = <0 0x32390000 0 0x3000>;
242 ranges = <0 0 0x32390000 0x3000>;
244 dpll0: clock-controller@0 {
246 reg = <0x0 0x100>;
254 reg = <0 0x323b0000 0 0x3000>;
257 ranges = <0 0 0x323b0000 0x3000>;
259 mpll1: clock-controller@0 {
261 reg = <0x0 0x100>;
269 reg = <0 0x323c0000 0 0x3000>;
272 ranges = <0 0 0x323c0000 0x3000>;
274 pll1: clock-controller@0 {
276 reg = <0x0 0x3000>;
286 reg = <0 0x323e0000 0 0x3000>;
289 ranges = <0 0 0x323e0000 0x3000>;
291 pll2: clock-controller@0 {
293 reg = <0x0 0x100>;
302 reg = <0 0x323f0000 0 0x3000>;
308 reg = <0 0x327d0000 0 0x3000>;
311 ranges = <0 0 0x327d0000 0x3000>;
313 aonapb_gate: clock-controller@0 {
315 reg = <0x0 0x3000>;
325 reg = <0 0x327e0000 0 0x3000>;
328 ranges = <0 0 0x327e0000 0x3000>;
330 pmu_gate: clock-controller@0 {
332 reg = <0x0 0x3000>;
342 reg = <0 0x3350d000 0 0x1000>;
345 ranges = <0 0 0x3350d000 0x1000>;
347 audcpapb_gate: clock-controller@0 {
349 reg = <0x0 0x300>;
357 reg = <0 0x335e0000 0 0x1000>;
360 ranges = <0 0 0x335e0000 0x1000>;
362 audcpahb_gate: clock-controller@0 {
364 reg = <0x0 0x300>;
372 reg = <0 0x60100000 0 0x3000>;
375 ranges = <0 0 0x60100000 0x3000>;
377 gpu_clk: clock-controller@0 {
381 reg = <0x0 0x100>;
389 reg = <0 0x60110000 0 0x3000>;
395 reg = <0 0x62200000 0 0x3000>;
398 ranges = <0 0 0x62200000 0x3000>;
400 mm_gate: clock-controller@0 {
402 reg = <0x0 0x3000>;
410 reg = <0 0x71000000 0 0x3000>;
413 ranges = <0 0 0x71000000 0x3000>;
415 apapb_gate: clock-controller@0 {
417 reg = <0x0 0x3000>;
424 reg = <0 0x20200000 0 0x1000>;
432 reg = <0 0x32080000 0 0x1000>;
442 reg = <0 0x62100000 0 0x1000>;
451 reg = <0 0x3c002000 0 0x1000>;
465 #size-cells = <0>;
480 reg = <0 0x3c003000 0 0x1000>;
497 reg = <0 0x3e001000 0 0x1000>;
512 #size-cells = <0>;
514 port@0 {
515 reg = <0>;
547 reg = <0 0x3e002000 0 0x1000>;
573 reg = <0 0x3e003000 0 0x1000>;
599 reg = <0 0x3e004000 0 0x1000>;
614 #size-cells = <0>;
616 port@0 {
617 reg = <0>;
635 reg = <0 0x3e005000 0 0x1000>;
649 #size-cells = <0>;
651 port@0 {
652 reg = <0>;
683 reg = <0 0x3f040000 0 0x1000>;
700 reg = <0 0x3f140000 0 0x1000>;
717 reg = <0 0x3f240000 0 0x1000>;
734 reg = <0 0x3f340000 0 0x1000>;
751 reg = <0 0x3f440000 0 0x1000>;
768 reg = <0 0x3f540000 0 0x1000>;
785 reg = <0 0x3f640000 0 0x1000>;
802 reg = <0 0x3f740000 0 0x1000>;
821 ranges = <0 0x0 0x70000000 0x10000000>;
823 uart0: serial@0 {
826 reg = <0x0 0x100>;
835 reg = <0x100000 0x100>;
843 reg = <0x1100000 0x1000>;
855 reg = <0x1400000 0x1000>;
870 ranges = <0 0x0 0x32000000 0x1000000>;
874 reg = <0x100000 0x100000>;
876 #size-cells = <0>;
877 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
878 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
879 <35 0x19b8>, <39 0x19ac>;
886 #clock-cells = <0>;
893 #clock-cells = <0>;
900 #clock-cells = <0>;
907 #clock-cells = <0>;