Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
60 compatible = "arm,cortex-a55";
61 reg = <0x0>;
62 enable-method = "psci";
63 capacity-dmips-mhz = <530>;
65 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
66 assigned-clock-rates = <816000000>;
67 cpu-idle-states = <&CPU_SLEEP>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <128>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&l2_cache_l0>;
75 dynamic-power-coefficient = <228>;
76 #cooling-cells = <2>;
81 compatible = "arm,cortex-a55";
82 reg = <0x100>;
83 enable-method = "psci";
84 capacity-dmips-mhz = <530>;
86 cpu-idle-states = <&CPU_SLEEP>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_cache_l1>;
94 dynamic-power-coefficient = <228>;
95 #cooling-cells = <2>;
100 compatible = "arm,cortex-a55";
101 reg = <0x200>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <530>;
105 cpu-idle-states = <&CPU_SLEEP>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_cache_l2>;
113 dynamic-power-coefficient = <228>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a55";
120 reg = <0x300>;
121 enable-method = "psci";
122 capacity-dmips-mhz = <530>;
124 cpu-idle-states = <&CPU_SLEEP>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_cache_l3>;
132 dynamic-power-coefficient = <228>;
133 #cooling-cells = <2>;
138 compatible = "arm,cortex-a76";
139 reg = <0x400>;
140 enable-method = "psci";
141 capacity-dmips-mhz = <1024>;
143 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
144 assigned-clock-rates = <816000000>;
145 cpu-idle-states = <&CPU_SLEEP>;
146 i-cache-size = <65536>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <65536>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&l2_cache_b0>;
153 dynamic-power-coefficient = <416>;
154 #cooling-cells = <2>;
159 compatible = "arm,cortex-a76";
160 reg = <0x500>;
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
164 cpu-idle-states = <&CPU_SLEEP>;
165 i-cache-size = <65536>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <65536>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 next-level-cache = <&l2_cache_b1>;
172 dynamic-power-coefficient = <416>;
173 #cooling-cells = <2>;
178 compatible = "arm,cortex-a76";
179 reg = <0x600>;
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
183 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
184 assigned-clock-rates = <816000000>;
185 cpu-idle-states = <&CPU_SLEEP>;
186 i-cache-size = <65536>;
187 i-cache-line-size = <64>;
188 i-cache-sets = <256>;
189 d-cache-size = <65536>;
190 d-cache-line-size = <64>;
191 d-cache-sets = <256>;
192 next-level-cache = <&l2_cache_b2>;
193 dynamic-power-coefficient = <416>;
194 #cooling-cells = <2>;
199 compatible = "arm,cortex-a76";
200 reg = <0x700>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
204 cpu-idle-states = <&CPU_SLEEP>;
205 i-cache-size = <65536>;
206 i-cache-line-size = <64>;
207 i-cache-sets = <256>;
208 d-cache-size = <65536>;
209 d-cache-line-size = <64>;
210 d-cache-sets = <256>;
211 next-level-cache = <&l2_cache_b3>;
212 dynamic-power-coefficient = <416>;
213 #cooling-cells = <2>;
216 idle-states {
217 entry-method = "psci";
218 CPU_SLEEP: cpu-sleep {
219 compatible = "arm,idle-state";
220 local-timer-stop;
221 arm,psci-suspend-param = <0x0010000>;
222 entry-latency-us = <100>;
223 exit-latency-us = <120>;
224 min-residency-us = <1000>;
228 l2_cache_l0: l2-cache-l0 {
230 cache-size = <131072>;
231 cache-line-size = <64>;
232 cache-sets = <512>;
233 cache-level = <2>;
234 cache-unified;
235 next-level-cache = <&l3_cache>;
238 l2_cache_l1: l2-cache-l1 {
240 cache-size = <131072>;
241 cache-line-size = <64>;
242 cache-sets = <512>;
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&l3_cache>;
248 l2_cache_l2: l2-cache-l2 {
250 cache-size = <131072>;
251 cache-line-size = <64>;
252 cache-sets = <512>;
253 cache-level = <2>;
254 cache-unified;
255 next-level-cache = <&l3_cache>;
258 l2_cache_l3: l2-cache-l3 {
260 cache-size = <131072>;
261 cache-line-size = <64>;
262 cache-sets = <512>;
263 cache-level = <2>;
264 cache-unified;
265 next-level-cache = <&l3_cache>;
268 l2_cache_b0: l2-cache-b0 {
270 cache-size = <524288>;
271 cache-line-size = <64>;
272 cache-sets = <1024>;
273 cache-level = <2>;
274 cache-unified;
275 next-level-cache = <&l3_cache>;
278 l2_cache_b1: l2-cache-b1 {
280 cache-size = <524288>;
281 cache-line-size = <64>;
282 cache-sets = <1024>;
283 cache-level = <2>;
284 cache-unified;
285 next-level-cache = <&l3_cache>;
288 l2_cache_b2: l2-cache-b2 {
290 cache-size = <524288>;
291 cache-line-size = <64>;
292 cache-sets = <1024>;
293 cache-level = <2>;
294 cache-unified;
295 next-level-cache = <&l3_cache>;
298 l2_cache_b3: l2-cache-b3 {
300 cache-size = <524288>;
301 cache-line-size = <64>;
302 cache-sets = <1024>;
303 cache-level = <2>;
304 cache-unified;
305 next-level-cache = <&l3_cache>;
308 l3_cache: l3-cache {
310 cache-size = <3145728>;
311 cache-line-size = <64>;
312 cache-sets = <4096>;
313 cache-level = <3>;
314 cache-unified;
320 compatible = "linaro,optee-tz";
325 compatible = "arm,scmi-smc";
326 arm,smc-id = <0x82000010>;
328 #address-cells = <1>;
329 #size-cells = <0>;
332 reg = <0x14>;
333 #clock-cells = <1>;
337 reg = <0x16>;
338 #reset-cells = <1>;
343 pmu-a55 {
344 compatible = "arm,cortex-a55-pmu";
348 pmu-a76 {
349 compatible = "arm,cortex-a76-pmu";
354 compatible = "arm,psci-1.0";
358 spll: clock-0 {
359 compatible = "fixed-clock";
360 clock-frequency = <702000000>;
361 clock-output-names = "spll";
362 #clock-cells = <0>;
366 compatible = "arm,armv8-timer";
372 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
375 xin24m: clock-1 {
376 compatible = "fixed-clock";
377 clock-frequency = <24000000>;
378 clock-output-names = "xin24m";
379 #clock-cells = <0>;
382 xin32k: clock-2 {
383 compatible = "fixed-clock";
384 clock-frequency = <32768>;
385 clock-output-names = "xin32k";
386 #clock-cells = <0>;
390 compatible = "mmio-sram";
391 reg = <0x0 0x0010f000 0x0 0x100>;
393 #address-cells = <1>;
394 #size-cells = <1>;
397 compatible = "arm,scmi-shmem";
398 reg = <0x0 0x100>;
403 compatible = "rockchip,rk3588-ehci", "generic-ehci";
404 reg = <0x0 0xfc800000 0x0 0x40000>;
408 phy-names = "usb";
409 power-domains = <&power RK3588_PD_USB>;
414 compatible = "rockchip,rk3588-ohci", "generic-ohci";
415 reg = <0x0 0xfc840000 0x0 0x40000>;
419 phy-names = "usb";
420 power-domains = <&power RK3588_PD_USB>;
425 compatible = "rockchip,rk3588-ehci", "generic-ehci";
426 reg = <0x0 0xfc880000 0x0 0x40000>;
430 phy-names = "usb";
431 power-domains = <&power RK3588_PD_USB>;
436 compatible = "rockchip,rk3588-ohci", "generic-ohci";
437 reg = <0x0 0xfc8c0000 0x0 0x40000>;
441 phy-names = "usb";
442 power-domains = <&power RK3588_PD_USB>;
447 compatible = "rockchip,rk3588-sys-grf", "syscon";
448 reg = <0x0 0xfd58c000 0x0 0x1000>;
452 compatible = "rockchip,rk3588-php-grf", "syscon";
453 reg = <0x0 0xfd5b0000 0x0 0x1000>;
457 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
458 reg = <0x0 0xfd5bc000 0x0 0x100>;
462 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
463 reg = <0x0 0xfd5c4000 0x0 0x100>;
467 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
468 reg = <0x0 0xfd5d8000 0x0 0x4000>;
469 #address-cells = <1>;
470 #size-cells = <1>;
472 u2phy2: usb2-phy@8000 {
473 compatible = "rockchip,rk3588-usb2phy";
474 reg = <0x8000 0x10>;
477 reset-names = "phy", "apb";
479 clock-names = "phyclk";
480 clock-output-names = "usb480m_phy2";
481 #clock-cells = <0>;
484 u2phy2_host: host-port {
485 #phy-cells = <0>;
492 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
493 reg = <0x0 0xfd5dc000 0x0 0x4000>;
494 #address-cells = <1>;
495 #size-cells = <1>;
497 u2phy3: usb2-phy@c000 {
498 compatible = "rockchip,rk3588-usb2phy";
499 reg = <0xc000 0x10>;
502 reset-names = "phy", "apb";
504 clock-names = "phyclk";
505 clock-output-names = "usb480m_phy3";
506 #clock-cells = <0>;
509 u2phy3_host: host-port {
510 #phy-cells = <0>;
517 compatible = "rockchip,rk3588-ioc", "syscon";
518 reg = <0x0 0xfd5f0000 0x0 0x10000>;
522 compatible = "mmio-sram";
523 reg = <0x0 0xfd600000 0x0 0x100000>;
525 #address-cells = <1>;
526 #size-cells = <1>;
529 cru: clock-controller@fd7c0000 {
530 compatible = "rockchip,rk3588-cru";
531 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
532 assigned-clocks =
542 assigned-clock-rates =
553 #clock-cells = <1>;
554 #reset-cells = <1>;
558 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
559 reg = <0x0 0xfd880000 0x0 0x1000>;
562 clock-names = "i2c", "pclk";
563 pinctrl-0 = <&i2c0m0_xfer>;
564 pinctrl-names = "default";
565 #address-cells = <1>;
566 #size-cells = <0>;
571 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
572 reg = <0x0 0xfd890000 0x0 0x100>;
575 clock-names = "baudclk", "apb_pclk";
577 dma-names = "tx", "rx";
578 pinctrl-0 = <&uart0m1_xfer>;
579 pinctrl-names = "default";
580 reg-shift = <2>;
581 reg-io-width = <4>;
586 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
587 reg = <0x0 0xfd8b0000 0x0 0x10>;
589 clock-names = "pwm", "pclk";
590 pinctrl-0 = <&pwm0m0_pins>;
591 pinctrl-names = "default";
592 #pwm-cells = <3>;
597 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
598 reg = <0x0 0xfd8b0010 0x0 0x10>;
600 clock-names = "pwm", "pclk";
601 pinctrl-0 = <&pwm1m0_pins>;
602 pinctrl-names = "default";
603 #pwm-cells = <3>;
608 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
609 reg = <0x0 0xfd8b0020 0x0 0x10>;
611 clock-names = "pwm", "pclk";
612 pinctrl-0 = <&pwm2m0_pins>;
613 pinctrl-names = "default";
614 #pwm-cells = <3>;
619 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
620 reg = <0x0 0xfd8b0030 0x0 0x10>;
622 clock-names = "pwm", "pclk";
623 pinctrl-0 = <&pwm3m0_pins>;
624 pinctrl-names = "default";
625 #pwm-cells = <3>;
629 pmu: power-management@fd8d8000 {
630 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
631 reg = <0x0 0xfd8d8000 0x0 0x400>;
633 power: power-controller {
634 compatible = "rockchip,rk3588-power-controller";
635 #address-cells = <1>;
636 #power-domain-cells = <1>;
637 #size-cells = <0>;
641 power-domain@RK3588_PD_NPU {
642 reg = <RK3588_PD_NPU>;
643 #power-domain-cells = <0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
647 power-domain@RK3588_PD_NPUTOP {
648 reg = <RK3588_PD_NPUTOP>;
656 #power-domain-cells = <0>;
657 #address-cells = <1>;
658 #size-cells = <0>;
660 power-domain@RK3588_PD_NPU1 {
661 reg = <RK3588_PD_NPU1>;
666 #power-domain-cells = <0>;
668 power-domain@RK3588_PD_NPU2 {
669 reg = <RK3588_PD_NPU2>;
674 #power-domain-cells = <0>;
679 power-domain@RK3588_PD_GPU {
680 reg = <RK3588_PD_GPU>;
688 #power-domain-cells = <0>;
691 power-domain@RK3588_PD_VCODEC {
692 reg = <RK3588_PD_VCODEC>;
693 #address-cells = <1>;
694 #size-cells = <0>;
695 #power-domain-cells = <0>;
697 power-domain@RK3588_PD_RKVDEC0 {
698 reg = <RK3588_PD_RKVDEC0>;
705 #power-domain-cells = <0>;
707 power-domain@RK3588_PD_RKVDEC1 {
708 reg = <RK3588_PD_RKVDEC1>;
714 #power-domain-cells = <0>;
716 power-domain@RK3588_PD_VENC0 {
717 reg = <RK3588_PD_VENC0>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 #power-domain-cells = <0>;
727 power-domain@RK3588_PD_VENC1 {
728 reg = <RK3588_PD_VENC1>;
736 #power-domain-cells = <0>;
741 power-domain@RK3588_PD_VDPU {
742 reg = <RK3588_PD_VDPU>;
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <0>;
774 power-domain@RK3588_PD_AV1 {
775 reg = <RK3588_PD_AV1>;
780 #power-domain-cells = <0>;
782 power-domain@RK3588_PD_RKVDEC0 {
783 reg = <RK3588_PD_RKVDEC0>;
789 #power-domain-cells = <0>;
791 power-domain@RK3588_PD_RKVDEC1 {
792 reg = <RK3588_PD_RKVDEC1>;
797 #power-domain-cells = <0>;
799 power-domain@RK3588_PD_RGA30 {
800 reg = <RK3588_PD_RGA30>;
804 #power-domain-cells = <0>;
807 power-domain@RK3588_PD_VOP {
808 reg = <RK3588_PD_VOP>;
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #power-domain-cells = <0>;
818 power-domain@RK3588_PD_VO0 {
819 reg = <RK3588_PD_VO0>;
828 #power-domain-cells = <0>;
831 power-domain@RK3588_PD_VO1 {
832 reg = <RK3588_PD_VO1>;
842 #power-domain-cells = <0>;
844 power-domain@RK3588_PD_VI {
845 reg = <RK3588_PD_VI>;
856 #address-cells = <1>;
857 #size-cells = <0>;
858 #power-domain-cells = <0>;
860 power-domain@RK3588_PD_ISP1 {
861 reg = <RK3588_PD_ISP1>;
868 #power-domain-cells = <0>;
870 power-domain@RK3588_PD_FEC {
871 reg = <RK3588_PD_FEC>;
879 #power-domain-cells = <0>;
882 power-domain@RK3588_PD_RGA31 {
883 reg = <RK3588_PD_RGA31>;
887 #power-domain-cells = <0>;
889 power-domain@RK3588_PD_USB {
890 reg = <RK3588_PD_USB>;
902 #power-domain-cells = <0>;
904 power-domain@RK3588_PD_GMAC {
905 reg = <RK3588_PD_GMAC>;
909 #power-domain-cells = <0>;
911 power-domain@RK3588_PD_PCIE {
912 reg = <RK3588_PD_PCIE>;
916 #power-domain-cells = <0>;
918 power-domain@RK3588_PD_SDIO {
919 reg = <RK3588_PD_SDIO>;
923 #power-domain-cells = <0>;
925 power-domain@RK3588_PD_AUDIO {
926 reg = <RK3588_PD_AUDIO>;
929 #power-domain-cells = <0>;
931 power-domain@RK3588_PD_SDMMC {
932 reg = <RK3588_PD_SDMMC>;
934 #power-domain-cells = <0>;
940 compatible = "rockchip,rk3588-i2s-tdm";
941 reg = <0x0 0xfddc0000 0x0 0x1000>;
944 clock-names = "mclk_tx", "mclk_rx", "hclk";
945 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
946 assigned-clock-parents = <&cru PLL_AUPLL>;
948 dma-names = "tx";
949 power-domains = <&power RK3588_PD_VO0>;
951 reset-names = "tx-m";
952 #sound-dai-cells = <0>;
957 compatible = "rockchip,rk3588-i2s-tdm";
958 reg = <0x0 0xfddf0000 0x0 0x1000>;
961 clock-names = "mclk_tx", "mclk_rx", "hclk";
962 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
963 assigned-clock-parents = <&cru PLL_AUPLL>;
965 dma-names = "tx";
966 power-domains = <&power RK3588_PD_VO1>;
968 reset-names = "tx-m";
969 #sound-dai-cells = <0>;
974 compatible = "rockchip,rk3588-i2s-tdm";
975 reg = <0x0 0xfddfc000 0x0 0x1000>;
978 clock-names = "mclk_tx", "mclk_rx", "hclk";
979 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
980 assigned-clock-parents = <&cru PLL_AUPLL>;
982 dma-names = "rx";
983 power-domains = <&power RK3588_PD_VO1>;
985 reset-names = "rx-m";
986 #sound-dai-cells = <0>;
991 compatible = "rockchip,rk3588-qos", "syscon";
992 reg = <0x0 0xfdf35000 0x0 0x20>;
996 compatible = "rockchip,rk3588-qos", "syscon";
997 reg = <0x0 0xfdf35200 0x0 0x20>;
1001 compatible = "rockchip,rk3588-qos", "syscon";
1002 reg = <0x0 0xfdf35400 0x0 0x20>;
1006 compatible = "rockchip,rk3588-qos", "syscon";
1007 reg = <0x0 0xfdf35600 0x0 0x20>;
1011 compatible = "rockchip,rk3588-qos", "syscon";
1012 reg = <0x0 0xfdf36000 0x0 0x20>;
1016 compatible = "rockchip,rk3588-qos", "syscon";
1017 reg = <0x0 0xfdf39000 0x0 0x20>;
1021 compatible = "rockchip,rk3588-qos", "syscon";
1022 reg = <0x0 0xfdf3d800 0x0 0x20>;
1026 compatible = "rockchip,rk3588-qos", "syscon";
1027 reg = <0x0 0xfdf3e000 0x0 0x20>;
1031 compatible = "rockchip,rk3588-qos", "syscon";
1032 reg = <0x0 0xfdf3e200 0x0 0x20>;
1036 compatible = "rockchip,rk3588-qos", "syscon";
1037 reg = <0x0 0xfdf3e400 0x0 0x20>;
1041 compatible = "rockchip,rk3588-qos", "syscon";
1042 reg = <0x0 0xfdf3e600 0x0 0x20>;
1046 compatible = "rockchip,rk3588-qos", "syscon";
1047 reg = <0x0 0xfdf40000 0x0 0x20>;
1051 compatible = "rockchip,rk3588-qos", "syscon";
1052 reg = <0x0 0xfdf40200 0x0 0x20>;
1056 compatible = "rockchip,rk3588-qos", "syscon";
1057 reg = <0x0 0xfdf40400 0x0 0x20>;
1061 compatible = "rockchip,rk3588-qos", "syscon";
1062 reg = <0x0 0xfdf40500 0x0 0x20>;
1066 compatible = "rockchip,rk3588-qos", "syscon";
1067 reg = <0x0 0xfdf40600 0x0 0x20>;
1071 compatible = "rockchip,rk3588-qos", "syscon";
1072 reg = <0x0 0xfdf40800 0x0 0x20>;
1076 compatible = "rockchip,rk3588-qos", "syscon";
1077 reg = <0x0 0xfdf41000 0x0 0x20>;
1081 compatible = "rockchip,rk3588-qos", "syscon";
1082 reg = <0x0 0xfdf41100 0x0 0x20>;
1086 compatible = "rockchip,rk3588-qos", "syscon";
1087 reg = <0x0 0xfdf60000 0x0 0x20>;
1091 compatible = "rockchip,rk3588-qos", "syscon";
1092 reg = <0x0 0xfdf60200 0x0 0x20>;
1096 compatible = "rockchip,rk3588-qos", "syscon";
1097 reg = <0x0 0xfdf60400 0x0 0x20>;
1101 compatible = "rockchip,rk3588-qos", "syscon";
1102 reg = <0x0 0xfdf61000 0x0 0x20>;
1106 compatible = "rockchip,rk3588-qos", "syscon";
1107 reg = <0x0 0xfdf61200 0x0 0x20>;
1111 compatible = "rockchip,rk3588-qos", "syscon";
1112 reg = <0x0 0xfdf61400 0x0 0x20>;
1116 compatible = "rockchip,rk3588-qos", "syscon";
1117 reg = <0x0 0xfdf62000 0x0 0x20>;
1121 compatible = "rockchip,rk3588-qos", "syscon";
1122 reg = <0x0 0xfdf63000 0x0 0x20>;
1126 compatible = "rockchip,rk3588-qos", "syscon";
1127 reg = <0x0 0xfdf64000 0x0 0x20>;
1131 compatible = "rockchip,rk3588-qos", "syscon";
1132 reg = <0x0 0xfdf66000 0x0 0x20>;
1136 compatible = "rockchip,rk3588-qos", "syscon";
1137 reg = <0x0 0xfdf66200 0x0 0x20>;
1141 compatible = "rockchip,rk3588-qos", "syscon";
1142 reg = <0x0 0xfdf66400 0x0 0x20>;
1146 compatible = "rockchip,rk3588-qos", "syscon";
1147 reg = <0x0 0xfdf66600 0x0 0x20>;
1151 compatible = "rockchip,rk3588-qos", "syscon";
1152 reg = <0x0 0xfdf66800 0x0 0x20>;
1156 compatible = "rockchip,rk3588-qos", "syscon";
1157 reg = <0x0 0xfdf66a00 0x0 0x20>;
1161 compatible = "rockchip,rk3588-qos", "syscon";
1162 reg = <0x0 0xfdf66c00 0x0 0x20>;
1166 compatible = "rockchip,rk3588-qos", "syscon";
1167 reg = <0x0 0xfdf66e00 0x0 0x20>;
1171 compatible = "rockchip,rk3588-qos", "syscon";
1172 reg = <0x0 0xfdf67000 0x0 0x20>;
1176 compatible = "rockchip,rk3588-qos", "syscon";
1177 reg = <0x0 0xfdf67200 0x0 0x20>;
1181 compatible = "rockchip,rk3588-qos", "syscon";
1182 reg = <0x0 0xfdf70000 0x0 0x20>;
1186 compatible = "rockchip,rk3588-qos", "syscon";
1187 reg = <0x0 0xfdf71000 0x0 0x20>;
1191 compatible = "rockchip,rk3588-qos", "syscon";
1192 reg = <0x0 0xfdf72000 0x0 0x20>;
1196 compatible = "rockchip,rk3588-qos", "syscon";
1197 reg = <0x0 0xfdf72200 0x0 0x20>;
1201 compatible = "rockchip,rk3588-qos", "syscon";
1202 reg = <0x0 0xfdf72400 0x0 0x20>;
1206 compatible = "rockchip,rk3588-qos", "syscon";
1207 reg = <0x0 0xfdf80000 0x0 0x20>;
1211 compatible = "rockchip,rk3588-qos", "syscon";
1212 reg = <0x0 0xfdf81000 0x0 0x20>;
1216 compatible = "rockchip,rk3588-qos", "syscon";
1217 reg = <0x0 0xfdf81200 0x0 0x20>;
1221 compatible = "rockchip,rk3588-qos", "syscon";
1222 reg = <0x0 0xfdf82000 0x0 0x20>;
1226 compatible = "rockchip,rk3588-qos", "syscon";
1227 reg = <0x0 0xfdf82200 0x0 0x20>;
1231 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1232 bus-range = <0x30 0x3f>;
1236 clock-names = "aclk_mst", "aclk_slv",
1245 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1246 #interrupt-cells = <1>;
1247 interrupt-map-mask = <0 0 0 7>;
1248 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1252 linux,pci-domain = <3>;
1253 max-link-speed = <2>;
1254 msi-map = <0x3000 &its0 0x3000 0x1000>;
1255 num-lanes = <1>;
1257 phy-names = "pcie-phy";
1258 power-domains = <&power RK3588_PD_PCIE>;
1262 reg = <0xa 0x40c00000 0x0 0x00400000>,
1265 reg-names = "dbi", "apb", "config";
1267 reset-names = "pwr", "pipe";
1268 #address-cells = <3>;
1269 #size-cells = <2>;
1272 pcie2x1l1_intc: legacy-interrupt-controller {
1273 interrupt-controller;
1274 #address-cells = <0>;
1275 #interrupt-cells = <1>;
1276 interrupt-parent = <&gic>;
1282 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1283 bus-range = <0x40 0x4f>;
1287 clock-names = "aclk_mst", "aclk_slv",
1296 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1297 #interrupt-cells = <1>;
1298 interrupt-map-mask = <0 0 0 7>;
1299 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1303 linux,pci-domain = <4>;
1304 max-link-speed = <2>;
1305 msi-map = <0x4000 &its0 0x4000 0x1000>;
1306 num-lanes = <1>;
1308 phy-names = "pcie-phy";
1309 power-domains = <&power RK3588_PD_PCIE>;
1313 reg = <0xa 0x41000000 0x0 0x00400000>,
1316 reg-names = "dbi", "apb", "config";
1318 reset-names = "pwr", "pipe";
1319 #address-cells = <3>;
1320 #size-cells = <2>;
1323 pcie2x1l2_intc: legacy-interrupt-controller {
1324 interrupt-controller;
1325 #address-cells = <0>;
1326 #interrupt-cells = <1>;
1327 interrupt-parent = <&gic>;
1333 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1334 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1337 interrupt-names = "macirq", "eth_wake_irq";
1341 clock-names = "stmmaceth", "clk_mac_ref",
1344 power-domains = <&power RK3588_PD_GMAC>;
1346 reset-names = "stmmaceth";
1348 rockchip,php-grf = <&php_grf>;
1349 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1350 snps,mixed-burst;
1351 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1352 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1357 compatible = "snps,dwmac-mdio";
1358 #address-cells = <0x1>;
1359 #size-cells = <0x0>;
1362 gmac1_stmmac_axi_setup: stmmac-axi-config {
1368 gmac1_mtl_rx_setup: rx-queues-config {
1369 snps,rx-queues-to-use = <2>;
1374 gmac1_mtl_tx_setup: tx-queues-config {
1375 snps,tx-queues-to-use = <2>;
1382 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1383 reg = <0 0xfe210000 0 0x1000>;
1388 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1389 ports-implemented = <0x1>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1394 sata-port@0 {
1395 reg = <0>;
1396 hba-port-cap = <HBA_PORT_FBSCP>;
1398 phy-names = "sata-phy";
1399 snps,rx-ts-max = <32>;
1400 snps,tx-ts-max = <32>;
1405 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1406 reg = <0 0xfe230000 0 0x1000>;
1411 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1412 ports-implemented = <0x1>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1417 sata-port@0 {
1418 reg = <0>;
1419 hba-port-cap = <HBA_PORT_FBSCP>;
1421 phy-names = "sata-phy";
1422 snps,rx-ts-max = <32>;
1423 snps,tx-ts-max = <32>;
1428 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1429 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1433 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1434 fifo-depth = <0x100>;
1435 max-frequency = <200000000>;
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1438 power-domains = <&power RK3588_PD_SDMMC>;
1443 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1444 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1448 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1449 fifo-depth = <0x100>;
1450 max-frequency = <200000000>;
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&sdiom1_pins>;
1453 power-domains = <&power RK3588_PD_SDIO>;
1458 compatible = "rockchip,rk3588-dwcmshc";
1459 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1461 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1462 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1466 clock-names = "core", "bus", "axi", "block", "timer";
1467 max-frequency = <200000000>;
1468 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1470 pinctrl-names = "default";
1474 reset-names = "core", "bus", "axi", "block", "timer";
1479 compatible = "rockchip,rk3588-i2s-tdm";
1480 reg = <0x0 0xfe470000 0x0 0x1000>;
1483 clock-names = "mclk_tx", "mclk_rx", "hclk";
1484 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1485 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&power RK3588_PD_AUDIO>;
1490 reset-names = "tx-m", "rx-m";
1491 rockchip,trcm-sync-tx-only;
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&i2s0_lrck
1503 #sound-dai-cells = <0>;
1508 compatible = "rockchip,rk3588-i2s-tdm";
1509 reg = <0x0 0xfe480000 0x0 0x1000>;
1512 clock-names = "mclk_tx", "mclk_rx", "hclk";
1514 dma-names = "tx", "rx";
1516 reset-names = "tx-m", "rx-m";
1517 rockchip,trcm-sync-tx-only;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&i2s1m0_lrck
1529 #sound-dai-cells = <0>;
1534 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1535 reg = <0x0 0xfe490000 0x0 0x1000>;
1538 clock-names = "i2s_clk", "i2s_hclk";
1539 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1540 assigned-clock-parents = <&cru PLL_AUPLL>;
1542 dma-names = "tx", "rx";
1543 power-domains = <&power RK3588_PD_AUDIO>;
1544 rockchip,trcm-sync-tx-only;
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&i2s2m1_lrck
1550 #sound-dai-cells = <0>;
1555 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1556 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1559 clock-names = "i2s_clk", "i2s_hclk";
1560 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1561 assigned-clock-parents = <&cru PLL_AUPLL>;
1563 dma-names = "tx", "rx";
1564 power-domains = <&power RK3588_PD_AUDIO>;
1565 rockchip,trcm-sync-tx-only;
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&i2s3_lrck
1571 #sound-dai-cells = <0>;
1575 gic: interrupt-controller@fe600000 {
1576 compatible = "arm,gic-v3";
1577 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1580 interrupt-controller;
1581 mbi-alias = <0x0 0xfe610000>;
1582 mbi-ranges = <424 56>;
1583 msi-controller;
1585 #address-cells = <2>;
1586 #interrupt-cells = <4>;
1587 #size-cells = <2>;
1589 its0: msi-controller@fe640000 {
1590 compatible = "arm,gic-v3-its";
1591 reg = <0x0 0xfe640000 0x0 0x20000>;
1592 msi-controller;
1593 #msi-cells = <1>;
1596 its1: msi-controller@fe660000 {
1597 compatible = "arm,gic-v3-its";
1598 reg = <0x0 0xfe660000 0x0 0x20000>;
1599 msi-controller;
1600 #msi-cells = <1>;
1603 ppi-partitions {
1604 ppi_partition0: interrupt-partition-0 {
1608 ppi_partition1: interrupt-partition-1 {
1614 dmac0: dma-controller@fea10000 {
1616 reg = <0x0 0xfea10000 0x0 0x4000>;
1619 arm,pl330-periph-burst;
1621 clock-names = "apb_pclk";
1622 #dma-cells = <1>;
1625 dmac1: dma-controller@fea30000 {
1627 reg = <0x0 0xfea30000 0x0 0x4000>;
1630 arm,pl330-periph-burst;
1632 clock-names = "apb_pclk";
1633 #dma-cells = <1>;
1637 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1638 reg = <0x0 0xfea90000 0x0 0x1000>;
1640 clock-names = "i2c", "pclk";
1642 pinctrl-0 = <&i2c1m0_xfer>;
1643 pinctrl-names = "default";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1650 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1651 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1653 clock-names = "i2c", "pclk";
1655 pinctrl-0 = <&i2c2m0_xfer>;
1656 pinctrl-names = "default";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1663 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1664 reg = <0x0 0xfeab0000 0x0 0x1000>;
1666 clock-names = "i2c", "pclk";
1668 pinctrl-0 = <&i2c3m0_xfer>;
1669 pinctrl-names = "default";
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1676 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1677 reg = <0x0 0xfeac0000 0x0 0x1000>;
1679 clock-names = "i2c", "pclk";
1681 pinctrl-0 = <&i2c4m0_xfer>;
1682 pinctrl-names = "default";
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1689 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1690 reg = <0x0 0xfead0000 0x0 0x1000>;
1692 clock-names = "i2c", "pclk";
1694 pinctrl-0 = <&i2c5m0_xfer>;
1695 pinctrl-names = "default";
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1702 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1703 reg = <0x0 0xfeae0000 0x0 0x20>;
1706 clock-names = "pclk", "timer";
1710 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1711 reg = <0x0 0xfeaf0000 0x0 0x100>;
1713 clock-names = "tclk", "pclk";
1718 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1719 reg = <0x0 0xfeb00000 0x0 0x1000>;
1722 clock-names = "spiclk", "apb_pclk";
1724 dma-names = "tx", "rx";
1725 num-cs = <2>;
1726 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1727 pinctrl-names = "default";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1734 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1735 reg = <0x0 0xfeb10000 0x0 0x1000>;
1738 clock-names = "spiclk", "apb_pclk";
1740 dma-names = "tx", "rx";
1741 num-cs = <2>;
1742 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1743 pinctrl-names = "default";
1744 #address-cells = <1>;
1745 #size-cells = <0>;
1750 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1751 reg = <0x0 0xfeb20000 0x0 0x1000>;
1754 clock-names = "spiclk", "apb_pclk";
1756 dma-names = "tx", "rx";
1757 num-cs = <2>;
1758 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1759 pinctrl-names = "default";
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1766 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1767 reg = <0x0 0xfeb30000 0x0 0x1000>;
1770 clock-names = "spiclk", "apb_pclk";
1772 dma-names = "tx", "rx";
1773 num-cs = <2>;
1774 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1775 pinctrl-names = "default";
1776 #address-cells = <1>;
1777 #size-cells = <0>;
1782 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1783 reg = <0x0 0xfeb40000 0x0 0x100>;
1786 clock-names = "baudclk", "apb_pclk";
1788 dma-names = "tx", "rx";
1789 pinctrl-0 = <&uart1m1_xfer>;
1790 pinctrl-names = "default";
1791 reg-io-width = <4>;
1792 reg-shift = <2>;
1797 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1798 reg = <0x0 0xfeb50000 0x0 0x100>;
1801 clock-names = "baudclk", "apb_pclk";
1803 dma-names = "tx", "rx";
1804 pinctrl-0 = <&uart2m1_xfer>;
1805 pinctrl-names = "default";
1806 reg-io-width = <4>;
1807 reg-shift = <2>;
1812 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1813 reg = <0x0 0xfeb60000 0x0 0x100>;
1816 clock-names = "baudclk", "apb_pclk";
1818 dma-names = "tx", "rx";
1819 pinctrl-0 = <&uart3m1_xfer>;
1820 pinctrl-names = "default";
1821 reg-io-width = <4>;
1822 reg-shift = <2>;
1827 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1828 reg = <0x0 0xfeb70000 0x0 0x100>;
1831 clock-names = "baudclk", "apb_pclk";
1833 dma-names = "tx", "rx";
1834 pinctrl-0 = <&uart4m1_xfer>;
1835 pinctrl-names = "default";
1836 reg-io-width = <4>;
1837 reg-shift = <2>;
1842 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1843 reg = <0x0 0xfeb80000 0x0 0x100>;
1846 clock-names = "baudclk", "apb_pclk";
1848 dma-names = "tx", "rx";
1849 pinctrl-0 = <&uart5m1_xfer>;
1850 pinctrl-names = "default";
1851 reg-io-width = <4>;
1852 reg-shift = <2>;
1857 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1858 reg = <0x0 0xfeb90000 0x0 0x100>;
1861 clock-names = "baudclk", "apb_pclk";
1863 dma-names = "tx", "rx";
1864 pinctrl-0 = <&uart6m1_xfer>;
1865 pinctrl-names = "default";
1866 reg-io-width = <4>;
1867 reg-shift = <2>;
1872 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1873 reg = <0x0 0xfeba0000 0x0 0x100>;
1876 clock-names = "baudclk", "apb_pclk";
1878 dma-names = "tx", "rx";
1879 pinctrl-0 = <&uart7m1_xfer>;
1880 pinctrl-names = "default";
1881 reg-io-width = <4>;
1882 reg-shift = <2>;
1887 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1888 reg = <0x0 0xfebb0000 0x0 0x100>;
1891 clock-names = "baudclk", "apb_pclk";
1893 dma-names = "tx", "rx";
1894 pinctrl-0 = <&uart8m1_xfer>;
1895 pinctrl-names = "default";
1896 reg-io-width = <4>;
1897 reg-shift = <2>;
1902 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1903 reg = <0x0 0xfebc0000 0x0 0x100>;
1906 clock-names = "baudclk", "apb_pclk";
1908 dma-names = "tx", "rx";
1909 pinctrl-0 = <&uart9m1_xfer>;
1910 pinctrl-names = "default";
1911 reg-io-width = <4>;
1912 reg-shift = <2>;
1917 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1918 reg = <0x0 0xfebd0000 0x0 0x10>;
1920 clock-names = "pwm", "pclk";
1921 pinctrl-0 = <&pwm4m0_pins>;
1922 pinctrl-names = "default";
1923 #pwm-cells = <3>;
1928 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1929 reg = <0x0 0xfebd0010 0x0 0x10>;
1931 clock-names = "pwm", "pclk";
1932 pinctrl-0 = <&pwm5m0_pins>;
1933 pinctrl-names = "default";
1934 #pwm-cells = <3>;
1939 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1940 reg = <0x0 0xfebd0020 0x0 0x10>;
1942 clock-names = "pwm", "pclk";
1943 pinctrl-0 = <&pwm6m0_pins>;
1944 pinctrl-names = "default";
1945 #pwm-cells = <3>;
1950 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1951 reg = <0x0 0xfebd0030 0x0 0x10>;
1953 clock-names = "pwm", "pclk";
1954 pinctrl-0 = <&pwm7m0_pins>;
1955 pinctrl-names = "default";
1956 #pwm-cells = <3>;
1961 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1962 reg = <0x0 0xfebe0000 0x0 0x10>;
1964 clock-names = "pwm", "pclk";
1965 pinctrl-0 = <&pwm8m0_pins>;
1966 pinctrl-names = "default";
1967 #pwm-cells = <3>;
1972 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1973 reg = <0x0 0xfebe0010 0x0 0x10>;
1975 clock-names = "pwm", "pclk";
1976 pinctrl-0 = <&pwm9m0_pins>;
1977 pinctrl-names = "default";
1978 #pwm-cells = <3>;
1983 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1984 reg = <0x0 0xfebe0020 0x0 0x10>;
1986 clock-names = "pwm", "pclk";
1987 pinctrl-0 = <&pwm10m0_pins>;
1988 pinctrl-names = "default";
1989 #pwm-cells = <3>;
1994 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1995 reg = <0x0 0xfebe0030 0x0 0x10>;
1997 clock-names = "pwm", "pclk";
1998 pinctrl-0 = <&pwm11m0_pins>;
1999 pinctrl-names = "default";
2000 #pwm-cells = <3>;
2005 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2006 reg = <0x0 0xfebf0000 0x0 0x10>;
2008 clock-names = "pwm", "pclk";
2009 pinctrl-0 = <&pwm12m0_pins>;
2010 pinctrl-names = "default";
2011 #pwm-cells = <3>;
2016 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2017 reg = <0x0 0xfebf0010 0x0 0x10>;
2019 clock-names = "pwm", "pclk";
2020 pinctrl-0 = <&pwm13m0_pins>;
2021 pinctrl-names = "default";
2022 #pwm-cells = <3>;
2027 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2028 reg = <0x0 0xfebf0020 0x0 0x10>;
2030 clock-names = "pwm", "pclk";
2031 pinctrl-0 = <&pwm14m0_pins>;
2032 pinctrl-names = "default";
2033 #pwm-cells = <3>;
2038 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2039 reg = <0x0 0xfebf0030 0x0 0x10>;
2041 clock-names = "pwm", "pclk";
2042 pinctrl-0 = <&pwm15m0_pins>;
2043 pinctrl-names = "default";
2044 #pwm-cells = <3>;
2049 compatible = "rockchip,rk3588-tsadc";
2050 reg = <0x0 0xfec00000 0x0 0x400>;
2053 clock-names = "tsadc", "apb_pclk";
2054 assigned-clocks = <&cru CLK_TSADC>;
2055 assigned-clock-rates = <2000000>;
2057 reset-names = "tsadc-apb", "tsadc";
2058 rockchip,hw-tshut-temp = <120000>;
2059 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2060 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2061 pinctrl-0 = <&tsadc_gpio_func>;
2062 pinctrl-1 = <&tsadc_shut>;
2063 pinctrl-names = "gpio", "otpout";
2064 #thermal-sensor-cells = <1>;
2069 compatible = "rockchip,rk3588-saradc";
2070 reg = <0x0 0xfec10000 0x0 0x10000>;
2072 #io-channel-cells = <1>;
2074 clock-names = "saradc", "apb_pclk";
2076 reset-names = "saradc-apb";
2081 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2082 reg = <0x0 0xfec80000 0x0 0x1000>;
2084 clock-names = "i2c", "pclk";
2086 pinctrl-0 = <&i2c6m0_xfer>;
2087 pinctrl-names = "default";
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2094 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2095 reg = <0x0 0xfec90000 0x0 0x1000>;
2097 clock-names = "i2c", "pclk";
2099 pinctrl-0 = <&i2c7m0_xfer>;
2100 pinctrl-names = "default";
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2107 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2108 reg = <0x0 0xfeca0000 0x0 0x1000>;
2110 clock-names = "i2c", "pclk";
2112 pinctrl-0 = <&i2c8m0_xfer>;
2113 pinctrl-names = "default";
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2120 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2121 reg = <0x0 0xfecb0000 0x0 0x1000>;
2124 clock-names = "spiclk", "apb_pclk";
2126 dma-names = "tx", "rx";
2127 num-cs = <2>;
2128 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2129 pinctrl-names = "default";
2130 #address-cells = <1>;
2131 #size-cells = <0>;
2136 compatible = "rockchip,rk3588-otp";
2137 reg = <0x0 0xfecc0000 0x0 0x400>;
2140 clock-names = "otp", "apb_pclk", "phy", "arb";
2143 reset-names = "otp", "apb", "arb";
2144 #address-cells = <1>;
2145 #size-cells = <1>;
2147 cpu_code: cpu-code@2 {
2148 reg = <0x02 0x2>;
2152 reg = <0x07 0x10>;
2155 cpub0_leakage: cpu-leakage@17 {
2156 reg = <0x17 0x1>;
2159 cpub1_leakage: cpu-leakage@18 {
2160 reg = <0x18 0x1>;
2163 cpul_leakage: cpu-leakage@19 {
2164 reg = <0x19 0x1>;
2167 log_leakage: log-leakage@1a {
2168 reg = <0x1a 0x1>;
2171 gpu_leakage: gpu-leakage@1b {
2172 reg = <0x1b 0x1>;
2175 otp_cpu_version: cpu-version@1c {
2176 reg = <0x1c 0x1>;
2180 npu_leakage: npu-leakage@28 {
2181 reg = <0x28 0x1>;
2184 codec_leakage: codec-leakage@29 {
2185 reg = <0x29 0x1>;
2189 dmac2: dma-controller@fed10000 {
2191 reg = <0x0 0xfed10000 0x0 0x4000>;
2194 arm,pl330-periph-burst;
2196 clock-names = "apb_pclk";
2197 #dma-cells = <1>;
2201 compatible = "rockchip,rk3588-naneng-combphy";
2202 reg = <0x0 0xfee00000 0x0 0x100>;
2205 clock-names = "ref", "apb", "pipe";
2206 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2207 assigned-clock-rates = <100000000>;
2208 #phy-cells = <1>;
2210 reset-names = "phy", "apb";
2211 rockchip,pipe-grf = <&php_grf>;
2212 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2217 compatible = "rockchip,rk3588-naneng-combphy";
2218 reg = <0x0 0xfee20000 0x0 0x100>;
2221 clock-names = "ref", "apb", "pipe";
2222 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2223 assigned-clock-rates = <100000000>;
2224 #phy-cells = <1>;
2226 reset-names = "phy", "apb";
2227 rockchip,pipe-grf = <&php_grf>;
2228 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2233 compatible = "mmio-sram";
2234 reg = <0x0 0xff001000 0x0 0xef000>;
2236 #address-cells = <1>;
2237 #size-cells = <1>;
2241 compatible = "rockchip,rk3588-pinctrl";
2244 #address-cells = <2>;
2245 #size-cells = <2>;
2248 compatible = "rockchip,gpio-bank";
2249 reg = <0x0 0xfd8a0000 0x0 0x100>;
2252 gpio-controller;
2253 gpio-ranges = <&pinctrl 0 0 32>;
2254 interrupt-controller;
2255 #gpio-cells = <2>;
2256 #interrupt-cells = <2>;
2260 compatible = "rockchip,gpio-bank";
2261 reg = <0x0 0xfec20000 0x0 0x100>;
2264 gpio-controller;
2265 gpio-ranges = <&pinctrl 0 32 32>;
2266 interrupt-controller;
2267 #gpio-cells = <2>;
2268 #interrupt-cells = <2>;
2272 compatible = "rockchip,gpio-bank";
2273 reg = <0x0 0xfec30000 0x0 0x100>;
2276 gpio-controller;
2277 gpio-ranges = <&pinctrl 0 64 32>;
2278 interrupt-controller;
2279 #gpio-cells = <2>;
2280 #interrupt-cells = <2>;
2284 compatible = "rockchip,gpio-bank";
2285 reg = <0x0 0xfec40000 0x0 0x100>;
2288 gpio-controller;
2289 gpio-ranges = <&pinctrl 0 96 32>;
2290 interrupt-controller;
2291 #gpio-cells = <2>;
2292 #interrupt-cells = <2>;
2296 compatible = "rockchip,gpio-bank";
2297 reg = <0x0 0xfec50000 0x0 0x100>;
2300 gpio-controller;
2301 gpio-ranges = <&pinctrl 0 128 32>;
2302 interrupt-controller;
2303 #gpio-cells = <2>;
2304 #interrupt-cells = <2>;
2309 #include "rk3588s-pinctrl.dtsi"