Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
49 #address-cells = <2>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a55";
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a55";
66 #cooling-cells = <2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
73 compatible = "arm,cortex-a55";
75 #cooling-cells = <2>;
76 enable-method = "psci";
77 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a55";
84 #cooling-cells = <2>;
85 enable-method = "psci";
86 operating-points-v2 = <&cpu0_opp_table>;
90 cpu0_opp_table: opp-table-0 {
91 compatible = "operating-points-v2";
92 opp-shared;
94 opp-408000000 {
95 opp-hz = /bits/ 64 <408000000>;
96 opp-microvolt = <900000 900000 1150000>;
97 clock-latency-ns = <40000>;
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <900000 900000 1150000>;
105 opp-816000000 {
106 opp-hz = /bits/ 64 <816000000>;
107 opp-microvolt = <900000 900000 1150000>;
108 opp-suspend;
111 opp-1104000000 {
112 opp-hz = /bits/ 64 <1104000000>;
113 opp-microvolt = <900000 900000 1150000>;
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <900000 900000 1150000>;
121 opp-1608000000 {
122 opp-hz = /bits/ 64 <1608000000>;
123 opp-microvolt = <975000 975000 1150000>;
126 opp-1800000000 {
127 opp-hz = /bits/ 64 <1800000000>;
128 opp-microvolt = <1050000 1050000 1150000>;
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
139 compatible = "arm,scmi-smc";
140 arm,smc-id = <0x82000010>;
142 #address-cells = <1>;
143 #size-cells = <0>;
147 #clock-cells = <1>;
152 gpu_opp_table: opp-table-1 {
153 compatible = "operating-points-v2";
155 opp-200000000 {
156 opp-hz = /bits/ 64 <200000000>;
157 opp-microvolt = <825000>;
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <825000>;
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <825000>;
170 opp-600000000 {
171 opp-hz = /bits/ 64 <600000000>;
172 opp-microvolt = <825000>;
175 opp-700000000 {
176 opp-hz = /bits/ 64 <700000000>;
177 opp-microvolt = <900000>;
180 opp-800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <1000000>;
186 hdmi_sound: hdmi-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "HDMI";
189 simple-audio-card,format = "i2s";
190 simple-audio-card,mclk-fs = <256>;
193 simple-audio-card,codec {
194 sound-dai = <&hdmi>;
197 simple-audio-card,cpu {
198 sound-dai = <&i2s0_8ch>;
203 compatible = "arm,cortex-a55-pmu";
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
212 compatible = "arm,psci-1.0";
217 compatible = "arm,armv8-timer";
222 arm,no-tick-in-suspend;
226 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
229 #clock-cells = <0>;
233 compatible = "fixed-clock";
234 clock-frequency = <32768>;
235 clock-output-names = "xin32k";
236 pinctrl-0 = <&clk32k_out0>;
237 pinctrl-names = "default";
238 #clock-cells = <0>;
242 compatible = "mmio-sram";
244 #address-cells = <1>;
245 #size-cells = <1>;
249 compatible = "arm,scmi-shmem";
255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
259 clock-names = "sata", "pmalive", "rxoob";
262 phy-names = "sata-phy";
263 ports-implemented = <0x1>;
264 power-domains = <&power RK3568_PD_PIPE>;
269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
273 clock-names = "sata", "pmalive", "rxoob";
276 phy-names = "sata-phy";
277 ports-implemented = <0x1>;
278 power-domains = <&power RK3568_PD_PIPE>;
283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
288 clock-names = "ref_clk", "suspend_clk",
292 power-domains = <&power RK3568_PD_PIPE>;
299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
304 clock-names = "ref_clk", "suspend_clk",
308 phy-names = "usb2-phy", "usb3-phy";
310 power-domains = <&power RK3568_PD_PIPE>;
316 gic: interrupt-controller@fd400000 {
317 compatible = "arm,gic-v3";
321 interrupt-controller;
322 #interrupt-cells = <3>;
323 mbi-alias = <0x0 0xfd410000>;
324 mbi-ranges = <296 24>;
325 msi-controller;
329 compatible = "generic-ehci";
335 phy-names = "usb";
340 compatible = "generic-ohci";
346 phy-names = "usb";
351 compatible = "generic-ehci";
357 phy-names = "usb";
362 compatible = "generic-ohci";
368 phy-names = "usb";
373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
376 pmu_io_domains: io-domains {
377 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
411 pmucru: clock-controller@fdd00000 {
412 compatible = "rockchip,rk3568-pmucru";
414 #clock-cells = <1>;
415 #reset-cells = <1>;
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
422 clock-names = "xin24m";
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426 assigned-clock-rates = <32768>, <1200000000>, <200000000>;
427 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
432 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
436 clock-names = "i2c", "pclk";
437 pinctrl-0 = <&i2c0_xfer>;
438 pinctrl-names = "default";
439 #address-cells = <1>;
440 #size-cells = <0>;
445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
449 clock-names = "baudclk", "apb_pclk";
451 pinctrl-0 = <&uart0_xfer>;
452 pinctrl-names = "default";
453 reg-io-width = <4>;
454 reg-shift = <2>;
458 pwm0: pwm@fdd70000 {
459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
462 clock-names = "pwm", "pclk";
463 pinctrl-0 = <&pwm0m0_pins>;
464 pinctrl-names = "default";
465 #pwm-cells = <3>;
469 pwm1: pwm@fdd70010 {
470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
473 clock-names = "pwm", "pclk";
474 pinctrl-0 = <&pwm1m0_pins>;
475 pinctrl-names = "default";
476 #pwm-cells = <3>;
480 pwm2: pwm@fdd70020 {
481 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
484 clock-names = "pwm", "pclk";
485 pinctrl-0 = <&pwm2m0_pins>;
486 pinctrl-names = "default";
487 #pwm-cells = <3>;
491 pwm3: pwm@fdd70030 {
492 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
495 clock-names = "pwm", "pclk";
496 pinctrl-0 = <&pwm3_pins>;
497 pinctrl-names = "default";
498 #pwm-cells = <3>;
502 pmu: power-management@fdd90000 {
503 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
506 power: power-controller {
507 compatible = "rockchip,rk3568-power-controller";
508 #power-domain-cells = <1>;
509 #address-cells = <1>;
510 #size-cells = <0>;
513 power-domain@RK3568_PD_GPU {
518 #power-domain-cells = <0>;
522 power-domain@RK3568_PD_VI {
529 #power-domain-cells = <0>;
532 power-domain@RK3568_PD_VO {
540 #power-domain-cells = <0>;
543 power-domain@RK3568_PD_RGA {
553 #power-domain-cells = <0>;
556 power-domain@RK3568_PD_VPU {
560 #power-domain-cells = <0>;
563 power-domain@RK3568_PD_RKVDEC {
567 #power-domain-cells = <0>;
570 power-domain@RK3568_PD_RKVENC {
576 #power-domain-cells = <0>;
582 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
587 interrupt-names = "job", "mmu", "gpu";
589 clock-names = "gpu", "bus";
590 #cooling-cells = <2>;
591 operating-points-v2 = <&gpu_opp_table>;
592 power-domains = <&power RK3568_PD_GPU>;
596 vpu: video-codec@fdea0400 {
597 compatible = "rockchip,rk3568-vpu";
601 clock-names = "aclk", "hclk";
603 power-domains = <&power RK3568_PD_VPU>;
607 compatible = "rockchip,rk3568-iommu";
610 clock-names = "aclk", "iface";
612 power-domains = <&power RK3568_PD_VPU>;
613 #iommu-cells = <0>;
617 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
621 clock-names = "aclk", "hclk", "sclk";
623 reset-names = "core", "axi", "ahb";
624 power-domains = <&power RK3568_PD_RGA>;
627 vepu: video-codec@fdee0000 {
628 compatible = "rockchip,rk3568-vepu";
632 clock-names = "aclk", "hclk";
634 power-domains = <&power RK3568_PD_RGA>;
638 compatible = "rockchip,rk3568-iommu";
642 clock-names = "aclk", "iface";
643 power-domains = <&power RK3568_PD_RGA>;
644 #iommu-cells = <0>;
648 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
653 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
654 fifo-depth = <0x100>;
655 max-frequency = <150000000>;
657 reset-names = "reset";
662 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
666 interrupt-names = "macirq", "eth_wake_irq";
671 clock-names = "stmmaceth", "mac_clk_rx",
676 reset-names = "stmmaceth";
678 snps,axi-config = <&gmac1_stmmac_axi_setup>;
679 snps,mixed-burst;
680 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
681 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
686 compatible = "snps,dwmac-mdio";
687 #address-cells = <0x1>;
688 #size-cells = <0x0>;
691 gmac1_stmmac_axi_setup: stmmac-axi-config {
697 gmac1_mtl_rx_setup: rx-queues-config {
698 snps,rx-queues-to-use = <1>;
702 gmac1_mtl_tx_setup: tx-queues-config {
703 snps,tx-queues-to-use = <1>;
710 reg-names = "vop", "gamma-lut";
714 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
716 power-domains = <&power RK3568_PD_VO>;
721 #address-cells = <1>;
722 #size-cells = <0>;
726 #address-cells = <1>;
727 #size-cells = <0>;
732 #address-cells = <1>;
733 #size-cells = <0>;
738 #address-cells = <1>;
739 #size-cells = <0>;
745 compatible = "rockchip,rk3568-iommu";
749 clock-names = "aclk", "iface";
750 #iommu-cells = <0>;
755 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
758 clock-names = "pclk";
760 phy-names = "dphy";
762 power-domains = <&power RK3568_PD_VO>;
763 reset-names = "apb";
769 #address-cells = <1>;
770 #size-cells = <0>;
783 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
786 clock-names = "pclk";
788 phy-names = "dphy";
790 power-domains = <&power RK3568_PD_VO>;
791 reset-names = "apb";
797 #address-cells = <1>;
798 #size-cells = <0>;
811 compatible = "rockchip,rk3568-dw-hdmi";
819 clock-names = "iahb", "isfr", "cec", "ref";
820 pinctrl-names = "default";
821 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
822 power-domains = <&power RK3568_PD_VO>;
823 reg-io-width = <4>;
825 #sound-dai-cells = <0>;
829 #address-cells = <1>;
830 #size-cells = <0>;
843 compatible = "rockchip,rk3568-qos", "syscon";
848 compatible = "rockchip,rk3568-qos", "syscon";
853 compatible = "rockchip,rk3568-qos", "syscon";
858 compatible = "rockchip,rk3568-qos", "syscon";
863 compatible = "rockchip,rk3568-qos", "syscon";
868 compatible = "rockchip,rk3568-qos", "syscon";
873 compatible = "rockchip,rk3568-qos", "syscon";
878 compatible = "rockchip,rk3568-qos", "syscon";
883 compatible = "rockchip,rk3568-qos", "syscon";
888 compatible = "rockchip,rk3568-qos", "syscon";
893 compatible = "rockchip,rk3568-qos", "syscon";
898 compatible = "rockchip,rk3568-qos", "syscon";
903 compatible = "rockchip,rk3568-qos", "syscon";
908 compatible = "rockchip,rk3568-qos", "syscon";
913 compatible = "rockchip,rk3568-qos", "syscon";
918 compatible = "rockchip,rk3568-qos", "syscon";
923 compatible = "rockchip,rk3568-qos", "syscon";
928 compatible = "rockchip,rk3568-qos", "syscon";
933 compatible = "rockchip,rk3568-qos", "syscon";
938 compatible = "rockchip,rk3568-qos", "syscon";
943 compatible = "rockchip,rk3568-qos", "syscon";
948 compatible = "rockchip,rk3568-qos", "syscon";
953 compatible = "rockchip,rk3568-qos", "syscon";
958 compatible = "rockchip,rk3568-qos", "syscon";
963 compatible = "rockchip,rk3568-pcie";
967 reg-names = "dbi", "apb", "config";
973 interrupt-names = "sys", "pmc", "msi", "legacy", "err";
974 bus-range = <0x0 0xf>;
978 clock-names = "aclk_mst", "aclk_slv",
981 #interrupt-cells = <1>;
982 interrupt-map-mask = <0 0 0 7>;
983 interrupt-map = <0 0 0 1 &pcie_intc 0>,
987 linux,pci-domain = <0>;
988 num-ib-windows = <6>;
989 num-ob-windows = <2>;
990 max-link-speed = <2>;
991 msi-map = <0x0 &gic 0x0 0x1000>;
992 num-lanes = <1>;
994 phy-names = "pcie-phy";
995 power-domains = <&power RK3568_PD_PIPE>;
1000 reset-names = "pipe";
1001 #address-cells = <3>;
1002 #size-cells = <2>;
1005 pcie_intc: legacy-interrupt-controller {
1006 #address-cells = <0>;
1007 #interrupt-cells = <1>;
1008 interrupt-controller;
1009 interrupt-parent = <&gic>;
1015 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1020 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1021 fifo-depth = <0x100>;
1022 max-frequency = <150000000>;
1024 reset-names = "reset";
1029 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1034 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1035 fifo-depth = <0x100>;
1036 max-frequency = <150000000>;
1038 reset-names = "reset";
1047 clock-names = "clk_sfc", "hclk_sfc";
1048 pinctrl-0 = <&fspi_pins>;
1049 pinctrl-names = "default";
1054 compatible = "rockchip,rk3568-dwcmshc";
1057 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1058 assigned-clock-rates = <200000000>, <24000000>;
1062 clock-names = "core", "bus", "axi", "block", "timer";
1067 compatible = "rockchip,rk3568-i2s-tdm";
1070 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1071 assigned-clock-rates = <1188000000>, <1188000000>;
1073 clock-names = "mclk_tx", "mclk_rx", "hclk";
1075 dma-names = "tx";
1077 reset-names = "tx-m", "rx-m";
1079 #sound-dai-cells = <0>;
1084 compatible = "rockchip,rk3568-i2s-tdm";
1087 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1088 assigned-clock-rates = <1188000000>, <1188000000>;
1091 clock-names = "mclk_tx", "mclk_rx", "hclk";
1093 dma-names = "rx", "tx";
1095 reset-names = "tx-m", "rx-m";
1097 pinctrl-names = "default";
1098 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1104 #sound-dai-cells = <0>;
1109 compatible = "rockchip,rk3568-i2s-tdm";
1112 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1113 assigned-clock-rates = <1188000000>;
1115 clock-names = "mclk_tx", "mclk_rx", "hclk";
1117 dma-names = "tx", "rx";
1119 reset-names = "m";
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&i2s2m0_sclktx
1126 #sound-dai-cells = <0>;
1131 compatible = "rockchip,rk3568-i2s-tdm";
1136 clock-names = "mclk_tx", "mclk_rx", "hclk";
1138 dma-names = "tx", "rx";
1140 reset-names = "tx-m", "rx-m";
1142 #sound-dai-cells = <0>;
1147 compatible = "rockchip,rk3568-pdm";
1151 clock-names = "pdm_clk", "pdm_hclk";
1153 dma-names = "rx";
1154 pinctrl-0 = <&pdmm0_clk
1160 pinctrl-names = "default";
1162 reset-names = "pdm-m";
1163 #sound-dai-cells = <0>;
1168 compatible = "rockchip,rk3568-spdif";
1171 clock-names = "mclk", "hclk";
1174 dma-names = "tx";
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&spdifm0_tx>;
1177 #sound-dai-cells = <0>;
1181 dmac0: dma-controller@fe530000 {
1186 arm,pl330-periph-burst;
1188 clock-names = "apb_pclk";
1189 #dma-cells = <1>;
1192 dmac1: dma-controller@fe550000 {
1197 arm,pl330-periph-burst;
1199 clock-names = "apb_pclk";
1200 #dma-cells = <1>;
1204 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1208 clock-names = "i2c", "pclk";
1209 pinctrl-0 = <&i2c1_xfer>;
1210 pinctrl-names = "default";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1217 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1221 clock-names = "i2c", "pclk";
1222 pinctrl-0 = <&i2c2m0_xfer>;
1223 pinctrl-names = "default";
1224 #address-cells = <1>;
1225 #size-cells = <0>;
1230 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1234 clock-names = "i2c", "pclk";
1235 pinctrl-0 = <&i2c3m0_xfer>;
1236 pinctrl-names = "default";
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1243 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1247 clock-names = "i2c", "pclk";
1248 pinctrl-0 = <&i2c4m0_xfer>;
1249 pinctrl-names = "default";
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1256 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1260 clock-names = "i2c", "pclk";
1261 pinctrl-0 = <&i2c5m0_xfer>;
1262 pinctrl-names = "default";
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1269 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1273 clock-names = "tclk", "pclk";
1277 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1281 clock-names = "spiclk", "apb_pclk";
1283 dma-names = "tx", "rx";
1284 pinctrl-names = "default";
1285 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1296 clock-names = "spiclk", "apb_pclk";
1298 dma-names = "tx", "rx";
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1301 #address-cells = <1>;
1302 #size-cells = <0>;
1307 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1311 clock-names = "spiclk", "apb_pclk";
1313 dma-names = "tx", "rx";
1314 pinctrl-names = "default";
1315 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1316 #address-cells = <1>;
1317 #size-cells = <0>;
1322 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1326 clock-names = "spiclk", "apb_pclk";
1328 dma-names = "tx", "rx";
1329 pinctrl-names = "default";
1330 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1331 #address-cells = <1>;
1332 #size-cells = <0>;
1337 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1341 clock-names = "baudclk", "apb_pclk";
1343 pinctrl-0 = <&uart1m0_xfer>;
1344 pinctrl-names = "default";
1345 reg-io-width = <4>;
1346 reg-shift = <2>;
1351 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1355 clock-names = "baudclk", "apb_pclk";
1357 pinctrl-0 = <&uart2m0_xfer>;
1358 pinctrl-names = "default";
1359 reg-io-width = <4>;
1360 reg-shift = <2>;
1365 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1369 clock-names = "baudclk", "apb_pclk";
1371 pinctrl-0 = <&uart3m0_xfer>;
1372 pinctrl-names = "default";
1373 reg-io-width = <4>;
1374 reg-shift = <2>;
1379 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1383 clock-names = "baudclk", "apb_pclk";
1385 pinctrl-0 = <&uart4m0_xfer>;
1386 pinctrl-names = "default";
1387 reg-io-width = <4>;
1388 reg-shift = <2>;
1393 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1397 clock-names = "baudclk", "apb_pclk";
1399 pinctrl-0 = <&uart5m0_xfer>;
1400 pinctrl-names = "default";
1401 reg-io-width = <4>;
1402 reg-shift = <2>;
1407 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1411 clock-names = "baudclk", "apb_pclk";
1413 pinctrl-0 = <&uart6m0_xfer>;
1414 pinctrl-names = "default";
1415 reg-io-width = <4>;
1416 reg-shift = <2>;
1421 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1425 clock-names = "baudclk", "apb_pclk";
1427 pinctrl-0 = <&uart7m0_xfer>;
1428 pinctrl-names = "default";
1429 reg-io-width = <4>;
1430 reg-shift = <2>;
1435 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1439 clock-names = "baudclk", "apb_pclk";
1441 pinctrl-0 = <&uart8m0_xfer>;
1442 pinctrl-names = "default";
1443 reg-io-width = <4>;
1444 reg-shift = <2>;
1449 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1453 clock-names = "baudclk", "apb_pclk";
1455 pinctrl-0 = <&uart9m0_xfer>;
1456 pinctrl-names = "default";
1457 reg-io-width = <4>;
1458 reg-shift = <2>;
1462 thermal_zones: thermal-zones {
1463 cpu_thermal: cpu-thermal {
1464 polling-delay-passive = <100>;
1465 polling-delay = <1000>;
1467 thermal-sensors = <&tsadc 0>;
1487 cooling-maps {
1490 cooling-device =
1499 gpu_thermal: gpu-thermal {
1500 polling-delay-passive = <20>; /* milliseconds */
1501 polling-delay = <1000>; /* milliseconds */
1503 thermal-sensors = <&tsadc 1>;
1506 gpu_threshold: gpu-threshold {
1511 gpu_target: gpu-target {
1516 gpu_crit: gpu-crit {
1523 cooling-maps {
1526 cooling-device =
1534 compatible = "rockchip,rk3568-tsadc";
1537 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1538 assigned-clock-rates = <17000000>, <700000>;
1540 clock-names = "tsadc", "apb_pclk";
1544 rockchip,hw-tshut-temp = <95000>;
1545 pinctrl-names = "init", "default", "sleep";
1546 pinctrl-0 = <&tsadc_pin>;
1547 pinctrl-1 = <&tsadc_shutorg>;
1548 pinctrl-2 = <&tsadc_pin>;
1549 #thermal-sensor-cells = <1>;
1554 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1558 clock-names = "saradc", "apb_pclk";
1560 reset-names = "saradc-apb";
1561 #io-channel-cells = <1>;
1565 pwm4: pwm@fe6e0000 {
1566 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1569 clock-names = "pwm", "pclk";
1570 pinctrl-0 = <&pwm4_pins>;
1571 pinctrl-names = "default";
1572 #pwm-cells = <3>;
1576 pwm5: pwm@fe6e0010 {
1577 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1580 clock-names = "pwm", "pclk";
1581 pinctrl-0 = <&pwm5_pins>;
1582 pinctrl-names = "default";
1583 #pwm-cells = <3>;
1587 pwm6: pwm@fe6e0020 {
1588 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1591 clock-names = "pwm", "pclk";
1592 pinctrl-0 = <&pwm6_pins>;
1593 pinctrl-names = "default";
1594 #pwm-cells = <3>;
1598 pwm7: pwm@fe6e0030 {
1599 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1602 clock-names = "pwm", "pclk";
1603 pinctrl-0 = <&pwm7_pins>;
1604 pinctrl-names = "default";
1605 #pwm-cells = <3>;
1609 pwm8: pwm@fe6f0000 {
1610 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1613 clock-names = "pwm", "pclk";
1614 pinctrl-0 = <&pwm8m0_pins>;
1615 pinctrl-names = "default";
1616 #pwm-cells = <3>;
1620 pwm9: pwm@fe6f0010 {
1621 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1624 clock-names = "pwm", "pclk";
1625 pinctrl-0 = <&pwm9m0_pins>;
1626 pinctrl-names = "default";
1627 #pwm-cells = <3>;
1631 pwm10: pwm@fe6f0020 {
1632 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1635 clock-names = "pwm", "pclk";
1636 pinctrl-0 = <&pwm10m0_pins>;
1637 pinctrl-names = "default";
1638 #pwm-cells = <3>;
1642 pwm11: pwm@fe6f0030 {
1643 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1646 clock-names = "pwm", "pclk";
1647 pinctrl-0 = <&pwm11m0_pins>;
1648 pinctrl-names = "default";
1649 #pwm-cells = <3>;
1653 pwm12: pwm@fe700000 {
1654 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1657 clock-names = "pwm", "pclk";
1658 pinctrl-0 = <&pwm12m0_pins>;
1659 pinctrl-names = "default";
1660 #pwm-cells = <3>;
1664 pwm13: pwm@fe700010 {
1665 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1668 clock-names = "pwm", "pclk";
1669 pinctrl-0 = <&pwm13m0_pins>;
1670 pinctrl-names = "default";
1671 #pwm-cells = <3>;
1675 pwm14: pwm@fe700020 {
1676 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1679 clock-names = "pwm", "pclk";
1680 pinctrl-0 = <&pwm14m0_pins>;
1681 pinctrl-names = "default";
1682 #pwm-cells = <3>;
1686 pwm15: pwm@fe700030 {
1687 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1690 clock-names = "pwm", "pclk";
1691 pinctrl-0 = <&pwm15m0_pins>;
1692 pinctrl-names = "default";
1693 #pwm-cells = <3>;
1698 compatible = "rockchip,rk3568-naneng-combphy";
1703 clock-names = "ref", "apb", "pipe";
1704 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1705 assigned-clock-rates = <100000000>;
1707 rockchip,pipe-grf = <&pipegrf>;
1708 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1709 #phy-cells = <1>;
1714 compatible = "rockchip,rk3568-naneng-combphy";
1719 clock-names = "ref", "apb", "pipe";
1720 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1721 assigned-clock-rates = <100000000>;
1723 rockchip,pipe-grf = <&pipegrf>;
1724 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1725 #phy-cells = <1>;
1730 compatible = "rockchip,rk3568-csi-dphy";
1733 clock-names = "pclk";
1734 #phy-cells = <0>;
1736 reset-names = "apb";
1741 dsi_dphy0: mipi-dphy@fe850000 {
1742 compatible = "rockchip,rk3568-dsi-dphy";
1744 clock-names = "ref", "pclk";
1746 #phy-cells = <0>;
1747 power-domains = <&power RK3568_PD_VO>;
1748 reset-names = "apb";
1753 dsi_dphy1: mipi-dphy@fe860000 {
1754 compatible = "rockchip,rk3568-dsi-dphy";
1756 clock-names = "ref", "pclk";
1758 #phy-cells = <0>;
1759 power-domains = <&power RK3568_PD_VO>;
1760 reset-names = "apb";
1766 compatible = "rockchip,rk3568-usb2phy";
1769 clock-names = "phyclk";
1770 clock-output-names = "clk_usbphy0_480m";
1773 #clock-cells = <0>;
1776 usb2phy0_host: host-port {
1777 #phy-cells = <0>;
1781 usb2phy0_otg: otg-port {
1782 #phy-cells = <0>;
1788 compatible = "rockchip,rk3568-usb2phy";
1791 clock-names = "phyclk";
1792 clock-output-names = "clk_usbphy1_480m";
1795 #clock-cells = <0>;
1798 usb2phy1_host: host-port {
1799 #phy-cells = <0>;
1803 usb2phy1_otg: otg-port {
1804 #phy-cells = <0>;
1810 compatible = "rockchip,rk3568-pinctrl";
1813 #address-cells = <2>;
1814 #size-cells = <2>;
1818 compatible = "rockchip,gpio-bank";
1822 gpio-controller;
1823 gpio-ranges = <&pinctrl 0 0 32>;
1824 #gpio-cells = <2>;
1825 interrupt-controller;
1826 #interrupt-cells = <2>;
1830 compatible = "rockchip,gpio-bank";
1834 gpio-controller;
1835 gpio-ranges = <&pinctrl 0 32 32>;
1836 #gpio-cells = <2>;
1837 interrupt-controller;
1838 #interrupt-cells = <2>;
1842 compatible = "rockchip,gpio-bank";
1846 gpio-controller;
1847 gpio-ranges = <&pinctrl 0 64 32>;
1848 #gpio-cells = <2>;
1849 interrupt-controller;
1850 #interrupt-cells = <2>;
1854 compatible = "rockchip,gpio-bank";
1858 gpio-controller;
1859 gpio-ranges = <&pinctrl 0 96 32>;
1860 #gpio-cells = <2>;
1861 interrupt-controller;
1862 #interrupt-cells = <2>;
1866 compatible = "rockchip,gpio-bank";
1870 gpio-controller;
1871 gpio-ranges = <&pinctrl 0 128 32>;
1872 #gpio-cells = <2>;
1873 interrupt-controller;
1874 #interrupt-cells = <2>;
1879 #include "rk3568-pinctrl.dtsi"