Lines Matching +full:io +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
32 assigned-clock-rates = <0>, <125000000>;
34 phy-handle = <&rgmii_phy0>;
35 phy-mode = "rgmii-id";
36 pinctrl-names = "default";
37 pinctrl-0 = <&gmac0_miim
42 snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
43 snps,reset-active-low;
44 /* Reset time is 15ms, 50ms for rtl8211f */
45 snps,reset-delays-us = <0 15000 50000>;
52 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
53 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
54 assigned-clock-rates = <0>, <125000000>;
56 phy-handle = <&rgmii_phy1>;
57 phy-mode = "rgmii-id";
58 pinctrl-names = "default";
59 pinctrl-0 = <&gmac1m1_miim
64 snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
65 snps,reset-active-low;
66 /* Reset time is 15ms, 50ms for rtl8211f */
67 snps,reset-delays-us = <0 15000 50000>;
74 rgmii_phy0: ethernet-phy@0 {
75 compatible = "ethernet-phy-ieee802.3-c22";
77 pinctrl-0 = <ð_phy0_reset_pin>;
78 pinctrl-names = "default";
83 rgmii_phy1: ethernet-phy@0 {
84 compatible = "ethernet-phy-ieee802.3-c22";
86 pinctrl-0 = <ð_phy1_reset_pin>;
87 pinctrl-names = "default";
93 eth_phy0_reset_pin: eth-phy0-reset-pin {
99 eth_phy1_reset_pin: eth-phy1-reset-pin {
106 bus-width = <8>;
107 max-frequency = <200000000>;
108 non-removable;
109 pinctrl-names = "default";
110 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;