Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
40 #address-cells = <2>;
41 #size-cells = <0>;
43 cpu-map {
71 compatible = "arm,cortex-a53";
73 enable-method = "psci";
74 capacity-dmips-mhz = <485>;
76 #cooling-cells = <2>; /* min followed by max */
77 dynamic-power-coefficient = <100>;
78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <485>;
88 #cooling-cells = <2>; /* min followed by max */
89 dynamic-power-coefficient = <100>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
95 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 capacity-dmips-mhz = <485>;
100 #cooling-cells = <2>; /* min followed by max */
101 dynamic-power-coefficient = <100>;
102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <485>;
112 #cooling-cells = <2>; /* min followed by max */
113 dynamic-power-coefficient = <100>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
119 compatible = "arm,cortex-a72";
121 enable-method = "psci";
122 capacity-dmips-mhz = <1024>;
124 #cooling-cells = <2>; /* min followed by max */
125 dynamic-power-coefficient = <436>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 thermal-idle {
129 #cooling-cells = <2>;
130 duration-us = <10000>;
131 exit-latency-us = <500>;
137 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
142 #cooling-cells = <2>; /* min followed by max */
143 dynamic-power-coefficient = <436>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
146 thermal-idle {
147 #cooling-cells = <2>;
148 duration-us = <10000>;
149 exit-latency-us = <500>;
153 idle-states {
154 entry-method = "psci";
156 CPU_SLEEP: cpu-sleep {
157 compatible = "arm,idle-state";
158 local-timer-stop;
159 arm,psci-suspend-param = <0x0010000>;
160 entry-latency-us = <120>;
161 exit-latency-us = <250>;
162 min-residency-us = <900>;
165 CLUSTER_SLEEP: cluster-sleep {
166 compatible = "arm,idle-state";
167 local-timer-stop;
168 arm,psci-suspend-param = <0x1010000>;
169 entry-latency-us = <400>;
170 exit-latency-us = <500>;
171 min-residency-us = <2000>;
176 display-subsystem {
177 compatible = "rockchip,display-subsystem";
181 dmc: memory-controller {
182 compatible = "rockchip,rk3399-dmc";
184 devfreq-events = <&dfi>;
186 clock-names = "dmc_clk";
191 compatible = "arm,cortex-a53-pmu";
196 compatible = "arm,cortex-a72-pmu";
201 compatible = "arm,psci-1.0";
206 compatible = "arm,armv8-timer";
211 arm,no-tick-in-suspend;
215 compatible = "fixed-clock";
216 clock-frequency = <24000000>;
217 clock-output-names = "xin24m";
218 #clock-cells = <0>;
222 compatible = "rockchip,rk3399-pcie";
225 reg-names = "axi-base", "apb-base";
227 #address-cells = <3>;
228 #size-cells = <2>;
229 #interrupt-cells = <1>;
230 aspm-no-l0s;
231 bus-range = <0x0 0x1f>;
234 clock-names = "aclk", "aclk-perf",
239 interrupt-names = "sys", "legacy", "client";
240 interrupt-map-mask = <0 0 0 7>;
241 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
245 max-link-speed = <1>;
246 msi-map = <0x0 &its 0x0 0x1000>;
249 phy-names = "pcie-phy-0", "pcie-phy-1",
250 "pcie-phy-2", "pcie-phy-3";
257 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
261 pcie0_intc: interrupt-controller {
262 interrupt-controller;
263 #address-cells = <0>;
264 #interrupt-cells = <1>;
268 pcie0_ep: pcie-ep@f8000000 {
269 compatible = "rockchip,rk3399-pcie-ep";
272 reg-names = "apb-base", "mem-base";
275 clock-names = "aclk", "aclk-perf",
277 max-functions = /bits/ 8 <8>;
278 num-lanes = <4>;
283 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
287 phy-names = "pcie-phy-0", "pcie-phy-1",
288 "pcie-phy-2", "pcie-phy-3";
289 rockchip,max-outbound-regions = <32>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pcie_clkreqnb_cpm>;
296 compatible = "rockchip,rk3399-gmac";
299 interrupt-names = "macirq";
304 clock-names = "stmmaceth", "mac_clk_rx",
308 power-domains = <&power RK3399_PD_GMAC>;
310 reset-names = "stmmaceth";
317 compatible = "rockchip,rk3399-dw-mshc",
318 "rockchip,rk3288-dw-mshc";
321 max-frequency = <150000000>;
324 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
325 fifo-depth = <0x100>;
326 power-domains = <&power RK3399_PD_SDIOAUDIO>;
328 reset-names = "reset";
333 compatible = "rockchip,rk3399-dw-mshc",
334 "rockchip,rk3288-dw-mshc";
337 max-frequency = <150000000>;
338 assigned-clocks = <&cru HCLK_SD>;
339 assigned-clock-rates = <200000000>;
342 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
343 fifo-depth = <0x100>;
344 power-domains = <&power RK3399_PD_SD>;
346 reset-names = "reset";
351 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
354 arasan,soc-ctl-syscon = <&grf>;
355 assigned-clocks = <&cru SCLK_EMMC>;
356 assigned-clock-rates = <200000000>;
358 clock-names = "clk_xin", "clk_ahb";
359 clock-output-names = "emmc_cardclock";
360 #clock-cells = <0>;
362 phy-names = "phy_arasan";
363 power-domains = <&power RK3399_PD_EMMC>;
364 disable-cqe-dcmd;
369 compatible = "generic-ehci";
375 phy-names = "usb";
380 compatible = "generic-ohci";
386 phy-names = "usb";
391 compatible = "generic-ehci";
397 phy-names = "usb";
402 compatible = "generic-ohci";
408 phy-names = "usb";
413 compatible = "arm,coresight-cpu-debug", "arm,primecell";
416 clock-names = "apb_pclk";
421 compatible = "arm,coresight-cpu-debug", "arm,primecell";
424 clock-names = "apb_pclk";
429 compatible = "arm,coresight-cpu-debug", "arm,primecell";
432 clock-names = "apb_pclk";
437 compatible = "arm,coresight-cpu-debug", "arm,primecell";
440 clock-names = "apb_pclk";
445 compatible = "arm,coresight-cpu-debug", "arm,primecell";
448 clock-names = "apb_pclk";
453 compatible = "arm,coresight-cpu-debug", "arm,primecell";
456 clock-names = "apb_pclk";
461 compatible = "rockchip,rk3399-dwc3";
462 #address-cells = <2>;
463 #size-cells = <2>;
468 clock-names = "ref_clk", "suspend_clk",
472 reset-names = "usb3-otg";
481 clock-names = "ref", "bus_early", "suspend";
484 phy-names = "usb2-phy", "usb3-phy";
487 snps,dis-u2-freeclk-exists-quirk;
489 snps,dis-del-phy-power-chg-quirk;
490 snps,dis-tx-ipgap-linecheck-quirk;
491 power-domains = <&power RK3399_PD_USB3>;
497 compatible = "rockchip,rk3399-dwc3";
498 #address-cells = <2>;
499 #size-cells = <2>;
504 clock-names = "ref_clk", "suspend_clk",
508 reset-names = "usb3-otg";
517 clock-names = "ref", "bus_early", "suspend";
520 phy-names = "usb2-phy", "usb3-phy";
523 snps,dis-u2-freeclk-exists-quirk;
525 snps,dis-del-phy-power-chg-quirk;
526 snps,dis-tx-ipgap-linecheck-quirk;
527 power-domains = <&power RK3399_PD_USB3>;
533 compatible = "rockchip,rk3399-cdn-dp";
536 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
537 assigned-clock-rates = <100000000>, <200000000>;
540 clock-names = "core-clk", "pclk", "spdif", "grf";
542 power-domains = <&power RK3399_PD_HDCP>;
545 reset-names = "spdif", "dptx", "apb", "core";
547 #sound-dai-cells = <1>;
552 #address-cells = <1>;
553 #size-cells = <0>;
557 remote-endpoint = <&vopb_out_dp>;
562 remote-endpoint = <&vopl_out_dp>;
568 gic: interrupt-controller@fee00000 {
569 compatible = "arm,gic-v3";
570 #interrupt-cells = <4>;
571 #address-cells = <2>;
572 #size-cells = <2>;
574 interrupt-controller;
582 its: msi-controller@fee20000 {
583 compatible = "arm,gic-v3-its";
584 msi-controller;
585 #msi-cells = <1>;
589 ppi-partitions {
590 ppi_cluster0: interrupt-partition-0 {
594 ppi_cluster1: interrupt-partition-1 {
601 compatible = "rockchip,rk3399-saradc";
604 #io-channel-cells = <1>;
606 clock-names = "saradc", "apb_pclk";
608 reset-names = "saradc-apb";
613 compatible = "rockchip,rk3399-crypto";
617 clock-names = "hclk_master", "hclk_slave", "sclk";
619 reset-names = "master", "slave", "crypto-rst";
623 compatible = "rockchip,rk3399-crypto";
627 clock-names = "hclk_master", "hclk_slave", "sclk";
629 reset-names = "master", "slave", "crypto-rst";
633 compatible = "rockchip,rk3399-i2c";
635 assigned-clocks = <&cru SCLK_I2C1>;
636 assigned-clock-rates = <200000000>;
638 clock-names = "i2c", "pclk";
640 pinctrl-names = "default";
641 pinctrl-0 = <&i2c1_xfer>;
642 #address-cells = <1>;
643 #size-cells = <0>;
648 compatible = "rockchip,rk3399-i2c";
650 assigned-clocks = <&cru SCLK_I2C2>;
651 assigned-clock-rates = <200000000>;
653 clock-names = "i2c", "pclk";
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2c2_xfer>;
657 #address-cells = <1>;
658 #size-cells = <0>;
663 compatible = "rockchip,rk3399-i2c";
665 assigned-clocks = <&cru SCLK_I2C3>;
666 assigned-clock-rates = <200000000>;
668 clock-names = "i2c", "pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c3_xfer>;
672 #address-cells = <1>;
673 #size-cells = <0>;
678 compatible = "rockchip,rk3399-i2c";
680 assigned-clocks = <&cru SCLK_I2C5>;
681 assigned-clock-rates = <200000000>;
683 clock-names = "i2c", "pclk";
685 pinctrl-names = "default";
686 pinctrl-0 = <&i2c5_xfer>;
687 #address-cells = <1>;
688 #size-cells = <0>;
693 compatible = "rockchip,rk3399-i2c";
695 assigned-clocks = <&cru SCLK_I2C6>;
696 assigned-clock-rates = <200000000>;
698 clock-names = "i2c", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&i2c6_xfer>;
702 #address-cells = <1>;
703 #size-cells = <0>;
708 compatible = "rockchip,rk3399-i2c";
710 assigned-clocks = <&cru SCLK_I2C7>;
711 assigned-clock-rates = <200000000>;
713 clock-names = "i2c", "pclk";
715 pinctrl-names = "default";
716 pinctrl-0 = <&i2c7_xfer>;
717 #address-cells = <1>;
718 #size-cells = <0>;
723 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
726 clock-names = "baudclk", "apb_pclk";
728 reg-shift = <2>;
729 reg-io-width = <4>;
730 pinctrl-names = "default";
731 pinctrl-0 = <&uart0_xfer>;
736 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
739 clock-names = "baudclk", "apb_pclk";
741 reg-shift = <2>;
742 reg-io-width = <4>;
743 pinctrl-names = "default";
744 pinctrl-0 = <&uart1_xfer>;
749 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
752 clock-names = "baudclk", "apb_pclk";
754 reg-shift = <2>;
755 reg-io-width = <4>;
756 pinctrl-names = "default";
757 pinctrl-0 = <&uart2c_xfer>;
762 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
765 clock-names = "baudclk", "apb_pclk";
767 reg-shift = <2>;
768 reg-io-width = <4>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&uart3_xfer>;
775 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
778 clock-names = "spiclk", "apb_pclk";
781 dma-names = "tx", "rx";
782 pinctrl-names = "default";
783 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
784 #address-cells = <1>;
785 #size-cells = <0>;
790 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
793 clock-names = "spiclk", "apb_pclk";
796 dma-names = "tx", "rx";
797 pinctrl-names = "default";
798 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
799 #address-cells = <1>;
800 #size-cells = <0>;
805 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
808 clock-names = "spiclk", "apb_pclk";
811 dma-names = "tx", "rx";
812 pinctrl-names = "default";
813 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
814 #address-cells = <1>;
815 #size-cells = <0>;
820 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
823 clock-names = "spiclk", "apb_pclk";
826 dma-names = "tx", "rx";
827 pinctrl-names = "default";
828 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
829 #address-cells = <1>;
830 #size-cells = <0>;
835 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
838 clock-names = "spiclk", "apb_pclk";
841 dma-names = "tx", "rx";
842 pinctrl-names = "default";
843 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
844 power-domains = <&power RK3399_PD_SDIOAUDIO>;
845 #address-cells = <1>;
846 #size-cells = <0>;
850 thermal_zones: thermal-zones {
851 cpu_thermal: cpu-thermal {
852 polling-delay-passive = <100>;
853 polling-delay = <1000>;
855 thermal-sensors = <&tsadc 0>;
875 cooling-maps {
878 cooling-device =
884 cooling-device =
895 gpu_thermal: gpu-thermal {
896 polling-delay-passive = <100>;
897 polling-delay = <1000>;
899 thermal-sensors = <&tsadc 1>;
914 cooling-maps {
917 cooling-device =
925 compatible = "rockchip,rk3399-tsadc";
928 assigned-clocks = <&cru SCLK_TSADC>;
929 assigned-clock-rates = <750000>;
931 clock-names = "tsadc", "apb_pclk";
933 reset-names = "tsadc-apb";
935 rockchip,hw-tshut-temp = <95000>;
936 pinctrl-names = "init", "default", "sleep";
937 pinctrl-0 = <&otp_pin>;
938 pinctrl-1 = <&otp_out>;
939 pinctrl-2 = <&otp_pin>;
940 #thermal-sensor-cells = <1>;
945 compatible = "rockchip,rk3399-qos", "syscon";
950 compatible = "rockchip,rk3399-qos", "syscon";
955 compatible = "rockchip,rk3399-qos", "syscon";
960 compatible = "rockchip,rk3399-qos", "syscon";
965 compatible = "rockchip,rk3399-qos", "syscon";
970 compatible = "rockchip,rk3399-qos", "syscon";
975 compatible = "rockchip,rk3399-qos", "syscon";
980 compatible = "rockchip,rk3399-qos", "syscon";
985 compatible = "rockchip,rk3399-qos", "syscon";
990 compatible = "rockchip,rk3399-qos", "syscon";
995 compatible = "rockchip,rk3399-qos", "syscon";
1000 compatible = "rockchip,rk3399-qos", "syscon";
1005 compatible = "rockchip,rk3399-qos", "syscon";
1010 compatible = "rockchip,rk3399-qos", "syscon";
1015 compatible = "rockchip,rk3399-qos", "syscon";
1020 compatible = "rockchip,rk3399-qos", "syscon";
1025 compatible = "rockchip,rk3399-qos", "syscon";
1030 compatible = "rockchip,rk3399-qos", "syscon";
1035 compatible = "rockchip,rk3399-qos", "syscon";
1040 compatible = "rockchip,rk3399-qos", "syscon";
1045 compatible = "rockchip,rk3399-qos", "syscon";
1050 compatible = "rockchip,rk3399-qos", "syscon";
1055 compatible = "rockchip,rk3399-qos", "syscon";
1060 compatible = "rockchip,rk3399-qos", "syscon";
1065 compatible = "rockchip,rk3399-qos", "syscon";
1069 pmu: power-management@ff310000 {
1070 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
1080 power: power-controller {
1081 compatible = "rockchip,rk3399-power-controller";
1082 #power-domain-cells = <1>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1087 power-domain@RK3399_PD_IEP {
1092 #power-domain-cells = <0>;
1094 power-domain@RK3399_PD_RGA {
1100 #power-domain-cells = <0>;
1102 power-domain@RK3399_PD_VCODEC {
1107 #power-domain-cells = <0>;
1109 power-domain@RK3399_PD_VDU {
1115 #power-domain-cells = <0>;
1119 power-domain@RK3399_PD_GPU {
1123 #power-domain-cells = <0>;
1127 power-domain@RK3399_PD_EDP {
1130 #power-domain-cells = <0>;
1132 power-domain@RK3399_PD_EMMC {
1136 #power-domain-cells = <0>;
1138 power-domain@RK3399_PD_GMAC {
1143 #power-domain-cells = <0>;
1145 power-domain@RK3399_PD_SD {
1150 #power-domain-cells = <0>;
1152 power-domain@RK3399_PD_SDIOAUDIO {
1156 #power-domain-cells = <0>;
1158 power-domain@RK3399_PD_TCPD0 {
1162 #power-domain-cells = <0>;
1164 power-domain@RK3399_PD_TCPD1 {
1168 #power-domain-cells = <0>;
1170 power-domain@RK3399_PD_USB3 {
1175 #power-domain-cells = <0>;
1177 power-domain@RK3399_PD_VIO {
1179 #power-domain-cells = <1>;
1180 #address-cells = <1>;
1181 #size-cells = <0>;
1183 power-domain@RK3399_PD_HDCP {
1189 #power-domain-cells = <0>;
1191 power-domain@RK3399_PD_ISP0 {
1197 #power-domain-cells = <0>;
1199 power-domain@RK3399_PD_ISP1 {
1205 #power-domain-cells = <0>;
1207 power-domain@RK3399_PD_VO {
1209 #power-domain-cells = <1>;
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1213 power-domain@RK3399_PD_VOPB {
1219 #power-domain-cells = <0>;
1221 power-domain@RK3399_PD_VOPL {
1226 #power-domain-cells = <0>;
1234 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1237 pmu_io_domains: io-domains {
1238 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1244 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1247 clock-names = "spiclk", "apb_pclk";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1257 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1260 clock-names = "baudclk", "apb_pclk";
1262 reg-shift = <2>;
1263 reg-io-width = <4>;
1264 pinctrl-names = "default";
1265 pinctrl-0 = <&uart4_xfer>;
1270 compatible = "rockchip,rk3399-i2c";
1272 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1273 assigned-clock-rates = <200000000>;
1275 clock-names = "i2c", "pclk";
1277 pinctrl-names = "default";
1278 pinctrl-0 = <&i2c0_xfer>;
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1285 compatible = "rockchip,rk3399-i2c";
1287 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1288 assigned-clock-rates = <200000000>;
1290 clock-names = "i2c", "pclk";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&i2c4_xfer>;
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1300 compatible = "rockchip,rk3399-i2c";
1302 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1303 assigned-clock-rates = <200000000>;
1305 clock-names = "i2c", "pclk";
1307 pinctrl-names = "default";
1308 pinctrl-0 = <&i2c8_xfer>;
1309 #address-cells = <1>;
1310 #size-cells = <0>;
1315 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1317 #pwm-cells = <3>;
1318 pinctrl-names = "default";
1319 pinctrl-0 = <&pwm0_pin>;
1325 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1327 #pwm-cells = <3>;
1328 pinctrl-names = "default";
1329 pinctrl-0 = <&pwm1_pin>;
1335 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1337 #pwm-cells = <3>;
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&pwm2_pin>;
1345 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1347 #pwm-cells = <3>;
1348 pinctrl-names = "default";
1349 pinctrl-0 = <&pwm3a_pin>;
1356 compatible = "rockchip,rk3399-dfi";
1360 clock-names = "pclk_ddr_mon";
1364 vpu: video-codec@ff650000 {
1365 compatible = "rockchip,rk3399-vpu";
1369 interrupt-names = "vepu", "vdpu";
1371 clock-names = "aclk", "hclk";
1373 power-domains = <&power RK3399_PD_VCODEC>;
1381 clock-names = "aclk", "iface";
1382 #iommu-cells = <0>;
1383 power-domains = <&power RK3399_PD_VCODEC>;
1386 vdec: video-codec@ff660000 {
1387 compatible = "rockchip,rk3399-vdec";
1392 clock-names = "axi", "ahb", "cabac", "core";
1394 power-domains = <&power RK3399_PD_VDU>;
1402 clock-names = "aclk", "iface";
1403 power-domains = <&power RK3399_PD_VDU>;
1404 #iommu-cells = <0>;
1412 clock-names = "aclk", "iface";
1413 #iommu-cells = <0>;
1418 compatible = "rockchip,rk3399-rga";
1422 clock-names = "aclk", "hclk", "sclk";
1424 reset-names = "core", "axi", "ahb";
1425 power-domains = <&power RK3399_PD_RGA>;
1429 compatible = "rockchip,rk3399-efuse";
1431 #address-cells = <1>;
1432 #size-cells = <1>;
1434 clock-names = "pclk_efuse";
1437 cpu_id: cpu-id@7 {
1440 cpub_leakage: cpu-leakage@17 {
1443 gpu_leakage: gpu-leakage@18 {
1446 center_leakage: center-leakage@19 {
1449 cpul_leakage: cpu-leakage@1a {
1452 logic_leakage: logic-leakage@1b {
1455 wafer_info: wafer-info@1c {
1460 dmac_bus: dma-controller@ff6d0000 {
1465 #dma-cells = <1>;
1466 arm,pl330-periph-burst;
1468 clock-names = "apb_pclk";
1471 dmac_peri: dma-controller@ff6e0000 {
1476 #dma-cells = <1>;
1477 arm,pl330-periph-burst;
1479 clock-names = "apb_pclk";
1482 pmucru: clock-controller@ff750000 {
1483 compatible = "rockchip,rk3399-pmucru";
1486 clock-names = "xin24m";
1488 #clock-cells = <1>;
1489 #reset-cells = <1>;
1490 assigned-clocks = <&pmucru PLL_PPLL>;
1491 assigned-clock-rates = <676000000>;
1494 cru: clock-controller@ff760000 {
1495 compatible = "rockchip,rk3399-cru";
1498 clock-names = "xin24m";
1500 #clock-cells = <1>;
1501 #reset-cells = <1>;
1502 assigned-clocks =
1514 assigned-clock-rates =
1529 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1531 #address-cells = <1>;
1532 #size-cells = <1>;
1534 io_domains: io-domains {
1535 compatible = "rockchip,rk3399-io-voltage-domain";
1539 mipi_dphy_rx0: mipi-dphy-rx0 {
1540 compatible = "rockchip,rk3399-mipi-dphy-rx0";
1544 clock-names = "dphy-ref", "dphy-cfg", "grf";
1545 power-domains = <&power RK3399_PD_VIO>;
1546 #phy-cells = <0>;
1551 compatible = "rockchip,rk3399-usb2phy";
1554 clock-names = "phyclk";
1555 #clock-cells = <0>;
1556 clock-output-names = "clk_usbphy0_480m";
1559 u2phy0_host: host-port {
1560 #phy-cells = <0>;
1562 interrupt-names = "linestate";
1566 u2phy0_otg: otg-port {
1567 #phy-cells = <0>;
1571 interrupt-names = "otg-bvalid", "otg-id",
1578 compatible = "rockchip,rk3399-usb2phy";
1581 clock-names = "phyclk";
1582 #clock-cells = <0>;
1583 clock-output-names = "clk_usbphy1_480m";
1586 u2phy1_host: host-port {
1587 #phy-cells = <0>;
1589 interrupt-names = "linestate";
1593 u2phy1_otg: otg-port {
1594 #phy-cells = <0>;
1598 interrupt-names = "otg-bvalid", "otg-id",
1605 compatible = "rockchip,rk3399-emmc-phy";
1608 clock-names = "emmcclk";
1609 drive-impedance-ohm = <50>;
1610 #phy-cells = <0>;
1614 pcie_phy: pcie-phy {
1615 compatible = "rockchip,rk3399-pcie-phy";
1617 clock-names = "refclk";
1618 #phy-cells = <1>;
1620 reset-names = "phy";
1626 compatible = "rockchip,rk3399-typec-phy";
1630 clock-names = "tcpdcore", "tcpdphy-ref";
1631 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1632 assigned-clock-rates = <50000000>;
1633 power-domains = <&power RK3399_PD_TCPD0>;
1637 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1641 tcphy0_dp: dp-port {
1642 #phy-cells = <0>;
1645 tcphy0_usb3: usb3-port {
1646 #phy-cells = <0>;
1651 compatible = "rockchip,rk3399-typec-phy";
1655 clock-names = "tcpdcore", "tcpdphy-ref";
1656 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1657 assigned-clock-rates = <50000000>;
1658 power-domains = <&power RK3399_PD_TCPD1>;
1662 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1666 tcphy1_dp: dp-port {
1667 #phy-cells = <0>;
1670 tcphy1_usb3: usb3-port {
1671 #phy-cells = <0>;
1676 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
1683 compatible = "rockchip,rk3399-timer";
1687 clock-names = "pclk", "timer";
1691 compatible = "rockchip,rk3399-spdif";
1695 dma-names = "tx";
1696 clock-names = "mclk", "hclk";
1698 pinctrl-names = "default";
1699 pinctrl-0 = <&spdif_bus>;
1700 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1701 #sound-dai-cells = <0>;
1706 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1711 dma-names = "tx", "rx";
1712 clock-names = "i2s_clk", "i2s_hclk";
1714 pinctrl-names = "bclk_on", "bclk_off";
1715 pinctrl-0 = <&i2s0_8ch_bus>;
1716 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
1717 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1718 #sound-dai-cells = <0>;
1723 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1727 dma-names = "tx", "rx";
1728 clock-names = "i2s_clk", "i2s_hclk";
1730 pinctrl-names = "default";
1731 pinctrl-0 = <&i2s1_2ch_bus>;
1732 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1733 #sound-dai-cells = <0>;
1738 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1742 dma-names = "tx", "rx";
1743 clock-names = "i2s_clk", "i2s_hclk";
1745 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1746 #sound-dai-cells = <0>;
1751 compatible = "rockchip,rk3399-vop-lit";
1754 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1755 assigned-clock-rates = <400000000>, <100000000>;
1757 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1759 power-domains = <&power RK3399_PD_VOPL>;
1761 reset-names = "axi", "ahb", "dclk";
1765 #address-cells = <1>;
1766 #size-cells = <0>;
1770 remote-endpoint = <&mipi_in_vopl>;
1775 remote-endpoint = <&edp_in_vopl>;
1780 remote-endpoint = <&hdmi_in_vopl>;
1785 remote-endpoint = <&mipi1_in_vopl>;
1790 remote-endpoint = <&dp_in_vopl>;
1800 clock-names = "aclk", "iface";
1801 power-domains = <&power RK3399_PD_VOPL>;
1802 #iommu-cells = <0>;
1807 compatible = "rockchip,rk3399-vop-big";
1810 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1811 assigned-clock-rates = <400000000>, <100000000>;
1813 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1815 power-domains = <&power RK3399_PD_VOPB>;
1817 reset-names = "axi", "ahb", "dclk";
1821 #address-cells = <1>;
1822 #size-cells = <0>;
1826 remote-endpoint = <&edp_in_vopb>;
1831 remote-endpoint = <&mipi_in_vopb>;
1836 remote-endpoint = <&hdmi_in_vopb>;
1841 remote-endpoint = <&mipi1_in_vopb>;
1846 remote-endpoint = <&dp_in_vopb>;
1856 clock-names = "aclk", "iface";
1857 power-domains = <&power RK3399_PD_VOPB>;
1858 #iommu-cells = <0>;
1863 compatible = "rockchip,rk3399-cif-isp";
1869 clock-names = "isp", "aclk", "hclk";
1872 phy-names = "dphy";
1873 power-domains = <&power RK3399_PD_ISP0>;
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1893 clock-names = "aclk", "iface";
1894 #iommu-cells = <0>;
1895 power-domains = <&power RK3399_PD_ISP0>;
1896 rockchip,disable-mmu-reset;
1900 compatible = "rockchip,rk3399-cif-isp";
1906 clock-names = "isp", "aclk", "hclk";
1909 phy-names = "dphy";
1910 power-domains = <&power RK3399_PD_ISP1>;
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1930 clock-names = "aclk", "iface";
1931 #iommu-cells = <0>;
1932 power-domains = <&power RK3399_PD_ISP1>;
1933 rockchip,disable-mmu-reset;
1936 hdmi_sound: hdmi-sound {
1937 compatible = "simple-audio-card";
1938 simple-audio-card,format = "i2s";
1939 simple-audio-card,mclk-fs = <256>;
1940 simple-audio-card,name = "hdmi-sound";
1943 simple-audio-card,cpu {
1944 sound-dai = <&i2s2>;
1946 simple-audio-card,codec {
1947 sound-dai = <&hdmi>;
1952 compatible = "rockchip,rk3399-dw-hdmi";
1960 clock-names = "iahb", "isfr", "cec", "grf", "ref";
1961 power-domains = <&power RK3399_PD_HDCP>;
1962 reg-io-width = <4>;
1964 #sound-dai-cells = <0>;
1969 #address-cells = <1>;
1970 #size-cells = <0>;
1974 remote-endpoint = <&vopb_out_hdmi>;
1978 remote-endpoint = <&vopl_out_hdmi>;
1985 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1990 clock-names = "ref", "pclk", "phy_cfg", "grf";
1991 power-domains = <&power RK3399_PD_VIO>;
1993 reset-names = "apb";
1995 #address-cells = <1>;
1996 #size-cells = <0>;
2000 #address-cells = <1>;
2001 #size-cells = <0>;
2005 #address-cells = <1>;
2006 #size-cells = <0>;
2010 remote-endpoint = <&vopb_out_mipi>;
2015 remote-endpoint = <&vopl_out_mipi>;
2026 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
2031 clock-names = "ref", "pclk", "phy_cfg", "grf";
2032 power-domains = <&power RK3399_PD_VIO>;
2034 reset-names = "apb";
2036 #address-cells = <1>;
2037 #size-cells = <0>;
2038 #phy-cells = <0>;
2042 #address-cells = <1>;
2043 #size-cells = <0>;
2047 #address-cells = <1>;
2048 #size-cells = <0>;
2052 remote-endpoint = <&vopb_out_mipi1>;
2057 remote-endpoint = <&vopl_out_mipi1>;
2068 compatible = "rockchip,rk3399-edp";
2072 clock-names = "dp", "pclk", "grf";
2073 pinctrl-names = "default";
2074 pinctrl-0 = <&edp_hpd>;
2075 power-domains = <&power RK3399_PD_EDP>;
2077 reset-names = "dp";
2082 #address-cells = <1>;
2083 #size-cells = <0>;
2087 #address-cells = <1>;
2088 #size-cells = <0>;
2092 remote-endpoint = <&vopb_out_edp>;
2097 remote-endpoint = <&vopl_out_edp>;
2108 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
2113 interrupt-names = "job", "mmu", "gpu";
2115 #cooling-cells = <2>;
2116 power-domains = <&power RK3399_PD_GPU>;
2121 compatible = "rockchip,rk3399-pinctrl";
2124 #address-cells = <2>;
2125 #size-cells = <2>;
2129 compatible = "rockchip,gpio-bank";
2134 gpio-controller;
2135 #gpio-cells = <0x2>;
2137 interrupt-controller;
2138 #interrupt-cells = <0x2>;
2142 compatible = "rockchip,gpio-bank";
2147 gpio-controller;
2148 #gpio-cells = <0x2>;
2150 interrupt-controller;
2151 #interrupt-cells = <0x2>;
2155 compatible = "rockchip,gpio-bank";
2160 gpio-controller;
2161 #gpio-cells = <0x2>;
2163 interrupt-controller;
2164 #interrupt-cells = <0x2>;
2168 compatible = "rockchip,gpio-bank";
2173 gpio-controller;
2174 #gpio-cells = <0x2>;
2176 interrupt-controller;
2177 #interrupt-cells = <0x2>;
2181 compatible = "rockchip,gpio-bank";
2186 gpio-controller;
2187 #gpio-cells = <0x2>;
2189 interrupt-controller;
2190 #interrupt-cells = <0x2>;
2193 pcfg_pull_up: pcfg-pull-up {
2194 bias-pull-up;
2197 pcfg_pull_down: pcfg-pull-down {
2198 bias-pull-down;
2201 pcfg_pull_none: pcfg-pull-none {
2202 bias-disable;
2205 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2206 bias-disable;
2207 drive-strength = <12>;
2210 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2211 bias-disable;
2212 drive-strength = <13>;
2215 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2216 bias-disable;
2217 drive-strength = <18>;
2220 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2221 bias-disable;
2222 drive-strength = <20>;
2225 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2226 bias-pull-up;
2227 drive-strength = <2>;
2230 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2231 bias-pull-up;
2232 drive-strength = <8>;
2235 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2236 bias-pull-up;
2237 drive-strength = <18>;
2240 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2241 bias-pull-up;
2242 drive-strength = <20>;
2245 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2246 bias-pull-down;
2247 drive-strength = <4>;
2250 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2251 bias-pull-down;
2252 drive-strength = <8>;
2255 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2256 bias-pull-down;
2257 drive-strength = <12>;
2260 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2261 bias-pull-down;
2262 drive-strength = <18>;
2265 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2266 bias-pull-down;
2267 drive-strength = <20>;
2270 pcfg_output_high: pcfg-output-high {
2271 output-high;
2274 pcfg_output_low: pcfg-output-low {
2275 output-low;
2278 pcfg_input_enable: pcfg-input-enable {
2279 input-enable;
2282 pcfg_input_pull_up: pcfg-input-pull-up {
2283 input-enable;
2284 bias-pull-up;
2287 pcfg_input_pull_down: pcfg-input-pull-down {
2288 input-enable;
2289 bias-pull-down;
2293 clk_32k: clk-32k {
2299 cif_clkin: cif-clkin {
2304 cif_clkouta: cif-clkouta {
2311 edp_hpd: edp-hpd {
2318 rgmii_pins: rgmii-pins {
2352 rmii_pins: rmii-pins {
2378 i2c0_xfer: i2c0-xfer {
2386 i2c1_xfer: i2c1-xfer {
2394 i2c2_xfer: i2c2-xfer {
2402 i2c3_xfer: i2c3-xfer {
2410 i2c4_xfer: i2c4-xfer {
2418 i2c5_xfer: i2c5-xfer {
2426 i2c6_xfer: i2c6-xfer {
2434 i2c7_xfer: i2c7-xfer {
2442 i2c8_xfer: i2c8-xfer {
2450 i2s0_2ch_bus: i2s0-2ch-bus {
2460 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
2470 i2s0_8ch_bus: i2s0-8ch-bus {
2483 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
2498 i2s1_2ch_bus: i2s1-2ch-bus {
2507 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
2518 sdio0_bus1: sdio0-bus1 {
2523 sdio0_bus4: sdio0-bus4 {
2531 sdio0_cmd: sdio0-cmd {
2536 sdio0_clk: sdio0-clk {
2541 sdio0_cd: sdio0-cd {
2546 sdio0_pwr: sdio0-pwr {
2551 sdio0_bkpwr: sdio0-bkpwr {
2556 sdio0_wp: sdio0-wp {
2561 sdio0_int: sdio0-int {
2568 sdmmc_bus1: sdmmc-bus1 {
2573 sdmmc_bus4: sdmmc-bus4 {
2581 sdmmc_clk: sdmmc-clk {
2586 sdmmc_cmd: sdmmc-cmd {
2591 sdmmc_cd: sdmmc-cd {
2596 sdmmc_wp: sdmmc-wp {
2603 ap_pwroff: ap-pwroff {
2607 ddrio_pwroff: ddrio-pwroff {
2613 spdif_bus: spdif-bus {
2618 spdif_bus_1: spdif-bus-1 {
2625 spi0_clk: spi0-clk {
2629 spi0_cs0: spi0-cs0 {
2633 spi0_cs1: spi0-cs1 {
2637 spi0_tx: spi0-tx {
2641 spi0_rx: spi0-rx {
2648 spi1_clk: spi1-clk {
2652 spi1_cs0: spi1-cs0 {
2656 spi1_rx: spi1-rx {
2660 spi1_tx: spi1-tx {
2667 spi2_clk: spi2-clk {
2671 spi2_cs0: spi2-cs0 {
2675 spi2_rx: spi2-rx {
2679 spi2_tx: spi2-tx {
2686 spi3_clk: spi3-clk {
2690 spi3_cs0: spi3-cs0 {
2694 spi3_rx: spi3-rx {
2698 spi3_tx: spi3-tx {
2705 spi4_clk: spi4-clk {
2709 spi4_cs0: spi4-cs0 {
2713 spi4_rx: spi4-rx {
2717 spi4_tx: spi4-tx {
2724 spi5_clk: spi5-clk {
2728 spi5_cs0: spi5-cs0 {
2732 spi5_rx: spi5-rx {
2736 spi5_tx: spi5-tx {
2743 test_clkout0: test-clkout0 {
2748 test_clkout1: test-clkout1 {
2753 test_clkout2: test-clkout2 {
2760 otp_pin: otp-pin {
2764 otp_out: otp-out {
2770 uart0_xfer: uart0-xfer {
2776 uart0_cts: uart0-cts {
2781 uart0_rts: uart0-rts {
2788 uart1_xfer: uart1-xfer {
2796 uart2a_xfer: uart2a-xfer {
2804 uart2b_xfer: uart2b-xfer {
2812 uart2c_xfer: uart2c-xfer {
2820 uart3_xfer: uart3-xfer {
2826 uart3_cts: uart3-cts {
2831 uart3_rts: uart3-rts {
2838 uart4_xfer: uart4-xfer {
2846 uarthdcp_xfer: uarthdcp-xfer {
2854 pwm0_pin: pwm0-pin {
2859 pwm0_pin_pull_down: pwm0-pin-pull-down {
2864 vop0_pwm_pin: vop0-pwm-pin {
2869 vop1_pwm_pin: vop1-pwm-pin {
2876 pwm1_pin: pwm1-pin {
2881 pwm1_pin_pull_down: pwm1-pin-pull-down {
2888 pwm2_pin: pwm2-pin {
2893 pwm2_pin_pull_down: pwm2-pin-pull-down {
2900 pwm3a_pin: pwm3a-pin {
2907 pwm3b_pin: pwm3b-pin {
2914 hdmi_i2c_xfer: hdmi-i2c-xfer {
2920 hdmi_cec: hdmi-cec {
2927 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2932 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {