Lines Matching +full:sclk +full:- +full:strength
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
38 #address-cells = <2>;
39 #size-cells = <0>;
43 compatible = "arm,cortex-a35";
45 enable-method = "psci";
47 #cooling-cells = <2>;
48 dynamic-power-coefficient = <90>;
49 operating-points-v2 = <&cpu0_opp_table>;
50 cpu-idle-states = <&CPU_SLEEP>;
51 next-level-cache = <&l2>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP>;
61 next-level-cache = <&l2>;
66 compatible = "arm,cortex-a35";
68 enable-method = "psci";
69 operating-points-v2 = <&cpu0_opp_table>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 next-level-cache = <&l2>;
76 compatible = "arm,cortex-a35";
78 enable-method = "psci";
79 operating-points-v2 = <&cpu0_opp_table>;
80 cpu-idle-states = <&CPU_SLEEP>;
81 next-level-cache = <&l2>;
84 idle-states {
85 entry-method = "psci";
87 CPU_SLEEP: cpu-sleep {
88 compatible = "arm,idle-state";
89 local-timer-stop;
90 arm,psci-suspend-param = <0x0010000>;
91 entry-latency-us = <120>;
92 exit-latency-us = <250>;
93 min-residency-us = <900>;
97 l2: l2-cache {
99 cache-level = <2>;
100 cache-unified;
104 cpu0_opp_table: opp-table-0 {
105 compatible = "operating-points-v2";
106 opp-shared;
108 opp-408000000 {
109 opp-hz = /bits/ 64 <408000000>;
110 opp-microvolt = <950000 950000 1340000>;
111 clock-latency-ns = <40000>;
112 opp-suspend;
114 opp-600000000 {
115 opp-hz = /bits/ 64 <600000000>;
116 opp-microvolt = <950000 950000 1340000>;
117 clock-latency-ns = <40000>;
119 opp-816000000 {
120 opp-hz = /bits/ 64 <816000000>;
121 opp-microvolt = <1025000 1025000 1340000>;
122 clock-latency-ns = <40000>;
124 opp-1008000000 {
125 opp-hz = /bits/ 64 <1008000000>;
126 opp-microvolt = <1125000 1125000 1340000>;
127 clock-latency-ns = <40000>;
131 arm-pmu {
132 compatible = "arm,cortex-a35-pmu";
137 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
140 mac_clkin: external-mac-clock {
141 compatible = "fixed-clock";
142 clock-frequency = <50000000>;
143 clock-output-names = "mac_clkin";
144 #clock-cells = <0>;
148 compatible = "arm,psci-1.0";
153 compatible = "arm,armv8-timer";
161 compatible = "fixed-clock";
162 #clock-cells = <0>;
163 clock-frequency = <24000000>;
164 clock-output-names = "xin24m";
168 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
171 reboot-mode {
172 compatible = "syscon-reboot-mode";
174 mode-bootloader = <BOOT_BL_DOWNLOAD>;
175 mode-loader = <BOOT_BL_DOWNLOAD>;
176 mode-normal = <BOOT_NORMAL>;
177 mode-recovery = <BOOT_RECOVERY>;
178 mode-fastboot = <BOOT_FASTBOOT>;
183 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
185 #address-cells = <1>;
186 #size-cells = <1>;
189 compatible = "rockchip,rk3308-usb2phy";
191 assigned-clocks = <&cru USB480M>;
192 assigned-clock-parents = <&u2phy>;
194 clock-names = "phyclk";
195 clock-output-names = "usb480m_phy";
196 #clock-cells = <0>;
199 u2phy_otg: otg-port {
203 interrupt-names = "otg-bvalid", "otg-id",
205 #phy-cells = <0>;
209 u2phy_host: host-port {
211 interrupt-names = "linestate";
212 #phy-cells = <0>;
219 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
221 #address-cells = <1>;
222 #size-cells = <1>;
226 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
228 #address-cells = <1>;
229 #size-cells = <1>;
233 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
236 clock-names = "i2c", "pclk";
238 pinctrl-names = "default";
239 pinctrl-0 = <&i2c0_xfer>;
240 #address-cells = <1>;
241 #size-cells = <0>;
246 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
249 clock-names = "i2c", "pclk";
251 pinctrl-names = "default";
252 pinctrl-0 = <&i2c1_xfer>;
253 #address-cells = <1>;
254 #size-cells = <0>;
259 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
262 clock-names = "i2c", "pclk";
264 pinctrl-names = "default";
265 pinctrl-0 = <&i2c2_xfer>;
266 #address-cells = <1>;
267 #size-cells = <0>;
272 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
275 clock-names = "i2c", "pclk";
277 pinctrl-names = "default";
278 pinctrl-0 = <&i2c3m0_xfer>;
279 #address-cells = <1>;
280 #size-cells = <0>;
285 compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
293 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
297 clock-names = "baudclk", "apb_pclk";
298 reg-shift = <2>;
299 reg-io-width = <4>;
300 pinctrl-names = "default";
301 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
306 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
310 clock-names = "baudclk", "apb_pclk";
311 reg-shift = <2>;
312 reg-io-width = <4>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
319 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
323 clock-names = "baudclk", "apb_pclk";
324 reg-shift = <2>;
325 reg-io-width = <4>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&uart2m0_xfer>;
332 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
336 clock-names = "baudclk", "apb_pclk";
337 reg-shift = <2>;
338 reg-io-width = <4>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart3_xfer>;
345 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
349 clock-names = "baudclk", "apb_pclk";
350 reg-shift = <2>;
351 reg-io-width = <4>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
358 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
361 #address-cells = <1>;
362 #size-cells = <0>;
364 clock-names = "spiclk", "apb_pclk";
366 dma-names = "tx", "rx";
367 pinctrl-names = "default";
368 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
373 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
376 #address-cells = <1>;
377 #size-cells = <0>;
379 clock-names = "spiclk", "apb_pclk";
381 dma-names = "tx", "rx";
382 pinctrl-names = "default";
383 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
388 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
391 #address-cells = <1>;
392 #size-cells = <0>;
394 clock-names = "spiclk", "apb_pclk";
396 dma-names = "tx", "rx";
397 pinctrl-names = "default";
398 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
403 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
406 clock-names = "pwm", "pclk";
407 pinctrl-names = "default";
408 pinctrl-0 = <&pwm8_pin>;
409 #pwm-cells = <3>;
414 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
417 clock-names = "pwm", "pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&pwm9_pin>;
420 #pwm-cells = <3>;
425 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
428 clock-names = "pwm", "pclk";
429 pinctrl-names = "default";
430 pinctrl-0 = <&pwm10_pin>;
431 #pwm-cells = <3>;
436 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
439 clock-names = "pwm", "pclk";
440 pinctrl-names = "default";
441 pinctrl-0 = <&pwm11_pin>;
442 #pwm-cells = <3>;
447 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
450 clock-names = "pwm", "pclk";
451 pinctrl-names = "default";
452 pinctrl-0 = <&pwm4_pin>;
453 #pwm-cells = <3>;
458 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
461 clock-names = "pwm", "pclk";
462 pinctrl-names = "default";
463 pinctrl-0 = <&pwm5_pin>;
464 #pwm-cells = <3>;
469 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
472 clock-names = "pwm", "pclk";
473 pinctrl-names = "default";
474 pinctrl-0 = <&pwm6_pin>;
475 #pwm-cells = <3>;
480 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
483 clock-names = "pwm", "pclk";
484 pinctrl-names = "default";
485 pinctrl-0 = <&pwm7_pin>;
486 #pwm-cells = <3>;
491 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
494 clock-names = "pwm", "pclk";
495 pinctrl-names = "default";
496 pinctrl-0 = <&pwm0_pin>;
497 #pwm-cells = <3>;
502 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
505 clock-names = "pwm", "pclk";
506 pinctrl-names = "default";
507 pinctrl-0 = <&pwm1_pin>;
508 #pwm-cells = <3>;
513 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
516 clock-names = "pwm", "pclk";
517 pinctrl-names = "default";
518 pinctrl-0 = <&pwm2_pin>;
519 #pwm-cells = <3>;
524 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
527 clock-names = "pwm", "pclk";
528 pinctrl-names = "default";
529 pinctrl-0 = <&pwm3_pin>;
530 #pwm-cells = <3>;
535 compatible = "rockchip,rk3288-timer";
539 clock-names = "pclk", "timer";
543 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
547 clock-names = "saradc", "apb_pclk";
548 #io-channel-cells = <1>;
550 reset-names = "saradc-apb";
554 dmac0: dma-controller@ff2c0000 {
559 arm,pl330-periph-burst;
561 clock-names = "apb_pclk";
562 #dma-cells = <1>;
565 dmac1: dma-controller@ff2d0000 {
570 arm,pl330-periph-burst;
572 clock-names = "apb_pclk";
573 #dma-cells = <1>;
577 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
581 clock-names = "i2s_clk", "i2s_hclk";
583 dma-names = "tx", "rx";
585 reset-names = "reset-m", "reset-h";
586 pinctrl-names = "default";
587 pinctrl-0 = <&i2s_2ch_0_sclk
595 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
599 clock-names = "i2s_clk", "i2s_hclk";
601 dma-names = "rx";
603 reset-names = "reset-m", "reset-h";
607 spdif_tx: spdif-tx@ff3a0000 {
608 compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
612 clock-names = "mclk", "hclk";
614 dma-names = "tx";
615 pinctrl-names = "default";
616 pinctrl-0 = <&spdif_out>;
621 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
626 clock-names = "otg";
628 g-np-tx-fifo-size = <16>;
629 g-rx-fifo-size = <280>;
630 g-tx-fifo-size = <256 128 128 64 32 16>;
632 phy-names = "usb2-phy";
637 compatible = "generic-ehci";
642 phy-names = "usb";
647 compatible = "generic-ohci";
652 phy-names = "usb";
657 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
660 bus-width = <4>;
663 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
664 fifo-depth = <0x100>;
665 max-frequency = <150000000>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
672 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
675 bus-width = <8>;
678 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
679 fifo-depth = <0x100>;
680 max-frequency = <150000000>;
685 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
688 bus-width = <4>;
691 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
692 fifo-depth = <0x100>;
693 max-frequency = <150000000>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
699 nfc: nand-controller@ff4b0000 {
700 compatible = "rockchip,rk3308-nfc",
701 "rockchip,rv1108-nfc";
705 clock-names = "ahb", "nfc";
706 assigned-clocks = <&cru SCLK_NANDC>;
707 assigned-clock-rates = <150000000>;
708 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
710 pinctrl-names = "default";
715 compatible = "rockchip,rk3308-gmac";
718 interrupt-names = "macirq";
723 clock-names = "stmmaceth", "mac_clk_rx",
727 phy-mode = "rmii";
728 pinctrl-names = "default";
729 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
731 reset-names = "stmmaceth";
741 clock-names = "clk_sfc", "hclk_sfc";
742 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
743 pinctrl-names = "default";
747 cru: clock-controller@ff500000 {
748 compatible = "rockchip,rk3308-cru";
751 clock-names = "xin24m";
753 #clock-cells = <1>;
754 #reset-cells = <1>;
755 assigned-clocks = <&cru SCLK_RTC32K>;
756 assigned-clock-rates = <32768>;
759 gic: interrupt-controller@ff580000 {
760 compatible = "arm,gic-400";
766 #interrupt-cells = <3>;
767 interrupt-controller;
768 #address-cells = <0>;
772 compatible = "mmio-sram";
775 #address-cells = <1>;
776 #size-cells = <1>;
779 ddr-sram@0 {
784 vad_sram: vad-sram@8000 {
790 compatible = "rockchip,rk3308-pinctrl";
792 #address-cells = <2>;
793 #size-cells = <2>;
797 compatible = "rockchip,gpio-bank";
801 gpio-controller;
802 #gpio-cells = <2>;
803 interrupt-controller;
804 #interrupt-cells = <2>;
808 compatible = "rockchip,gpio-bank";
812 gpio-controller;
813 #gpio-cells = <2>;
814 interrupt-controller;
815 #interrupt-cells = <2>;
819 compatible = "rockchip,gpio-bank";
823 gpio-controller;
824 #gpio-cells = <2>;
825 interrupt-controller;
826 #interrupt-cells = <2>;
830 compatible = "rockchip,gpio-bank";
834 gpio-controller;
835 #gpio-cells = <2>;
836 interrupt-controller;
837 #interrupt-cells = <2>;
841 compatible = "rockchip,gpio-bank";
845 gpio-controller;
846 #gpio-cells = <2>;
847 interrupt-controller;
848 #interrupt-cells = <2>;
851 pcfg_pull_up: pcfg-pull-up {
852 bias-pull-up;
855 pcfg_pull_down: pcfg-pull-down {
856 bias-pull-down;
859 pcfg_pull_none: pcfg-pull-none {
860 bias-disable;
863 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
864 bias-disable;
865 drive-strength = <2>;
868 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
869 bias-pull-up;
870 drive-strength = <2>;
873 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
874 bias-pull-up;
875 drive-strength = <4>;
878 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
879 bias-disable;
880 drive-strength = <4>;
883 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
884 bias-pull-down;
885 drive-strength = <4>;
888 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
889 bias-disable;
890 drive-strength = <8>;
893 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
894 bias-pull-up;
895 drive-strength = <8>;
898 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
899 bias-disable;
900 drive-strength = <12>;
903 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
904 bias-pull-up;
905 drive-strength = <12>;
908 pcfg_pull_none_smt: pcfg-pull-none-smt {
909 bias-disable;
910 input-schmitt-enable;
913 pcfg_output_high: pcfg-output-high {
914 output-high;
917 pcfg_output_low: pcfg-output-low {
918 output-low;
921 pcfg_input_high: pcfg-input-high {
922 bias-pull-up;
923 input-enable;
926 pcfg_input: pcfg-input {
927 input-enable;
931 emmc_clk: emmc-clk {
936 emmc_cmd: emmc-cmd {
941 emmc_pwren: emmc-pwren {
946 emmc_rstn: emmc-rstn {
951 emmc_bus1: emmc-bus1 {
956 emmc_bus4: emmc-bus4 {
964 emmc_bus8: emmc-bus8 {
978 flash_csn0: flash-csn0 {
983 flash_rdy: flash-rdy {
988 flash_ale: flash-ale {
993 flash_cle: flash-cle {
998 flash_wrn: flash-wrn {
1003 flash_rdn: flash-rdn {
1008 flash_bus8: flash-bus8 {
1022 sfc_bus4: sfc-bus4 {
1030 sfc_bus2: sfc-bus2 {
1036 sfc_cs0: sfc-cs0 {
1041 sfc_clk: sfc-clk {
1048 rmii_pins: rmii-pins {
1070 mac_refclk_12ma: mac-refclk-12ma {
1075 mac_refclk: mac-refclk {
1081 gmac-m1 {
1082 rmiim1_pins: rmiim1-pins {
1104 macm1_refclk_12ma: macm1-refclk-12ma {
1109 macm1_refclk: macm1-refclk {
1116 i2c0_xfer: i2c0-xfer {
1124 i2c1_xfer: i2c1-xfer {
1132 i2c2_xfer: i2c2-xfer {
1139 i2c3-m0 {
1140 i2c3m0_xfer: i2c3m0-xfer {
1147 i2c3-m1 {
1148 i2c3m1_xfer: i2c3m1-xfer {
1155 i2c3-m2 {
1156 i2c3m2_xfer: i2c3m2-xfer {
1164 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
1169 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
1174 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
1179 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
1184 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
1191 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
1196 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
1201 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
1206 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
1211 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
1216 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
1221 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
1226 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
1231 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
1236 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
1241 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
1246 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
1251 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
1258 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
1263 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
1268 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
1273 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
1278 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
1283 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
1288 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
1293 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
1298 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
1303 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1310 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1315 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1320 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1325 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1330 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1335 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1340 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1345 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1350 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1355 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1362 pdm_m0_clk: pdm-m0-clk {
1367 pdm_m0_sdi0: pdm-m0-sdi0 {
1372 pdm_m0_sdi1: pdm-m0-sdi1 {
1377 pdm_m0_sdi2: pdm-m0-sdi2 {
1382 pdm_m0_sdi3: pdm-m0-sdi3 {
1389 pdm_m1_clk: pdm-m1-clk {
1394 pdm_m1_sdi0: pdm-m1-sdi0 {
1399 pdm_m1_sdi1: pdm-m1-sdi1 {
1404 pdm_m1_sdi2: pdm-m1-sdi2 {
1409 pdm_m1_sdi3: pdm-m1-sdi3 {
1416 pdm_m2_clkm: pdm-m2-clkm {
1421 pdm_m2_clk: pdm-m2-clk {
1426 pdm_m2_sdi0: pdm-m2-sdi0 {
1431 pdm_m2_sdi1: pdm-m2-sdi1 {
1436 pdm_m2_sdi2: pdm-m2-sdi2 {
1441 pdm_m2_sdi3: pdm-m2-sdi3 {
1448 pwm0_pin: pwm0-pin {
1453 pwm0_pin_pull_down: pwm0-pin-pull-down {
1460 pwm1_pin: pwm1-pin {
1465 pwm1_pin_pull_down: pwm1-pin-pull-down {
1472 pwm2_pin: pwm2-pin {
1477 pwm2_pin_pull_down: pwm2-pin-pull-down {
1484 pwm3_pin: pwm3-pin {
1489 pwm3_pin_pull_down: pwm3-pin-pull-down {
1496 pwm4_pin: pwm4-pin {
1501 pwm4_pin_pull_down: pwm4-pin-pull-down {
1508 pwm5_pin: pwm5-pin {
1513 pwm5_pin_pull_down: pwm5-pin-pull-down {
1520 pwm6_pin: pwm6-pin {
1525 pwm6_pin_pull_down: pwm6-pin-pull-down {
1532 pwm7_pin: pwm7-pin {
1537 pwm7_pin_pull_down: pwm7-pin-pull-down {
1544 pwm8_pin: pwm8-pin {
1549 pwm8_pin_pull_down: pwm8-pin-pull-down {
1556 pwm9_pin: pwm9-pin {
1561 pwm9_pin_pull_down: pwm9-pin-pull-down {
1568 pwm10_pin: pwm10-pin {
1573 pwm10_pin_pull_down: pwm10-pin-pull-down {
1580 pwm11_pin: pwm11-pin {
1585 pwm11_pin_pull_down: pwm11-pin-pull-down {
1592 rtc_32k: rtc-32k {
1599 sdmmc_clk: sdmmc-clk {
1604 sdmmc_cmd: sdmmc-cmd {
1609 sdmmc_det: sdmmc-det {
1614 sdmmc_pwren: sdmmc-pwren {
1619 sdmmc_bus1: sdmmc-bus1 {
1624 sdmmc_bus4: sdmmc-bus4 {
1634 sdio_clk: sdio-clk {
1639 sdio_cmd: sdio-cmd {
1644 sdio_pwren: sdio-pwren {
1649 sdio_wrpt: sdio-wrpt {
1654 sdio_intn: sdio-intn {
1659 sdio_bus1: sdio-bus1 {
1664 sdio_bus4: sdio-bus4 {
1674 spdif_in: spdif-in {
1681 spdif_out: spdif-out {
1688 spi0_clk: spi0-clk {
1693 spi0_csn0: spi0-csn0 {
1698 spi0_miso: spi0-miso {
1703 spi0_mosi: spi0-mosi {
1710 spi1_clk: spi1-clk {
1715 spi1_csn0: spi1-csn0 {
1720 spi1_miso: spi1-miso {
1725 spi1_mosi: spi1-mosi {
1731 spi1-m1 {
1732 spi1m1_miso: spi1m1-miso {
1737 spi1m1_mosi: spi1m1-mosi {
1742 spi1m1_clk: spi1m1-clk {
1747 spi1m1_csn0: spi1m1-csn0 {
1754 spi2_clk: spi2-clk {
1759 spi2_csn0: spi2-csn0 {
1764 spi2_miso: spi2-miso {
1769 spi2_mosi: spi2-mosi {
1776 tsadc_otp_pin: tsadc-otp-pin {
1781 tsadc_otp_out: tsadc-otp-out {
1788 uart0_xfer: uart0-xfer {
1794 uart0_cts: uart0-cts {
1799 uart0_rts: uart0-rts {
1804 uart0_rts_pin: uart0-rts-pin {
1811 uart1_xfer: uart1-xfer {
1817 uart1_cts: uart1-cts {
1822 uart1_rts: uart1-rts {
1828 uart2-m0 {
1829 uart2m0_xfer: uart2m0-xfer {
1836 uart2-m1 {
1837 uart2m1_xfer: uart2m1-xfer {
1845 uart3_xfer: uart3-xfer {
1852 uart3-m1 {
1853 uart3m1_xfer: uart3m1-xfer {
1861 uart4_xfer: uart4-xfer {
1867 uart4_cts: uart4-cts {
1872 uart4_rts: uart4-rts {
1877 uart4_rts_pin: uart4-rts-pin {