Lines Matching +full:rk3399 +full:- +full:cif +full:- +full:isp
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: opp-table-0 {
114 compatible = "operating-points-v2";
115 opp-shared;
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
194 target: trip-point-1 {
200 soc_crit: soc-crit {
207 cooling-maps {
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 gpu_thermal: gpu-thermal {
217 polling-delay-passive = <100>; /* milliseconds */
218 polling-delay = <1000>; /* milliseconds */
219 thermal-sensors = <&tsadc 1>;
222 gpu_threshold: gpu-threshold {
228 gpu_target: gpu-target {
234 gpu_crit: gpu-crit {
241 cooling-maps {
244 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
251 compatible = "fixed-clock";
252 #clock-cells = <0>;
253 clock-frequency = <24000000>;
254 clock-output-names = "xin24m";
257 pmu: power-management@ff000000 {
258 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
261 power: power-controller {
262 compatible = "rockchip,px30-power-controller";
263 #power-domain-cells = <1>;
264 #address-cells = <1>;
265 #size-cells = <0>;
268 power-domain@PX30_PD_USB {
274 #power-domain-cells = <0>;
276 power-domain@PX30_PD_SDCARD {
281 #power-domain-cells = <0>;
283 power-domain@PX30_PD_GMAC {
290 #power-domain-cells = <0>;
292 power-domain@PX30_PD_MMC_NAND {
304 #power-domain-cells = <0>;
306 power-domain@PX30_PD_VPU {
312 #power-domain-cells = <0>;
314 power-domain@PX30_PD_VO {
329 #power-domain-cells = <0>;
331 power-domain@PX30_PD_VI {
341 #power-domain-cells = <0>;
343 power-domain@PX30_PD_GPU {
347 #power-domain-cells = <0>;
353 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
355 #address-cells = <1>;
356 #size-cells = <1>;
358 pmu_io_domains: io-domains {
359 compatible = "rockchip,px30-pmu-io-voltage-domain";
363 reboot-mode {
364 compatible = "syscon-reboot-mode";
366 mode-bootloader = <BOOT_BL_DOWNLOAD>;
367 mode-fastboot = <BOOT_FASTBOOT>;
368 mode-loader = <BOOT_BL_DOWNLOAD>;
369 mode-normal = <BOOT_NORMAL>;
370 mode-recovery = <BOOT_RECOVERY>;
375 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
379 clock-names = "baudclk", "apb_pclk";
381 dma-names = "tx", "rx";
382 reg-shift = <2>;
383 reg-io-width = <4>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
390 compatible = "rockchip,px30-i2s-tdm";
394 clock-names = "mclk_tx", "mclk_rx", "hclk";
396 dma-names = "tx", "rx";
399 reset-names = "tx-m", "rx-m";
400 pinctrl-names = "default";
401 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
407 #sound-dai-cells = <0>;
412 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
416 clock-names = "i2s_clk", "i2s_hclk";
418 dma-names = "tx", "rx";
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
422 #sound-dai-cells = <0>;
427 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
431 clock-names = "i2s_clk", "i2s_hclk";
433 dma-names = "tx", "rx";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
437 #sound-dai-cells = <0>;
441 gic: interrupt-controller@ff131000 {
442 compatible = "arm,gic-400";
443 #interrupt-cells = <3>;
444 #address-cells = <0>;
445 interrupt-controller;
455 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
457 #address-cells = <1>;
458 #size-cells = <1>;
460 io_domains: io-domains {
461 compatible = "rockchip,px30-io-voltage-domain";
466 compatible = "rockchip,px30-lvds";
468 phy-names = "dphy";
474 #address-cells = <1>;
475 #size-cells = <0>;
479 #address-cells = <1>;
480 #size-cells = <0>;
484 remote-endpoint = <&vopb_out_lvds>;
489 remote-endpoint = <&vopl_out_lvds>;
501 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
505 clock-names = "baudclk", "apb_pclk";
507 dma-names = "tx", "rx";
508 reg-shift = <2>;
509 reg-io-width = <4>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
516 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
520 clock-names = "baudclk", "apb_pclk";
522 dma-names = "tx", "rx";
523 reg-shift = <2>;
524 reg-io-width = <4>;
525 pinctrl-names = "default";
526 pinctrl-0 = <&uart2m0_xfer>;
531 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
535 clock-names = "baudclk", "apb_pclk";
537 dma-names = "tx", "rx";
538 reg-shift = <2>;
539 reg-io-width = <4>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
546 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
550 clock-names = "baudclk", "apb_pclk";
552 dma-names = "tx", "rx";
553 reg-shift = <2>;
554 reg-io-width = <4>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
561 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
565 clock-names = "baudclk", "apb_pclk";
567 dma-names = "tx", "rx";
568 reg-shift = <2>;
569 reg-io-width = <4>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
576 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
579 clock-names = "i2c", "pclk";
581 pinctrl-names = "default";
582 pinctrl-0 = <&i2c0_xfer>;
583 #address-cells = <1>;
584 #size-cells = <0>;
589 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
592 clock-names = "i2c", "pclk";
594 pinctrl-names = "default";
595 pinctrl-0 = <&i2c1_xfer>;
596 #address-cells = <1>;
597 #size-cells = <0>;
602 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
605 clock-names = "i2c", "pclk";
607 pinctrl-names = "default";
608 pinctrl-0 = <&i2c2_xfer>;
609 #address-cells = <1>;
610 #size-cells = <0>;
615 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
618 clock-names = "i2c", "pclk";
620 pinctrl-names = "default";
621 pinctrl-0 = <&i2c3_xfer>;
622 #address-cells = <1>;
623 #size-cells = <0>;
628 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
632 clock-names = "spiclk", "apb_pclk";
634 dma-names = "tx", "rx";
635 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>;
638 #size-cells = <0>;
643 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
647 clock-names = "spiclk", "apb_pclk";
649 dma-names = "tx", "rx";
650 pinctrl-names = "default";
651 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
652 #address-cells = <1>;
653 #size-cells = <0>;
658 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
669 clock-names = "pwm", "pclk";
670 pinctrl-names = "default";
671 pinctrl-0 = <&pwm0_pin>;
672 #pwm-cells = <3>;
677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
680 clock-names = "pwm", "pclk";
681 pinctrl-names = "default";
682 pinctrl-0 = <&pwm1_pin>;
683 #pwm-cells = <3>;
688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
691 clock-names = "pwm", "pclk";
692 pinctrl-names = "default";
693 pinctrl-0 = <&pwm2_pin>;
694 #pwm-cells = <3>;
699 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
702 clock-names = "pwm", "pclk";
703 pinctrl-names = "default";
704 pinctrl-0 = <&pwm3_pin>;
705 #pwm-cells = <3>;
710 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
713 clock-names = "pwm", "pclk";
714 pinctrl-names = "default";
715 pinctrl-0 = <&pwm4_pin>;
716 #pwm-cells = <3>;
721 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
724 clock-names = "pwm", "pclk";
725 pinctrl-names = "default";
726 pinctrl-0 = <&pwm5_pin>;
727 #pwm-cells = <3>;
732 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
735 clock-names = "pwm", "pclk";
736 pinctrl-names = "default";
737 pinctrl-0 = <&pwm6_pin>;
738 #pwm-cells = <3>;
743 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
746 clock-names = "pwm", "pclk";
747 pinctrl-names = "default";
748 pinctrl-0 = <&pwm7_pin>;
749 #pwm-cells = <3>;
754 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
758 clock-names = "pclk", "timer";
761 dmac: dma-controller@ff240000 {
766 arm,pl330-periph-burst;
768 clock-names = "apb_pclk";
769 #dma-cells = <1>;
773 compatible = "rockchip,px30-tsadc";
776 assigned-clocks = <&cru SCLK_TSADC>;
777 assigned-clock-rates = <50000>;
779 clock-names = "tsadc", "apb_pclk";
781 reset-names = "tsadc-apb";
783 rockchip,hw-tshut-temp = <120000>;
784 pinctrl-names = "init", "default", "sleep";
785 pinctrl-0 = <&tsadc_otp_pin>;
786 pinctrl-1 = <&tsadc_otp_out>;
787 pinctrl-2 = <&tsadc_otp_pin>;
788 #thermal-sensor-cells = <1>;
793 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
796 #io-channel-cells = <1>;
798 clock-names = "saradc", "apb_pclk";
800 reset-names = "saradc-apb";
805 compatible = "rockchip,px30-otp";
809 clock-names = "otp", "apb_pclk", "phy";
811 reset-names = "phy";
812 #address-cells = <1>;
813 #size-cells = <1>;
819 cpu_leakage: cpu-leakage@17 {
828 cru: clock-controller@ff2b0000 {
829 compatible = "rockchip,px30-cru";
832 clock-names = "xin24m", "gpll";
834 #clock-cells = <1>;
835 #reset-cells = <1>;
837 assigned-clocks = <&cru PLL_NPLL>,
842 assigned-clock-rates = <1188000000>,
848 pmucru: clock-controller@ff2bc000 {
849 compatible = "rockchip,px30-pmucru";
852 clock-names = "xin24m";
854 #clock-cells = <1>;
855 #reset-cells = <1>;
857 assigned-clocks =
860 assigned-clock-rates =
866 compatible = "rockchip,px30-usb2phy-grf", "syscon",
867 "simple-mfd";
869 #address-cells = <1>;
870 #size-cells = <1>;
873 compatible = "rockchip,px30-usb2phy";
876 clock-names = "phyclk";
877 #clock-cells = <0>;
878 assigned-clocks = <&cru USB480M>;
879 assigned-clock-parents = <&u2phy>;
880 clock-output-names = "usb480m_phy";
883 u2phy_host: host-port {
884 #phy-cells = <0>;
886 interrupt-names = "linestate";
890 u2phy_otg: otg-port {
891 #phy-cells = <0>;
895 interrupt-names = "otg-bvalid", "otg-id",
903 compatible = "rockchip,px30-dsi-dphy";
906 clock-names = "ref", "pclk";
908 reset-names = "apb";
909 #phy-cells = <0>;
910 power-domains = <&power PX30_PD_VO>;
915 compatible = "rockchip,px30-csi-dphy";
918 clock-names = "pclk";
919 #phy-cells = <0>;
920 power-domains = <&power PX30_PD_VI>;
922 reset-names = "apb";
928 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
933 clock-names = "otg";
935 g-np-tx-fifo-size = <16>;
936 g-rx-fifo-size = <280>;
937 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phy-names = "usb2-phy";
940 power-domains = <&power PX30_PD_USB>;
945 compatible = "generic-ehci";
950 phy-names = "usb";
951 power-domains = <&power PX30_PD_USB>;
956 compatible = "generic-ohci";
961 phy-names = "usb";
962 power-domains = <&power PX30_PD_USB>;
967 compatible = "rockchip,px30-gmac";
970 interrupt-names = "macirq";
975 clock-names = "stmmaceth", "mac_clk_rx",
980 phy-mode = "rmii";
981 pinctrl-names = "default";
982 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
983 power-domains = <&power PX30_PD_GMAC>;
985 reset-names = "stmmaceth";
990 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
995 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
996 bus-width = <4>;
997 fifo-depth = <0x100>;
998 max-frequency = <150000000>;
999 pinctrl-names = "default";
1000 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1001 power-domains = <&power PX30_PD_SDCARD>;
1006 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1011 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1012 bus-width = <4>;
1013 fifo-depth = <0x100>;
1014 max-frequency = <150000000>;
1015 pinctrl-names = "default";
1016 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1017 power-domains = <&power PX30_PD_MMC_NAND>;
1022 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1027 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1028 bus-width = <8>;
1029 fifo-depth = <0x100>;
1030 max-frequency = <150000000>;
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1033 power-domains = <&power PX30_PD_MMC_NAND>;
1042 clock-names = "clk_sfc", "hclk_sfc";
1043 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1044 pinctrl-names = "default";
1045 power-domains = <&power PX30_PD_MMC_NAND>;
1049 nfc: nand-controller@ff3b0000 {
1050 compatible = "rockchip,px30-nfc";
1054 clock-names = "ahb", "nfc";
1055 assigned-clocks = <&cru SCLK_NANDC>;
1056 assigned-clock-rates = <150000000>;
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 power-domains = <&power PX30_PD_MMC_NAND>;
1064 gpu_opp_table: opp-table-1 {
1065 compatible = "operating-points-v2";
1067 opp-200000000 {
1068 opp-hz = /bits/ 64 <200000000>;
1069 opp-microvolt = <950000>;
1071 opp-300000000 {
1072 opp-hz = /bits/ 64 <300000000>;
1073 opp-microvolt = <975000>;
1075 opp-400000000 {
1076 opp-hz = /bits/ 64 <400000000>;
1077 opp-microvolt = <1050000>;
1079 opp-480000000 {
1080 opp-hz = /bits/ 64 <480000000>;
1081 opp-microvolt = <1125000>;
1086 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1091 interrupt-names = "job", "mmu", "gpu";
1093 #cooling-cells = <2>;
1094 power-domains = <&power PX30_PD_GPU>;
1095 operating-points-v2 = <&gpu_opp_table>;
1099 vpu: video-codec@ff442000 {
1100 compatible = "rockchip,px30-vpu";
1104 interrupt-names = "vepu", "vdpu";
1106 clock-names = "aclk", "hclk";
1108 power-domains = <&power PX30_PD_VPU>;
1116 clock-names = "aclk", "iface";
1117 #iommu-cells = <0>;
1118 power-domains = <&power PX30_PD_VPU>;
1122 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1126 clock-names = "pclk";
1128 phy-names = "dphy";
1129 power-domains = <&power PX30_PD_VO>;
1131 reset-names = "apb";
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1148 remote-endpoint = <&vopb_out_dsi>;
1153 remote-endpoint = <&vopl_out_dsi>;
1164 compatible = "rockchip,px30-vop-big";
1169 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 reset-names = "axi", "ahb", "dclk";
1173 power-domains = <&power PX30_PD_VO>;
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1182 remote-endpoint = <&dsi_in_vopb>;
1187 remote-endpoint = <&lvds_vopb_in>;
1197 clock-names = "aclk", "iface";
1198 power-domains = <&power PX30_PD_VO>;
1199 #iommu-cells = <0>;
1204 compatible = "rockchip,px30-vop-lit";
1209 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 reset-names = "axi", "ahb", "dclk";
1213 power-domains = <&power PX30_PD_VO>;
1217 #address-cells = <1>;
1218 #size-cells = <0>;
1222 remote-endpoint = <&dsi_in_vopl>;
1227 remote-endpoint = <&lvds_vopl_in>;
1237 clock-names = "aclk", "iface";
1238 power-domains = <&power PX30_PD_VO>;
1239 #iommu-cells = <0>;
1243 isp: isp@ff4a0000 { label
1244 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1249 interrupt-names = "isp", "mi", "mipi";
1254 clock-names = "isp", "aclk", "hclk", "pclk";
1257 phy-names = "dphy";
1258 power-domains = <&power PX30_PD_VI>;
1262 #address-cells = <1>;
1263 #size-cells = <0>;
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1278 clock-names = "aclk", "iface";
1279 power-domains = <&power PX30_PD_VI>;
1280 rockchip,disable-mmu-reset;
1281 #iommu-cells = <0>;
1285 compatible = "rockchip,px30-qos", "syscon";
1290 compatible = "rockchip,px30-qos", "syscon";
1295 compatible = "rockchip,px30-qos", "syscon";
1300 compatible = "rockchip,px30-qos", "syscon";
1305 compatible = "rockchip,px30-qos", "syscon";
1310 compatible = "rockchip,px30-qos", "syscon";
1315 compatible = "rockchip,px30-qos", "syscon";
1320 compatible = "rockchip,px30-qos", "syscon";
1325 compatible = "rockchip,px30-qos", "syscon";
1330 compatible = "rockchip,px30-qos", "syscon";
1335 compatible = "rockchip,px30-qos", "syscon";
1340 compatible = "rockchip,px30-qos", "syscon";
1345 compatible = "rockchip,px30-qos", "syscon";
1350 compatible = "rockchip,px30-qos", "syscon";
1355 compatible = "rockchip,px30-qos", "syscon";
1360 compatible = "rockchip,px30-qos", "syscon";
1365 compatible = "rockchip,px30-qos", "syscon";
1370 compatible = "rockchip,px30-qos", "syscon";
1375 compatible = "rockchip,px30-qos", "syscon";
1380 compatible = "rockchip,px30-qos", "syscon";
1385 compatible = "rockchip,px30-pinctrl";
1388 #address-cells = <2>;
1389 #size-cells = <2>;
1393 compatible = "rockchip,gpio-bank";
1397 gpio-controller;
1398 #gpio-cells = <2>;
1400 interrupt-controller;
1401 #interrupt-cells = <2>;
1405 compatible = "rockchip,gpio-bank";
1409 gpio-controller;
1410 #gpio-cells = <2>;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1417 compatible = "rockchip,gpio-bank";
1421 gpio-controller;
1422 #gpio-cells = <2>;
1424 interrupt-controller;
1425 #interrupt-cells = <2>;
1429 compatible = "rockchip,gpio-bank";
1433 gpio-controller;
1434 #gpio-cells = <2>;
1436 interrupt-controller;
1437 #interrupt-cells = <2>;
1440 pcfg_pull_up: pcfg-pull-up {
1441 bias-pull-up;
1444 pcfg_pull_down: pcfg-pull-down {
1445 bias-pull-down;
1448 pcfg_pull_none: pcfg-pull-none {
1449 bias-disable;
1452 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1453 bias-disable;
1454 drive-strength = <2>;
1457 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1458 bias-pull-up;
1459 drive-strength = <2>;
1462 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1463 bias-pull-up;
1464 drive-strength = <4>;
1467 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1468 bias-disable;
1469 drive-strength = <4>;
1472 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1473 bias-pull-down;
1474 drive-strength = <4>;
1477 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1478 bias-disable;
1479 drive-strength = <8>;
1482 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1483 bias-pull-up;
1484 drive-strength = <8>;
1487 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1488 bias-disable;
1489 drive-strength = <12>;
1492 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1493 bias-pull-up;
1494 drive-strength = <12>;
1497 pcfg_pull_none_smt: pcfg-pull-none-smt {
1498 bias-disable;
1499 input-schmitt-enable;
1502 pcfg_output_high: pcfg-output-high {
1503 output-high;
1506 pcfg_output_low: pcfg-output-low {
1507 output-low;
1510 pcfg_input_high: pcfg-input-high {
1511 bias-pull-up;
1512 input-enable;
1515 pcfg_input: pcfg-input {
1516 input-enable;
1520 i2c0_xfer: i2c0-xfer {
1528 i2c1_xfer: i2c1-xfer {
1536 i2c2_xfer: i2c2-xfer {
1544 i2c3_xfer: i2c3-xfer {
1552 tsadc_otp_pin: tsadc-otp-pin {
1557 tsadc_otp_out: tsadc-otp-out {
1564 uart0_xfer: uart0-xfer {
1570 uart0_cts: uart0-cts {
1575 uart0_rts: uart0-rts {
1582 uart1_xfer: uart1-xfer {
1588 uart1_cts: uart1-cts {
1593 uart1_rts: uart1-rts {
1599 uart2-m0 {
1600 uart2m0_xfer: uart2m0-xfer {
1607 uart2-m1 {
1608 uart2m1_xfer: uart2m1-xfer {
1615 uart3-m0 {
1616 uart3m0_xfer: uart3m0-xfer {
1622 uart3m0_cts: uart3m0-cts {
1627 uart3m0_rts: uart3m0-rts {
1633 uart3-m1 {
1634 uart3m1_xfer: uart3m1-xfer {
1640 uart3m1_cts: uart3m1-cts {
1645 uart3m1_rts: uart3m1-rts {
1652 uart4_xfer: uart4-xfer {
1658 uart4_cts: uart4-cts {
1663 uart4_rts: uart4-rts {
1670 uart5_xfer: uart5-xfer {
1676 uart5_cts: uart5-cts {
1681 uart5_rts: uart5-rts {
1688 spi0_clk: spi0-clk {
1693 spi0_csn: spi0-csn {
1698 spi0_miso: spi0-miso {
1703 spi0_mosi: spi0-mosi {
1708 spi0_clk_hs: spi0-clk-hs {
1713 spi0_miso_hs: spi0-miso-hs {
1718 spi0_mosi_hs: spi0-mosi-hs {
1725 spi1_clk: spi1-clk {
1730 spi1_csn0: spi1-csn0 {
1735 spi1_csn1: spi1-csn1 {
1740 spi1_miso: spi1-miso {
1745 spi1_mosi: spi1-mosi {
1750 spi1_clk_hs: spi1-clk-hs {
1755 spi1_miso_hs: spi1-miso-hs {
1760 spi1_mosi_hs: spi1-mosi-hs {
1767 pdm_clk0m0: pdm-clk0m0 {
1772 pdm_clk0m1: pdm-clk0m1 {
1777 pdm_clk1: pdm-clk1 {
1782 pdm_sdi0m0: pdm-sdi0m0 {
1787 pdm_sdi0m1: pdm-sdi0m1 {
1792 pdm_sdi1: pdm-sdi1 {
1797 pdm_sdi2: pdm-sdi2 {
1802 pdm_sdi3: pdm-sdi3 {
1807 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1812 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1817 pdm_clk1_sleep: pdm-clk1-sleep {
1822 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1827 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1832 pdm_sdi1_sleep: pdm-sdi1-sleep {
1837 pdm_sdi2_sleep: pdm-sdi2-sleep {
1842 pdm_sdi3_sleep: pdm-sdi3-sleep {
1849 i2s0_8ch_mclk: i2s0-8ch-mclk {
1854 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1859 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1864 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1869 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1874 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1879 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1884 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1889 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1894 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1899 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1904 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1909 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1916 i2s1_2ch_mclk: i2s1-2ch-mclk {
1921 i2s1_2ch_sclk: i2s1-2ch-sclk {
1926 i2s1_2ch_lrck: i2s1-2ch-lrck {
1931 i2s1_2ch_sdi: i2s1-2ch-sdi {
1936 i2s1_2ch_sdo: i2s1-2ch-sdo {
1943 i2s2_2ch_mclk: i2s2-2ch-mclk {
1948 i2s2_2ch_sclk: i2s2-2ch-sclk {
1953 i2s2_2ch_lrck: i2s2-2ch-lrck {
1958 i2s2_2ch_sdi: i2s2-2ch-sdi {
1963 i2s2_2ch_sdo: i2s2-2ch-sdo {
1970 sdmmc_clk: sdmmc-clk {
1975 sdmmc_cmd: sdmmc-cmd {
1980 sdmmc_det: sdmmc-det {
1985 sdmmc_bus1: sdmmc-bus1 {
1990 sdmmc_bus4: sdmmc-bus4 {
2000 sdio_clk: sdio-clk {
2005 sdio_cmd: sdio-cmd {
2010 sdio_bus4: sdio-bus4 {
2020 emmc_clk: emmc-clk {
2025 emmc_cmd: emmc-cmd {
2030 emmc_rstnout: emmc-rstnout {
2035 emmc_bus1: emmc-bus1 {
2040 emmc_bus4: emmc-bus4 {
2048 emmc_bus8: emmc-bus8 {
2062 flash_cs0: flash-cs0 {
2067 flash_rdy: flash-rdy {
2072 flash_dqs: flash-dqs {
2077 flash_ale: flash-ale {
2082 flash_cle: flash-cle {
2087 flash_wrn: flash-wrn {
2092 flash_csl: flash-csl {
2097 flash_rdn: flash-rdn {
2102 flash_bus8: flash-bus8 {
2116 sfc_bus4: sfc-bus4 {
2124 sfc_bus2: sfc-bus2 {
2130 sfc_cs0: sfc-cs0 {
2135 sfc_clk: sfc-clk {
2142 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2147 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2152 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2157 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2162 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2190 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2212 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2232 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2253 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2268 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2283 pwm0_pin: pwm0-pin {
2290 pwm1_pin: pwm1-pin {
2297 pwm2_pin: pwm2-pin {
2304 pwm3_pin: pwm3-pin {
2311 pwm4_pin: pwm4-pin {
2318 pwm5_pin: pwm5-pin {
2325 pwm6_pin: pwm6-pin {
2332 pwm7_pin: pwm7-pin {
2339 rmii_pins: rmii-pins {
2352 mac_refclk_12ma: mac-refclk-12ma {
2357 mac_refclk: mac-refclk {
2363 cif-m0 {
2364 cif_clkout_m0: cif-clkout-m0 {
2369 dvp_d2d9_m0: dvp-d2d9-m0 {
2385 dvp_d0d1_m0: dvp-d0d1-m0 {
2391 dvp_d10d11_m0:d10-d11-m0 {
2398 cif-m1 {
2399 cif_clkout_m1: cif-clkout-m1 {
2404 dvp_d2d9_m1: dvp-d2d9-m1 {
2420 dvp_d0d1_m1: dvp-d0d1-m1 {
2426 dvp_d10d11_m1:d10-d11-m1 {
2433 isp {
2434 isp_prelight: isp-prelight {