Lines Matching +full:0 +full:xe6190000
22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
88 clock-frequency = <0>;
102 reg = <0 0xe6020000 0 0x0c>;
113 reg = <0 0xe6050000 0 0x50>;
117 gpio-ranges = <&pfc 0 0 22>;
128 reg = <0 0xe6051000 0 0x50>;
132 gpio-ranges = <&pfc 0 32 28>;
143 reg = <0 0xe6052000 0 0x50>;
147 gpio-ranges = <&pfc 0 64 17>;
158 reg = <0 0xe6053000 0 0x50>;
162 gpio-ranges = <&pfc 0 96 17>;
173 reg = <0 0xe6054000 0 0x50>;
177 gpio-ranges = <&pfc 0 128 6>;
188 reg = <0 0xe6055000 0 0x50>;
192 gpio-ranges = <&pfc 0 160 15>;
202 reg = <0 0xe6060000 0 0x504>;
208 reg = <0 0xe60f0000 0 0x1004>;
221 reg = <0 0xe6130000 0 0x1004>;
240 reg = <0 0xe6140000 0 0x1004>;
259 reg = <0 0xe6148000 0 0x1004>;
277 reg = <0 0xe6150000 0 0x1000>;
281 #power-domain-cells = <0>;
287 reg = <0 0xe6160000 0 0x200>;
292 reg = <0 0xe6180000 0 0x440>;
298 reg = <0 0xe6190000 0 0x10>,
299 <0 0xe6190100 0 0x120>;
306 #thermal-sensor-cells = <0>;
313 reg = <0 0xe61c0000 0 0x200>;
314 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
327 reg = <0 0xe61e0000 0 0x30>;
340 reg = <0 0xe6fc0000 0 0x30>;
353 reg = <0 0xe6fd0000 0 0x30>;
366 reg = <0 0xe6fe0000 0 0x30>;
379 reg = <0 0xffc00000 0 0x30>;
393 reg = <0 0xe6500000 0 0x40>;
398 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
399 <&dmac2 0x91>, <&dmac2 0x90>;
403 #size-cells = <0>;
410 reg = <0 0xe6508000 0 0x40>;
415 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
416 <&dmac2 0x93>, <&dmac2 0x92>;
420 #size-cells = <0>;
427 reg = <0 0xe6510000 0 0x40>;
432 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
433 <&dmac2 0x95>, <&dmac2 0x94>;
437 #size-cells = <0>;
444 reg = <0 0xe66d0000 0 0x40>;
449 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
450 <&dmac2 0x97>, <&dmac2 0x96>;
454 #size-cells = <0>;
461 reg = <0 0xe66d8000 0 0x40>;
466 dmas = <&dmac1 0x99>, <&dmac1 0x98>,
467 <&dmac2 0x99>, <&dmac2 0x98>;
471 #size-cells = <0>;
479 reg = <0 0xe6540000 0 96>;
485 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
486 <&dmac2 0x31>, <&dmac2 0x30>;
497 reg = <0 0xe6550000 0 96>;
503 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
504 <&dmac2 0x33>, <&dmac2 0x32>;
515 reg = <0 0xe6560000 0 96>;
521 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
522 <&dmac2 0x35>, <&dmac2 0x34>;
532 reg = <0 0xe66a0000 0 96>;
538 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
539 <&dmac2 0x37>, <&dmac2 0x36>;
549 reg = <0 0xe66c0000 0 0x8000>;
575 reg = <0 0xe6800000 0 0x800>;
613 rx-internal-delay-ps = <0>;
614 tx-internal-delay-ps = <0>;
617 #size-cells = <0>;
623 reg = <0 0xe6e30000 0 8>;
633 reg = <0 0xe6e31000 0 8>;
643 reg = <0 0xe6e32000 0 8>;
653 reg = <0 0xe6e33000 0 8>;
663 reg = <0 0xe6e34000 0 8>;
675 reg = <0 0xe6e60000 0 64>;
681 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
682 <&dmac2 0x51>, <&dmac2 0x50>;
693 reg = <0 0xe6e68000 0 64>;
699 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
700 <&dmac2 0x53>, <&dmac2 0x52>;
711 reg = <0 0xe6c50000 0 64>;
717 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
718 <&dmac2 0x57>, <&dmac2 0x56>;
728 reg = <0 0xe6c40000 0 64>;
734 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
735 <&dmac2 0x59>, <&dmac2 0x58>;
744 reg = <0 0xe6e80000 0 0x148>;
756 reg = <0 0xe6e90000 0 0x64>;
761 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
762 <&dmac2 0x41>, <&dmac2 0x40>;
765 #size-cells = <0>;
772 reg = <0 0xe6ea0000 0 0x0064>;
777 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
778 <&dmac2 0x43>, <&dmac2 0x42>;
781 #size-cells = <0>;
788 reg = <0 0xe6c00000 0 0x0064>;
793 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
794 <&dmac2 0x45>, <&dmac2 0x44>;
797 #size-cells = <0>;
804 reg = <0 0xe6c10000 0 0x0064>;
809 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
810 <&dmac2 0x47>, <&dmac2 0x46>;
813 #size-cells = <0>;
819 reg = <0 0xe6ef0000 0 0x1000>;
824 renesas,id = <0>;
829 #size-cells = <0>;
833 #size-cells = <0>;
847 reg = <0 0xe6ef1000 0 0x1000>;
857 #size-cells = <0>;
861 #size-cells = <0>;
875 reg = <0 0xe6ef2000 0 0x1000>;
885 #size-cells = <0>;
889 #size-cells = <0>;
903 reg = <0 0xe6ef3000 0 0x1000>;
913 #size-cells = <0>;
917 #size-cells = <0>;
932 reg = <0 0xe7300000 0 0x10000>;
951 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
960 reg = <0 0xe7310000 0 0x10000>;
987 reg = <0 0xe7740000 0 0x1000>;
988 renesas,ipmmu-main = <&ipmmu_mm 0>;
995 reg = <0 0xff8b0000 0 0x1000>;
1003 reg = <0 0xe67b0000 0 0x1000>;
1012 reg = <0 0xffc80000 0 0x1000>;
1020 reg = <0 0xfebd0000 0 0x1000>;
1029 reg = <0 0xee140000 0 0x2000>;
1042 reg = <0 0xee200000 0 0x200>,
1043 <0 0x08000000 0 0x4000000>,
1044 <0 0xee208000 0 0x100>;
1051 #size-cells = <0>;
1058 #address-cells = <0>;
1060 reg = <0 0xf1010000 0 0x1000>,
1061 <0 0xf1020000 0 0x20000>,
1062 <0 0xf1040000 0 0x20000>,
1063 <0 0xf1060000 0 0x20000>;
1074 reg = <0 0xfea20000 0 0x5000>;
1084 reg = <0 0xfea27000 0 0x200>;
1092 reg = <0 0xfeaa0000 0 0x10000>;
1101 #size-cells = <0>;
1103 port@0 {
1104 reg = <0>;
1109 #size-cells = <0>;
1113 csi40vin0: endpoint@0 {
1114 reg = <0>;
1135 reg = <0 0xfeb00000 0 0x80000>;
1138 clock-names = "du.0";
1141 reset-names = "du.0";
1142 renesas,vsps = <&vspd0 0>;
1148 #size-cells = <0>;
1150 port@0 {
1151 reg = <0>;
1165 reg = <0 0xfeb90000 0 0x14>;
1173 #size-cells = <0>;
1175 port@0 {
1176 reg = <0>;
1190 reg = <0 0xfff00044 0 4>;