Lines Matching +full:0 +full:xe61a8000
25 * The external audio clocks are configured as 0 Hz fixed frequency
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
54 cluster0_opp: opp-table-0 {
94 #size-cells = <0>;
96 a57_0: cpu@0 {
98 reg = <0x0>;
112 reg = <0x1>;
122 L2_CA57: cache-controller-0 {
132 CPU_SLEEP_0: cpu-sleep-0 {
134 arm,psci-suspend-param = <0x0010000>;
145 #clock-cells = <0>;
147 clock-frequency = <0>;
152 #clock-cells = <0>;
154 clock-frequency = <0>;
160 #clock-cells = <0>;
161 clock-frequency = <0>;
180 #clock-cells = <0>;
181 clock-frequency = <0>;
194 reg = <0 0xe6020000 0 0x0c>;
205 reg = <0 0xe6050000 0 0x50>;
209 gpio-ranges = <&pfc 0 0 16>;
220 reg = <0 0xe6051000 0 0x50>;
224 gpio-ranges = <&pfc 0 32 29>;
235 reg = <0 0xe6052000 0 0x50>;
239 gpio-ranges = <&pfc 0 64 15>;
250 reg = <0 0xe6053000 0 0x50>;
254 gpio-ranges = <&pfc 0 96 16>;
265 reg = <0 0xe6054000 0 0x50>;
269 gpio-ranges = <&pfc 0 128 18>;
280 reg = <0 0xe6055000 0 0x50>;
284 gpio-ranges = <&pfc 0 160 26>;
295 reg = <0 0xe6055400 0 0x50>;
299 gpio-ranges = <&pfc 0 192 32>;
310 reg = <0 0xe6055800 0 0x50>;
314 gpio-ranges = <&pfc 0 224 4>;
324 reg = <0 0xe6060000 0 0x50c>;
330 reg = <0 0xe60f0000 0 0x1004>;
343 reg = <0 0xe6130000 0 0x1004>;
362 reg = <0 0xe6140000 0 0x1004>;
381 reg = <0 0xe6148000 0 0x1004>;
399 reg = <0 0xe6150000 0 0x1000>;
403 #power-domain-cells = <0>;
409 reg = <0 0xe6160000 0 0x0200>;
414 reg = <0 0xe6180000 0 0x0400>;
420 reg = <0 0xe6198000 0 0x100>,
421 <0 0xe61a0000 0 0x100>,
422 <0 0xe61a8000 0 0x100>;
436 reg = <0 0xe61c0000 0 0x200>;
437 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
450 reg = <0 0xe61e0000 0 0x30>;
463 reg = <0 0xe6fc0000 0 0x30>;
476 reg = <0 0xe6fd0000 0 0x30>;
489 reg = <0 0xe6fe0000 0 0x30>;
502 reg = <0 0xffc00000 0 0x30>;
515 #size-cells = <0>;
518 reg = <0 0xe6500000 0 0x40>;
523 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
524 <&dmac2 0x91>, <&dmac2 0x90>;
532 #size-cells = <0>;
535 reg = <0 0xe6508000 0 0x40>;
540 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
541 <&dmac2 0x93>, <&dmac2 0x92>;
549 #size-cells = <0>;
552 reg = <0 0xe6510000 0 0x40>;
557 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
558 <&dmac2 0x95>, <&dmac2 0x94>;
566 #size-cells = <0>;
569 reg = <0 0xe66d0000 0 0x40>;
574 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
582 #size-cells = <0>;
585 reg = <0 0xe66d8000 0 0x40>;
590 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
598 #size-cells = <0>;
601 reg = <0 0xe66e0000 0 0x40>;
606 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
614 #size-cells = <0>;
617 reg = <0 0xe66e8000 0 0x40>;
622 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
630 #size-cells = <0>;
634 reg = <0 0xe60b0000 0 0x425>;
639 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
648 reg = <0 0xe6540000 0 0x60>;
654 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
655 <&dmac2 0x31>, <&dmac2 0x30>;
666 reg = <0 0xe6550000 0 0x60>;
672 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
673 <&dmac2 0x33>, <&dmac2 0x32>;
684 reg = <0 0xe6560000 0 0x60>;
690 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
691 <&dmac2 0x35>, <&dmac2 0x34>;
702 reg = <0 0xe66a0000 0 0x60>;
708 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
719 reg = <0 0xe66b0000 0 0x60>;
725 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
735 reg = <0 0xe6590000 0 0x200>;
738 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
739 <&usb_dmac1 0>, <&usb_dmac1 1>;
752 reg = <0 0xe65a0000 0 0x100>;
766 reg = <0 0xe65b0000 0 0x100>;
780 reg = <0 0xe65ee000 0 0x90>;
786 #phy-cells = <0>;
793 reg = <0x0 0xe6601000 0 0x1000>;
802 reg = <0 0xe6700000 0 0x10000>;
831 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
844 reg = <0 0xe7300000 0 0x10000>;
873 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
886 reg = <0 0xe7310000 0 0x10000>;
927 reg = <0 0xe6740000 0 0x1000>;
928 renesas,ipmmu-main = <&ipmmu_mm 0>;
935 reg = <0 0xe7740000 0 0x1000>;
943 reg = <0 0xe6570000 0 0x1000>;
951 reg = <0 0xe67b0000 0 0x1000>;
960 reg = <0 0xec670000 0 0x1000>;
968 reg = <0 0xfd800000 0 0x1000>;
976 reg = <0 0xffc80000 0 0x1000>;
984 reg = <0 0xfe6b0000 0 0x1000>;
992 reg = <0 0xfebd0000 0 0x1000>;
1000 reg = <0 0xfe990000 0 0x1000>;
1009 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1047 rx-internal-delay-ps = <0>;
1048 tx-internal-delay-ps = <0>;
1051 #size-cells = <0>;
1058 reg = <0 0xe6c30000 0 0x1000>;
1074 reg = <0 0xe6c38000 0 0x1000>;
1090 reg = <0 0xe66c0000 0 0x8000>;
1115 reg = <0 0xe6e30000 0 8>;
1125 reg = <0 0xe6e31000 0 8>;
1135 reg = <0 0xe6e32000 0 8>;
1145 reg = <0 0xe6e33000 0 8>;
1155 reg = <0 0xe6e34000 0 8>;
1165 reg = <0 0xe6e35000 0 8>;
1175 reg = <0 0xe6e36000 0 8>;
1186 reg = <0 0xe6e60000 0 64>;
1192 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1193 <&dmac2 0x51>, <&dmac2 0x50>;
1203 reg = <0 0xe6e68000 0 64>;
1209 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1210 <&dmac2 0x53>, <&dmac2 0x52>;
1220 reg = <0 0xe6e88000 0 64>;
1226 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1227 <&dmac2 0x13>, <&dmac2 0x12>;
1237 reg = <0 0xe6c50000 0 64>;
1243 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1253 reg = <0 0xe6c40000 0 64>;
1259 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1269 reg = <0 0xe6f30000 0 64>;
1275 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1276 <&dmac2 0x5b>, <&dmac2 0x5a>;
1285 reg = <0 0xe6e80000 0 0x148>;
1297 reg = <0 0xe6e90000 0 0x0064>;
1300 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1301 <&dmac2 0x41>, <&dmac2 0x40>;
1306 #size-cells = <0>;
1313 reg = <0 0xe6ea0000 0 0x0064>;
1316 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1317 <&dmac2 0x43>, <&dmac2 0x42>;
1322 #size-cells = <0>;
1329 reg = <0 0xe6c00000 0 0x0064>;
1332 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1337 #size-cells = <0>;
1344 reg = <0 0xe6c10000 0 0x0064>;
1347 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1352 #size-cells = <0>;
1358 reg = <0 0xe6ef0000 0 0x1000>;
1363 renesas,id = <0>;
1368 #size-cells = <0>;
1372 #size-cells = <0>;
1376 vin0csi20: endpoint@0 {
1377 reg = <0>;
1390 reg = <0 0xe6ef1000 0 0x1000>;
1400 #size-cells = <0>;
1404 #size-cells = <0>;
1408 vin1csi20: endpoint@0 {
1409 reg = <0>;
1422 reg = <0 0xe6ef2000 0 0x1000>;
1432 #size-cells = <0>;
1436 #size-cells = <0>;
1440 vin2csi20: endpoint@0 {
1441 reg = <0>;
1454 reg = <0 0xe6ef3000 0 0x1000>;
1464 #size-cells = <0>;
1468 #size-cells = <0>;
1472 vin3csi20: endpoint@0 {
1473 reg = <0>;
1486 reg = <0 0xe6ef4000 0 0x1000>;
1496 #size-cells = <0>;
1500 #size-cells = <0>;
1504 vin4csi20: endpoint@0 {
1505 reg = <0>;
1518 reg = <0 0xe6ef5000 0 0x1000>;
1528 #size-cells = <0>;
1532 #size-cells = <0>;
1536 vin5csi20: endpoint@0 {
1537 reg = <0>;
1550 reg = <0 0xe6ef6000 0 0x1000>;
1560 #size-cells = <0>;
1564 #size-cells = <0>;
1568 vin6csi20: endpoint@0 {
1569 reg = <0>;
1582 reg = <0 0xe6ef7000 0 0x1000>;
1592 #size-cells = <0>;
1596 #size-cells = <0>;
1600 vin7csi20: endpoint@0 {
1601 reg = <0>;
1615 reg = <0 0xe6f40000 0 0x84>;
1619 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1630 reg = <0 0xe6f50000 0 0x84>;
1634 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1645 reg = <0 0xe6f60000 0 0x84>;
1649 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1660 reg = <0 0xe6f70000 0 0x84>;
1664 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1675 reg = <0 0xe6f80000 0 0x84>;
1679 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1690 reg = <0 0xe6f90000 0 0x84>;
1694 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1705 reg = <0 0xe6fa0000 0 0x84>;
1709 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1720 reg = <0 0xe6fb0000 0 0x84>;
1724 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1736 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1742 * clkout : #clock-cells = <0>; <&rcar_sound>;
1746 reg = <0 0xec500000 0 0x1000>, /* SCU */
1747 <0 0xec5a0000 0 0x100>, /* ADG */
1748 <0 0xec540000 0 0x1000>, /* SSIU */
1749 <0 0xec541000 0 0x280>, /* SSI */
1750 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1773 "ssi.1", "ssi.0",
1776 "src.1", "src.0",
1777 "mix.1", "mix.0",
1778 "ctu.1", "ctu.0",
1779 "dvc.0", "dvc.1",
1791 "ssi.1", "ssi.0";
1795 dvc0: dvc-0 {
1796 dmas = <&audma1 0xbc>;
1800 dmas = <&audma1 0xbe>;
1806 mix0: mix-0 { };
1811 ctu00: ctu-0 { };
1822 src0: src-0 {
1824 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1829 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1834 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1839 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1844 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1849 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1854 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1859 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1864 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1869 dmas = <&audma0 0x97>, <&audma1 0xba>;
1875 ssiu00: ssiu-0 {
1876 dmas = <&audma0 0x15>, <&audma1 0x16>;
1880 dmas = <&audma0 0x35>, <&audma1 0x36>;
1884 dmas = <&audma0 0x37>, <&audma1 0x38>;
1888 dmas = <&audma0 0x47>, <&audma1 0x48>;
1892 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1896 dmas = <&audma0 0x43>, <&audma1 0x44>;
1900 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1904 dmas = <&audma0 0x53>, <&audma1 0x54>;
1908 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1912 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1916 dmas = <&audma0 0x57>, <&audma1 0x58>;
1920 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1924 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1928 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1932 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1936 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1940 dmas = <&audma0 0x63>, <&audma1 0x64>;
1944 dmas = <&audma0 0x67>, <&audma1 0x68>;
1948 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1952 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1956 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1960 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1964 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1968 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1972 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1976 dmas = <&audma0 0x21>, <&audma1 0x22>;
1980 dmas = <&audma0 0x23>, <&audma1 0x24>;
1984 dmas = <&audma0 0x25>, <&audma1 0x26>;
1988 dmas = <&audma0 0x27>, <&audma1 0x28>;
1992 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1996 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2000 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2004 dmas = <&audma0 0x71>, <&audma1 0x72>;
2008 dmas = <&audma0 0x17>, <&audma1 0x18>;
2012 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2016 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2020 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2024 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2028 dmas = <&audma0 0x31>, <&audma1 0x32>;
2032 dmas = <&audma0 0x33>, <&audma1 0x34>;
2036 dmas = <&audma0 0x73>, <&audma1 0x74>;
2040 dmas = <&audma0 0x75>, <&audma1 0x76>;
2044 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2048 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2052 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2056 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2060 dmas = <&audma0 0x81>, <&audma1 0x82>;
2064 dmas = <&audma0 0x83>, <&audma1 0x84>;
2068 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2072 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2076 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2080 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2086 ssi0: ssi-0 {
2088 dmas = <&audma0 0x01>, <&audma1 0x02>;
2093 dmas = <&audma0 0x03>, <&audma1 0x04>;
2098 dmas = <&audma0 0x05>, <&audma1 0x06>;
2103 dmas = <&audma0 0x07>, <&audma1 0x08>;
2108 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2113 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2118 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2123 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2128 dmas = <&audma0 0x11>, <&audma1 0x12>;
2133 dmas = <&audma0 0x13>, <&audma1 0x14>;
2142 reg = <0 0xec520000 0 0x800>;
2154 reg = <0 0xec700000 0 0x10000>;
2188 reg = <0 0xec720000 0 0x10000>;
2222 reg = <0 0xee000000 0 0xc00>;
2233 reg = <0 0xee020000 0 0x400>;
2243 reg = <0 0xee080000 0 0x100>;
2255 reg = <0 0xee0a0000 0 0x100>;
2267 reg = <0 0xee080100 0 0x100>;
2280 reg = <0 0xee0a0100 0 0x100>;
2294 reg = <0 0xee080200 0 0x700>;
2306 reg = <0 0xee0a0200 0 0x700>;
2317 reg = <0 0xee100000 0 0x2000>;
2331 reg = <0 0xee120000 0 0x2000>;
2345 reg = <0 0xee140000 0 0x2000>;
2359 reg = <0 0xee160000 0 0x2000>;
2373 reg = <0 0xee200000 0 0x200>,
2374 <0 0x08000000 0 0x04000000>,
2375 <0 0xee208000 0 0x100>;
2382 #size-cells = <0>;
2389 reg = <0 0xee300000 0 0x200000>;
2400 #address-cells = <0>;
2402 reg = <0x0 0xf1010000 0 0x1000>,
2403 <0x0 0xf1020000 0 0x20000>,
2404 <0x0 0xf1040000 0 0x20000>,
2405 <0x0 0xf1060000 0 0x20000>;
2417 reg = <0 0xfe000000 0 0x80000>;
2420 bus-range = <0x00 0xff>;
2422 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2423 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2424 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2425 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2427 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2432 interrupt-map-mask = <0 0 0 0>;
2433 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2438 iommu-map = <0 &ipmmu_hc 0 1>;
2439 iommu-map-mask = <0>;
2446 reg = <0 0xee800000 0 0x80000>;
2449 bus-range = <0x00 0xff>;
2451 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2452 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2453 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2454 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2456 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2461 interrupt-map-mask = <0 0 0 0>;
2462 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2467 iommu-map = <0 &ipmmu_hc 1 1>;
2468 iommu-map-mask = <0>;
2474 reg = <0 0xfe940000 0 0x2400>;
2484 reg = <0 0xfe950000 0 0x200>;
2492 reg = <0 0xfe960000 0 0x8000>;
2503 reg = <0 0xfe9a0000 0 0x8000>;
2514 reg = <0 0xfea20000 0 0x5000>;
2525 reg = <0 0xfea28000 0 0x5000>;
2536 reg = <0 0xfe96f000 0 0x200>;
2544 reg = <0 0xfea27000 0 0x200>;
2552 reg = <0 0xfea2f000 0 0x200>;
2560 reg = <0 0xfe9af000 0 0x200>;
2569 reg = <0 0xfea40000 0 0x1000>;
2578 reg = <0 0xfea50000 0 0x1000>;
2587 reg = <0 0xfea70000 0 0x1000>;
2595 reg = <0 0xfea80000 0 0x10000>;
2604 #size-cells = <0>;
2606 port@0 {
2607 reg = <0>;
2612 #size-cells = <0>;
2616 csi20vin0: endpoint@0 {
2617 reg = <0>;
2654 reg = <0 0xfeaa0000 0 0x10000>;
2663 #size-cells = <0>;
2665 port@0 {
2666 reg = <0>;
2671 #size-cells = <0>;
2675 csi40vin0: endpoint@0 {
2676 reg = <0>;
2714 reg = <0 0xfead0000 0 0x10000>;
2725 #size-cells = <0>;
2726 port@0 {
2727 reg = <0>;
2740 reg = <0 0xfeb00000 0 0x80000>;
2746 clock-names = "du.0", "du.1", "du.3";
2748 reset-names = "du.0", "du.3";
2751 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;
2757 #size-cells = <0>;
2759 port@0 {
2760 reg = <0>;
2779 reg = <0 0xfeb90000 0 0x14>;
2787 #size-cells = <0>;
2789 port@0 {
2790 reg = <0>;
2803 reg = <0 0xfff00044 0 4>;
2811 thermal-sensors = <&tsc 0>;
2880 #clock-cells = <0>;
2881 clock-frequency = <0>;
2886 #clock-cells = <0>;
2887 clock-frequency = <0>;