Lines Matching +full:0 +full:xe61a8000
20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
49 cluster0_opp: opp-table-0 {
116 #size-cells = <0>;
144 a57_0: cpu@0 {
146 reg = <0x0>;
161 reg = <0x1>;
175 reg = <0x100>;
190 reg = <0x101>;
203 reg = <0x102>;
216 reg = <0x103>;
227 L2_CA57: cache-controller-0 {
244 CPU_SLEEP_0: cpu-sleep-0 {
246 arm,psci-suspend-param = <0x0010000>;
255 arm,psci-suspend-param = <0x0010000>;
266 #clock-cells = <0>;
268 clock-frequency = <0>;
273 #clock-cells = <0>;
275 clock-frequency = <0>;
281 #clock-cells = <0>;
282 clock-frequency = <0>;
309 #clock-cells = <0>;
310 clock-frequency = <0>;
323 reg = <0 0xe6020000 0 0x0c>;
334 reg = <0 0xe6050000 0 0x50>;
338 gpio-ranges = <&pfc 0 0 16>;
349 reg = <0 0xe6051000 0 0x50>;
353 gpio-ranges = <&pfc 0 32 29>;
364 reg = <0 0xe6052000 0 0x50>;
368 gpio-ranges = <&pfc 0 64 15>;
379 reg = <0 0xe6053000 0 0x50>;
383 gpio-ranges = <&pfc 0 96 16>;
394 reg = <0 0xe6054000 0 0x50>;
398 gpio-ranges = <&pfc 0 128 18>;
409 reg = <0 0xe6055000 0 0x50>;
413 gpio-ranges = <&pfc 0 160 26>;
424 reg = <0 0xe6055400 0 0x50>;
428 gpio-ranges = <&pfc 0 192 32>;
439 reg = <0 0xe6055800 0 0x50>;
443 gpio-ranges = <&pfc 0 224 4>;
453 reg = <0 0xe6060000 0 0x50c>;
459 reg = <0 0xe60f0000 0 0x1004>;
472 reg = <0 0xe6130000 0 0x1004>;
491 reg = <0 0xe6140000 0 0x1004>;
510 reg = <0 0xe6148000 0 0x1004>;
528 reg = <0 0xe6150000 0 0x1000>;
532 #power-domain-cells = <0>;
538 reg = <0 0xe6160000 0 0x0200>;
543 reg = <0 0xe6180000 0 0x0400>;
549 reg = <0 0xe6198000 0 0x100>,
550 <0 0xe61a0000 0 0x100>,
551 <0 0xe61a8000 0 0x100>;
565 reg = <0 0xe61c0000 0 0x200>;
566 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
579 reg = <0 0xe61e0000 0 0x30>;
592 reg = <0 0xe6fc0000 0 0x30>;
605 reg = <0 0xe6fd0000 0 0x30>;
618 reg = <0 0xe6fe0000 0 0x30>;
631 reg = <0 0xffc00000 0 0x30>;
644 #size-cells = <0>;
647 reg = <0 0xe6500000 0 0x40>;
652 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
653 <&dmac2 0x91>, <&dmac2 0x90>;
661 #size-cells = <0>;
664 reg = <0 0xe6508000 0 0x40>;
669 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
670 <&dmac2 0x93>, <&dmac2 0x92>;
678 #size-cells = <0>;
681 reg = <0 0xe6510000 0 0x40>;
686 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
687 <&dmac2 0x95>, <&dmac2 0x94>;
695 #size-cells = <0>;
698 reg = <0 0xe66d0000 0 0x40>;
703 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
711 #size-cells = <0>;
714 reg = <0 0xe66d8000 0 0x40>;
719 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
727 #size-cells = <0>;
730 reg = <0 0xe66e0000 0 0x40>;
735 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
743 #size-cells = <0>;
746 reg = <0 0xe66e8000 0 0x40>;
751 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
759 #size-cells = <0>;
763 reg = <0 0xe60b0000 0 0x425>;
768 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
777 reg = <0 0xe6540000 0 0x60>;
783 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
784 <&dmac2 0x31>, <&dmac2 0x30>;
795 reg = <0 0xe6550000 0 0x60>;
801 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
802 <&dmac2 0x33>, <&dmac2 0x32>;
813 reg = <0 0xe6560000 0 0x60>;
819 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
820 <&dmac2 0x35>, <&dmac2 0x34>;
831 reg = <0 0xe66a0000 0 0x60>;
837 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
848 reg = <0 0xe66b0000 0 0x60>;
854 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
864 reg = <0 0xe6590000 0 0x200>;
867 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
868 <&usb_dmac1 0>, <&usb_dmac1 1>;
881 reg = <0 0xe65a0000 0 0x100>;
895 reg = <0 0xe65b0000 0 0x100>;
909 reg = <0 0xe65ee000 0 0x90>;
915 #phy-cells = <0>;
922 reg = <0x0 0xe6601000 0 0x1000>;
931 reg = <0 0xe6700000 0 0x10000>;
960 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
973 reg = <0 0xe7300000 0 0x10000>;
1002 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1015 reg = <0 0xe7310000 0 0x10000>;
1056 reg = <0 0xe6740000 0 0x1000>;
1057 renesas,ipmmu-main = <&ipmmu_mm 0>;
1064 reg = <0 0xe7740000 0 0x1000>;
1072 reg = <0 0xe6570000 0 0x1000>;
1080 reg = <0 0xff8b0000 0 0x1000>;
1088 reg = <0 0xe67b0000 0 0x1000>;
1097 reg = <0 0xec670000 0 0x1000>;
1105 reg = <0 0xfd800000 0 0x1000>;
1113 reg = <0 0xfd950000 0 0x1000>;
1121 reg = <0 0xffc80000 0 0x1000>;
1129 reg = <0 0xfe6b0000 0 0x1000>;
1137 reg = <0 0xfebd0000 0 0x1000>;
1146 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1184 rx-internal-delay-ps = <0>;
1185 tx-internal-delay-ps = <0>;
1188 #size-cells = <0>;
1195 reg = <0 0xe6c30000 0 0x1000>;
1211 reg = <0 0xe6c38000 0 0x1000>;
1227 reg = <0 0xe66c0000 0 0x8000>;
1252 reg = <0 0xe6e30000 0 8>;
1262 reg = <0 0xe6e31000 0 8>;
1272 reg = <0 0xe6e32000 0 8>;
1282 reg = <0 0xe6e33000 0 8>;
1292 reg = <0 0xe6e34000 0 8>;
1302 reg = <0 0xe6e35000 0 8>;
1312 reg = <0 0xe6e36000 0 8>;
1323 reg = <0 0xe6e60000 0 64>;
1329 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1330 <&dmac2 0x51>, <&dmac2 0x50>;
1340 reg = <0 0xe6e68000 0 64>;
1346 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1347 <&dmac2 0x53>, <&dmac2 0x52>;
1357 reg = <0 0xe6e88000 0 64>;
1363 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1364 <&dmac2 0x13>, <&dmac2 0x12>;
1374 reg = <0 0xe6c50000 0 64>;
1380 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1390 reg = <0 0xe6c40000 0 64>;
1396 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1406 reg = <0 0xe6f30000 0 64>;
1412 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1413 <&dmac2 0x5b>, <&dmac2 0x5a>;
1422 reg = <0 0xe6e80000 0 0x148>;
1434 reg = <0 0xe6e90000 0 0x0064>;
1437 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1438 <&dmac2 0x41>, <&dmac2 0x40>;
1443 #size-cells = <0>;
1450 reg = <0 0xe6ea0000 0 0x0064>;
1453 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1454 <&dmac2 0x43>, <&dmac2 0x42>;
1459 #size-cells = <0>;
1466 reg = <0 0xe6c00000 0 0x0064>;
1469 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1474 #size-cells = <0>;
1481 reg = <0 0xe6c10000 0 0x0064>;
1484 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1489 #size-cells = <0>;
1495 reg = <0 0xe6ef0000 0 0x1000>;
1500 renesas,id = <0>;
1505 #size-cells = <0>;
1509 #size-cells = <0>;
1513 vin0csi20: endpoint@0 {
1514 reg = <0>;
1527 reg = <0 0xe6ef1000 0 0x1000>;
1537 #size-cells = <0>;
1541 #size-cells = <0>;
1545 vin1csi20: endpoint@0 {
1546 reg = <0>;
1559 reg = <0 0xe6ef2000 0 0x1000>;
1569 #size-cells = <0>;
1573 #size-cells = <0>;
1577 vin2csi20: endpoint@0 {
1578 reg = <0>;
1591 reg = <0 0xe6ef3000 0 0x1000>;
1601 #size-cells = <0>;
1605 #size-cells = <0>;
1609 vin3csi20: endpoint@0 {
1610 reg = <0>;
1623 reg = <0 0xe6ef4000 0 0x1000>;
1633 #size-cells = <0>;
1637 #size-cells = <0>;
1641 vin4csi20: endpoint@0 {
1642 reg = <0>;
1655 reg = <0 0xe6ef5000 0 0x1000>;
1665 #size-cells = <0>;
1669 #size-cells = <0>;
1673 vin5csi20: endpoint@0 {
1674 reg = <0>;
1687 reg = <0 0xe6ef6000 0 0x1000>;
1697 #size-cells = <0>;
1701 #size-cells = <0>;
1705 vin6csi20: endpoint@0 {
1706 reg = <0>;
1719 reg = <0 0xe6ef7000 0 0x1000>;
1729 #size-cells = <0>;
1733 #size-cells = <0>;
1737 vin7csi20: endpoint@0 {
1738 reg = <0>;
1753 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1759 * clkout : #clock-cells = <0>; <&rcar_sound>;
1763 reg = <0 0xec500000 0 0x1000>, /* SCU */
1764 <0 0xec5a0000 0 0x100>, /* ADG */
1765 <0 0xec540000 0 0x1000>, /* SSIU */
1766 <0 0xec541000 0 0x280>, /* SSI */
1767 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1790 "ssi.1", "ssi.0",
1793 "src.1", "src.0",
1794 "mix.1", "mix.0",
1795 "ctu.1", "ctu.0",
1796 "dvc.0", "dvc.1",
1808 "ssi.1", "ssi.0";
1812 ctu00: ctu-0 { };
1823 dvc0: dvc-0 {
1824 dmas = <&audma1 0xbc>;
1828 dmas = <&audma1 0xbe>;
1834 mix0: mix-0 { };
1839 src0: src-0 {
1841 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1846 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1851 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1856 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1861 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1866 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1871 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1876 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1881 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1886 dmas = <&audma0 0x97>, <&audma1 0xba>;
1892 ssi0: ssi-0 {
1894 dmas = <&audma0 0x01>, <&audma1 0x02>;
1899 dmas = <&audma0 0x03>, <&audma1 0x04>;
1904 dmas = <&audma0 0x05>, <&audma1 0x06>;
1909 dmas = <&audma0 0x07>, <&audma1 0x08>;
1914 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1919 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1924 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1929 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1934 dmas = <&audma0 0x11>, <&audma1 0x12>;
1939 dmas = <&audma0 0x13>, <&audma1 0x14>;
1945 ssiu00: ssiu-0 {
1946 dmas = <&audma0 0x15>, <&audma1 0x16>;
1950 dmas = <&audma0 0x35>, <&audma1 0x36>;
1954 dmas = <&audma0 0x37>, <&audma1 0x38>;
1958 dmas = <&audma0 0x47>, <&audma1 0x48>;
1962 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1966 dmas = <&audma0 0x43>, <&audma1 0x44>;
1970 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1974 dmas = <&audma0 0x53>, <&audma1 0x54>;
1978 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1982 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1986 dmas = <&audma0 0x57>, <&audma1 0x58>;
1990 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1994 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1998 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2002 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2006 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2010 dmas = <&audma0 0x63>, <&audma1 0x64>;
2014 dmas = <&audma0 0x67>, <&audma1 0x68>;
2018 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2022 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2026 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2030 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2034 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2038 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2042 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2046 dmas = <&audma0 0x21>, <&audma1 0x22>;
2050 dmas = <&audma0 0x23>, <&audma1 0x24>;
2054 dmas = <&audma0 0x25>, <&audma1 0x26>;
2058 dmas = <&audma0 0x27>, <&audma1 0x28>;
2062 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2066 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2070 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2074 dmas = <&audma0 0x71>, <&audma1 0x72>;
2078 dmas = <&audma0 0x17>, <&audma1 0x18>;
2082 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2086 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2090 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2094 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2098 dmas = <&audma0 0x31>, <&audma1 0x32>;
2102 dmas = <&audma0 0x33>, <&audma1 0x34>;
2106 dmas = <&audma0 0x73>, <&audma1 0x74>;
2110 dmas = <&audma0 0x75>, <&audma1 0x76>;
2114 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2118 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2122 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2126 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2130 dmas = <&audma0 0x81>, <&audma1 0x82>;
2134 dmas = <&audma0 0x83>, <&audma1 0x84>;
2138 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2142 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2146 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2150 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2159 reg = <0 0xec520000 0 0x800>;
2171 reg = <0 0xec700000 0 0x10000>;
2200 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2213 reg = <0 0xec720000 0 0x10000>;
2255 reg = <0 0xee000000 0 0xc00>;
2266 reg = <0 0xee020000 0 0x400>;
2276 reg = <0 0xee080000 0 0x100>;
2288 reg = <0 0xee0a0000 0 0x100>;
2300 reg = <0 0xee080100 0 0x100>;
2313 reg = <0 0xee0a0100 0 0x100>;
2327 reg = <0 0xee080200 0 0x700>;
2339 reg = <0 0xee0a0200 0 0x700>;
2350 reg = <0 0xee100000 0 0x2000>;
2364 reg = <0 0xee120000 0 0x2000>;
2378 reg = <0 0xee140000 0 0x2000>;
2392 reg = <0 0xee160000 0 0x2000>;
2406 reg = <0 0xee200000 0 0x200>,
2407 <0 0x08000000 0 0x04000000>,
2408 <0 0xee208000 0 0x100>;
2415 #size-cells = <0>;
2422 #address-cells = <0>;
2424 reg = <0x0 0xf1010000 0 0x1000>,
2425 <0x0 0xf1020000 0 0x20000>,
2426 <0x0 0xf1040000 0 0x20000>,
2427 <0x0 0xf1060000 0 0x20000>;
2439 reg = <0 0xfe000000 0 0x80000>;
2442 bus-range = <0x00 0xff>;
2444 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2445 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2446 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2447 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2449 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2454 interrupt-map-mask = <0 0 0 0>;
2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2460 iommu-map = <0 &ipmmu_hc 0 1>;
2461 iommu-map-mask = <0>;
2468 reg = <0 0xee800000 0 0x80000>;
2471 bus-range = <0x00 0xff>;
2473 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2474 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2475 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2476 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2478 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2483 interrupt-map-mask = <0 0 0 0>;
2484 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2489 iommu-map = <0 &ipmmu_hc 1 1>;
2490 iommu-map-mask = <0>;
2496 reg = <0 0xfe950000 0 0x200>;
2504 reg = <0 0xfe96f000 0 0x200>;
2512 reg = <0 0xfe9af000 0 0x200>;
2521 reg = <0 0xfea27000 0 0x200>;
2530 reg = <0 0xfea2f000 0 0x200>;
2539 reg = <0 0xfea37000 0 0x200>;
2548 reg = <0 0xfe960000 0 0x8000>;
2559 reg = <0 0xfea20000 0 0x5000>;
2570 reg = <0 0xfea28000 0 0x5000>;
2581 reg = <0 0xfea30000 0 0x5000>;
2592 reg = <0 0xfe9a0000 0 0x8000>;
2603 reg = <0 0xfea80000 0 0x10000>;
2612 #size-cells = <0>;
2614 port@0 {
2615 reg = <0>;
2620 #size-cells = <0>;
2624 csi20vin0: endpoint@0 {
2625 reg = <0>;
2662 reg = <0 0xfeaa0000 0 0x10000>;
2671 #size-cells = <0>;
2673 port@0 {
2674 reg = <0>;
2679 #size-cells = <0>;
2683 csi40vin0: endpoint@0 {
2684 reg = <0>;
2722 reg = <0 0xfead0000 0 0x10000>;
2732 #size-cells = <0>;
2733 port@0 {
2734 reg = <0>;
2751 reg = <0 0xfeb00000 0 0x70000>;
2757 clock-names = "du.0", "du.1", "du.2";
2759 reset-names = "du.0", "du.2";
2761 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2766 #size-cells = <0>;
2768 port@0 {
2769 reg = <0>;
2788 reg = <0 0xfeb90000 0 0x14>;
2796 #size-cells = <0>;
2798 port@0 {
2799 reg = <0>;
2812 reg = <0 0xfff00044 0 4>;
2820 thermal-sensors = <&tsc 0>;
2861 cooling-device = <&a53_0 0 2>;
2892 #clock-cells = <0>;
2893 clock-frequency = <0>;
2898 #clock-cells = <0>;
2899 clock-frequency = <0>;