Lines Matching +full:0 +full:xe6198000
20 * The external audio clocks are configured as 0 Hz fixed frequency
26 #clock-cells = <0>;
27 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
49 cluster0_opp: opp-table-0 {
116 #size-cells = <0>;
144 a57_0: cpu@0 {
146 reg = <0x0>;
161 reg = <0x1>;
175 reg = <0x100>;
190 reg = <0x101>;
203 reg = <0x102>;
216 reg = <0x103>;
227 L2_CA57: cache-controller-0 {
244 CPU_SLEEP_0: cpu-sleep-0 {
246 arm,psci-suspend-param = <0x0010000>;
255 arm,psci-suspend-param = <0x0010000>;
266 #clock-cells = <0>;
268 clock-frequency = <0>;
273 #clock-cells = <0>;
275 clock-frequency = <0>;
281 #clock-cells = <0>;
282 clock-frequency = <0>;
309 #clock-cells = <0>;
310 clock-frequency = <0>;
323 reg = <0 0xe6020000 0 0x0c>;
334 reg = <0 0xe6050000 0 0x50>;
338 gpio-ranges = <&pfc 0 0 16>;
349 reg = <0 0xe6051000 0 0x50>;
353 gpio-ranges = <&pfc 0 32 29>;
364 reg = <0 0xe6052000 0 0x50>;
368 gpio-ranges = <&pfc 0 64 15>;
379 reg = <0 0xe6053000 0 0x50>;
383 gpio-ranges = <&pfc 0 96 16>;
394 reg = <0 0xe6054000 0 0x50>;
398 gpio-ranges = <&pfc 0 128 18>;
409 reg = <0 0xe6055000 0 0x50>;
413 gpio-ranges = <&pfc 0 160 26>;
424 reg = <0 0xe6055400 0 0x50>;
428 gpio-ranges = <&pfc 0 192 32>;
439 reg = <0 0xe6055800 0 0x50>;
443 gpio-ranges = <&pfc 0 224 4>;
453 reg = <0 0xe6060000 0 0x50c>;
459 reg = <0 0xe60f0000 0 0x1004>;
472 reg = <0 0xe6130000 0 0x1004>;
491 reg = <0 0xe6140000 0 0x1004>;
510 reg = <0 0xe6148000 0 0x1004>;
528 reg = <0 0xe6150000 0 0x1000>;
532 #power-domain-cells = <0>;
538 reg = <0 0xe6160000 0 0x0200>;
543 reg = <0 0xe6180000 0 0x0400>;
549 reg = <0 0xe6198000 0 0x100>,
550 <0 0xe61a0000 0 0x100>,
551 <0 0xe61a8000 0 0x100>;
565 reg = <0 0xe61c0000 0 0x200>;
566 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
579 reg = <0 0xe61e0000 0 0x30>;
592 reg = <0 0xe6fc0000 0 0x30>;
605 reg = <0 0xe6fd0000 0 0x30>;
618 reg = <0 0xe6fe0000 0 0x30>;
631 reg = <0 0xffc00000 0 0x30>;
644 #size-cells = <0>;
647 reg = <0 0xe6500000 0 0x40>;
652 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
653 <&dmac2 0x91>, <&dmac2 0x90>;
661 #size-cells = <0>;
664 reg = <0 0xe6508000 0 0x40>;
669 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
670 <&dmac2 0x93>, <&dmac2 0x92>;
678 #size-cells = <0>;
681 reg = <0 0xe6510000 0 0x40>;
686 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
687 <&dmac2 0x95>, <&dmac2 0x94>;
695 #size-cells = <0>;
698 reg = <0 0xe66d0000 0 0x40>;
703 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
711 #size-cells = <0>;
714 reg = <0 0xe66d8000 0 0x40>;
719 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
727 #size-cells = <0>;
730 reg = <0 0xe66e0000 0 0x40>;
735 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
743 #size-cells = <0>;
746 reg = <0 0xe66e8000 0 0x40>;
751 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
759 #size-cells = <0>;
763 reg = <0 0xe60b0000 0 0x425>;
768 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
777 reg = <0 0xe6540000 0 0x60>;
783 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
784 <&dmac2 0x31>, <&dmac2 0x30>;
795 reg = <0 0xe6550000 0 0x60>;
801 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
802 <&dmac2 0x33>, <&dmac2 0x32>;
813 reg = <0 0xe6560000 0 0x60>;
819 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
820 <&dmac2 0x35>, <&dmac2 0x34>;
831 reg = <0 0xe66a0000 0 0x60>;
837 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
848 reg = <0 0xe66b0000 0 0x60>;
854 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
864 reg = <0 0xe6590000 0 0x200>;
867 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
868 <&usb_dmac1 0>, <&usb_dmac1 1>;
881 reg = <0 0xe65a0000 0 0x100>;
895 reg = <0 0xe65b0000 0 0x100>;
909 reg = <0 0xe65ee000 0 0x90>;
915 #phy-cells = <0>;
922 reg = <0x0 0xe6601000 0 0x1000>;
931 reg = <0 0xe6700000 0 0x10000>;
960 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
973 reg = <0 0xe7300000 0 0x10000>;
1002 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
1015 reg = <0 0xe7310000 0 0x10000>;
1056 reg = <0 0xe6740000 0 0x1000>;
1057 renesas,ipmmu-main = <&ipmmu_mm 0>;
1064 reg = <0 0xe7740000 0 0x1000>;
1072 reg = <0 0xe6570000 0 0x1000>;
1080 reg = <0 0xff8b0000 0 0x1000>;
1088 reg = <0 0xe67b0000 0 0x1000>;
1097 reg = <0 0xec670000 0 0x1000>;
1105 reg = <0 0xfd800000 0 0x1000>;
1113 reg = <0 0xfd950000 0 0x1000>;
1121 reg = <0 0xffc80000 0 0x1000>;
1129 reg = <0 0xfe6b0000 0 0x1000>;
1137 reg = <0 0xfebd0000 0 0x1000>;
1146 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
1184 rx-internal-delay-ps = <0>;
1185 tx-internal-delay-ps = <0>;
1188 #size-cells = <0>;
1195 reg = <0 0xe6c30000 0 0x1000>;
1211 reg = <0 0xe6c38000 0 0x1000>;
1227 reg = <0 0xe66c0000 0 0x8000>;
1252 reg = <0 0xe6e30000 0 8>;
1262 reg = <0 0xe6e31000 0 8>;
1272 reg = <0 0xe6e32000 0 8>;
1282 reg = <0 0xe6e33000 0 8>;
1292 reg = <0 0xe6e34000 0 8>;
1302 reg = <0 0xe6e35000 0 8>;
1312 reg = <0 0xe6e36000 0 8>;
1323 reg = <0 0xe6e60000 0 64>;
1329 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1330 <&dmac2 0x51>, <&dmac2 0x50>;
1340 reg = <0 0xe6e68000 0 64>;
1346 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1347 <&dmac2 0x53>, <&dmac2 0x52>;
1357 reg = <0 0xe6e88000 0 64>;
1363 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1364 <&dmac2 0x13>, <&dmac2 0x12>;
1374 reg = <0 0xe6c50000 0 64>;
1380 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1390 reg = <0 0xe6c40000 0 64>;
1396 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1406 reg = <0 0xe6f30000 0 64>;
1412 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1413 <&dmac2 0x5b>, <&dmac2 0x5a>;
1422 reg = <0 0xe6e80000 0 0x148>;
1434 reg = <0 0xe6e90000 0 0x0064>;
1437 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1438 <&dmac2 0x41>, <&dmac2 0x40>;
1443 #size-cells = <0>;
1450 reg = <0 0xe6ea0000 0 0x0064>;
1453 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1454 <&dmac2 0x43>, <&dmac2 0x42>;
1459 #size-cells = <0>;
1466 reg = <0 0xe6c00000 0 0x0064>;
1469 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1474 #size-cells = <0>;
1481 reg = <0 0xe6c10000 0 0x0064>;
1484 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1489 #size-cells = <0>;
1495 reg = <0 0xe6ef0000 0 0x1000>;
1500 renesas,id = <0>;
1505 #size-cells = <0>;
1509 #size-cells = <0>;
1513 vin0csi20: endpoint@0 {
1514 reg = <0>;
1527 reg = <0 0xe6ef1000 0 0x1000>;
1537 #size-cells = <0>;
1541 #size-cells = <0>;
1545 vin1csi20: endpoint@0 {
1546 reg = <0>;
1559 reg = <0 0xe6ef2000 0 0x1000>;
1569 #size-cells = <0>;
1573 #size-cells = <0>;
1577 vin2csi20: endpoint@0 {
1578 reg = <0>;
1591 reg = <0 0xe6ef3000 0 0x1000>;
1601 #size-cells = <0>;
1605 #size-cells = <0>;
1609 vin3csi20: endpoint@0 {
1610 reg = <0>;
1623 reg = <0 0xe6ef4000 0 0x1000>;
1633 #size-cells = <0>;
1637 #size-cells = <0>;
1641 vin4csi20: endpoint@0 {
1642 reg = <0>;
1655 reg = <0 0xe6ef5000 0 0x1000>;
1665 #size-cells = <0>;
1669 #size-cells = <0>;
1673 vin5csi20: endpoint@0 {
1674 reg = <0>;
1687 reg = <0 0xe6ef6000 0 0x1000>;
1697 #size-cells = <0>;
1701 #size-cells = <0>;
1705 vin6csi20: endpoint@0 {
1706 reg = <0>;
1719 reg = <0 0xe6ef7000 0 0x1000>;
1729 #size-cells = <0>;
1733 #size-cells = <0>;
1737 vin7csi20: endpoint@0 {
1738 reg = <0>;
1752 reg = <0 0xe6f40000 0 0x64>;
1756 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1767 reg = <0 0xe6f50000 0 0x64>;
1771 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1782 reg = <0 0xe6f60000 0 0x64>;
1786 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1797 reg = <0 0xe6f70000 0 0x64>;
1801 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1812 reg = <0 0xe6f80000 0 0x64>;
1816 dmas = <&dmac1 0x28>, <&dmac2 0x28>;
1827 reg = <0 0xe6f90000 0 0x64>;
1831 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
1842 reg = <0 0xe6fa0000 0 0x64>;
1846 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
1857 reg = <0 0xe6fb0000 0 0x64>;
1861 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
1873 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1879 * clkout : #clock-cells = <0>; <&rcar_sound>;
1883 reg = <0 0xec500000 0 0x1000>, /* SCU */
1884 <0 0xec5a0000 0 0x100>, /* ADG */
1885 <0 0xec540000 0 0x1000>, /* SSIU */
1886 <0 0xec541000 0 0x280>, /* SSI */
1887 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1910 "ssi.1", "ssi.0",
1913 "src.1", "src.0",
1914 "mix.1", "mix.0",
1915 "ctu.1", "ctu.0",
1916 "dvc.0", "dvc.1",
1928 "ssi.1", "ssi.0";
1932 ctu00: ctu-0 { };
1943 dvc0: dvc-0 {
1944 dmas = <&audma1 0xbc>;
1948 dmas = <&audma1 0xbe>;
1954 mix0: mix-0 { };
1959 src0: src-0 {
1961 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1966 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1971 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1976 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1981 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1986 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1991 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1996 dmas = <&audma0 0x93>, <&audma1 0xb6>;
2001 dmas = <&audma0 0x95>, <&audma1 0xb8>;
2006 dmas = <&audma0 0x97>, <&audma1 0xba>;
2012 ssi0: ssi-0 {
2014 dmas = <&audma0 0x01>, <&audma1 0x02>;
2019 dmas = <&audma0 0x03>, <&audma1 0x04>;
2024 dmas = <&audma0 0x05>, <&audma1 0x06>;
2029 dmas = <&audma0 0x07>, <&audma1 0x08>;
2034 dmas = <&audma0 0x09>, <&audma1 0x0a>;
2039 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
2044 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
2049 dmas = <&audma0 0x0f>, <&audma1 0x10>;
2054 dmas = <&audma0 0x11>, <&audma1 0x12>;
2059 dmas = <&audma0 0x13>, <&audma1 0x14>;
2065 ssiu00: ssiu-0 {
2066 dmas = <&audma0 0x15>, <&audma1 0x16>;
2070 dmas = <&audma0 0x35>, <&audma1 0x36>;
2074 dmas = <&audma0 0x37>, <&audma1 0x38>;
2078 dmas = <&audma0 0x47>, <&audma1 0x48>;
2082 dmas = <&audma0 0x3F>, <&audma1 0x40>;
2086 dmas = <&audma0 0x43>, <&audma1 0x44>;
2090 dmas = <&audma0 0x4F>, <&audma1 0x50>;
2094 dmas = <&audma0 0x53>, <&audma1 0x54>;
2098 dmas = <&audma0 0x49>, <&audma1 0x4a>;
2102 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
2106 dmas = <&audma0 0x57>, <&audma1 0x58>;
2110 dmas = <&audma0 0x59>, <&audma1 0x5A>;
2114 dmas = <&audma0 0x5F>, <&audma1 0x60>;
2118 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
2122 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
2126 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
2130 dmas = <&audma0 0x63>, <&audma1 0x64>;
2134 dmas = <&audma0 0x67>, <&audma1 0x68>;
2138 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
2142 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
2146 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
2150 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
2154 dmas = <&audma0 0xED>, <&audma1 0xEE>;
2158 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
2162 dmas = <&audma0 0x6f>, <&audma1 0x70>;
2166 dmas = <&audma0 0x21>, <&audma1 0x22>;
2170 dmas = <&audma0 0x23>, <&audma1 0x24>;
2174 dmas = <&audma0 0x25>, <&audma1 0x26>;
2178 dmas = <&audma0 0x27>, <&audma1 0x28>;
2182 dmas = <&audma0 0x29>, <&audma1 0x2A>;
2186 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2190 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2194 dmas = <&audma0 0x71>, <&audma1 0x72>;
2198 dmas = <&audma0 0x17>, <&audma1 0x18>;
2202 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2206 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2210 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2214 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2218 dmas = <&audma0 0x31>, <&audma1 0x32>;
2222 dmas = <&audma0 0x33>, <&audma1 0x34>;
2226 dmas = <&audma0 0x73>, <&audma1 0x74>;
2230 dmas = <&audma0 0x75>, <&audma1 0x76>;
2234 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2238 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2242 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2246 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2250 dmas = <&audma0 0x81>, <&audma1 0x82>;
2254 dmas = <&audma0 0x83>, <&audma1 0x84>;
2258 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2262 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2266 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2270 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2279 reg = <0 0xec520000 0 0x800>;
2291 reg = <0 0xec700000 0 0x10000>;
2320 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2333 reg = <0 0xec720000 0 0x10000>;
2375 reg = <0 0xee000000 0 0xc00>;
2386 reg = <0 0xee020000 0 0x400>;
2396 reg = <0 0xee080000 0 0x100>;
2408 reg = <0 0xee0a0000 0 0x100>;
2420 reg = <0 0xee080100 0 0x100>;
2433 reg = <0 0xee0a0100 0 0x100>;
2447 reg = <0 0xee080200 0 0x700>;
2459 reg = <0 0xee0a0200 0 0x700>;
2470 reg = <0 0xee100000 0 0x2000>;
2484 reg = <0 0xee120000 0 0x2000>;
2498 reg = <0 0xee140000 0 0x2000>;
2512 reg = <0 0xee160000 0 0x2000>;
2526 reg = <0 0xee200000 0 0x200>,
2527 <0 0x08000000 0 0x04000000>,
2528 <0 0xee208000 0 0x100>;
2535 #size-cells = <0>;
2542 #address-cells = <0>;
2544 reg = <0x0 0xf1010000 0 0x1000>,
2545 <0x0 0xf1020000 0 0x20000>,
2546 <0x0 0xf1040000 0 0x20000>,
2547 <0x0 0xf1060000 0 0x20000>;
2559 reg = <0 0xfe000000 0 0x80000>;
2562 bus-range = <0x00 0xff>;
2564 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2565 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2566 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2567 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2569 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2574 interrupt-map-mask = <0 0 0 0>;
2575 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2580 iommu-map = <0 &ipmmu_hc 0 1>;
2581 iommu-map-mask = <0>;
2588 reg = <0 0xee800000 0 0x80000>;
2591 bus-range = <0x00 0xff>;
2593 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2594 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2595 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2596 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2598 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2603 interrupt-map-mask = <0 0 0 0>;
2604 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2609 iommu-map = <0 &ipmmu_hc 1 1>;
2610 iommu-map-mask = <0>;
2617 reg = <0 0xfe860000 0 0x2000>;
2627 reg = <0 0xfe870000 0 0x2000>;
2636 reg = <0 0xfe940000 0 0x2400>;
2646 reg = <0 0xfe950000 0 0x200>;
2654 reg = <0 0xfe96f000 0 0x200>;
2662 reg = <0 0xfe9af000 0 0x200>;
2671 reg = <0 0xfea27000 0 0x200>;
2680 reg = <0 0xfea2f000 0 0x200>;
2689 reg = <0 0xfea37000 0 0x200>;
2698 reg = <0 0xfe960000 0 0x8000>;
2709 reg = <0 0xfea20000 0 0x5000>;
2720 reg = <0 0xfea28000 0 0x5000>;
2731 reg = <0 0xfea30000 0 0x5000>;
2742 reg = <0 0xfe9a0000 0 0x8000>;
2754 reg = <0 0xfea40000 0 0x1000>;
2763 reg = <0 0xfea50000 0 0x1000>;
2772 reg = <0 0xfea60000 0 0x1000>;
2780 reg = <0 0xfea80000 0 0x10000>;
2789 #size-cells = <0>;
2791 port@0 {
2792 reg = <0>;
2797 #size-cells = <0>;
2801 csi20vin0: endpoint@0 {
2802 reg = <0>;
2839 reg = <0 0xfeaa0000 0 0x10000>;
2848 #size-cells = <0>;
2850 port@0 {
2851 reg = <0>;
2856 #size-cells = <0>;
2860 csi40vin0: endpoint@0 {
2861 reg = <0>;
2899 reg = <0 0xfead0000 0 0x10000>;
2909 #size-cells = <0>;
2910 port@0 {
2911 reg = <0>;
2928 reg = <0 0xfeb00000 0 0x70000>;
2934 clock-names = "du.0", "du.1", "du.2";
2936 reset-names = "du.0", "du.2";
2939 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2945 #size-cells = <0>;
2947 port@0 {
2948 reg = <0>;
2967 reg = <0 0xfeb90000 0 0x14>;
2975 #size-cells = <0>;
2977 port@0 {
2978 reg = <0>;
2991 reg = <0 0xfff00044 0 4>;
2999 thermal-sensors = <&tsc 0>;
3040 cooling-device = <&a53_0 0 2>;
3071 #clock-cells = <0>;
3072 clock-frequency = <0>;
3077 #clock-cells = <0>;
3078 clock-frequency = <0>;