Lines Matching +full:0 +full:xe6198000
21 * The external audio clocks are configured as 0 Hz fixed frequency
27 #clock-cells = <0>;
28 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
39 #clock-cells = <0>;
40 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
50 cluster0_opp: opp-table-0 {
95 #size-cells = <0>;
123 a57_0: cpu@0 {
125 reg = <0x0>;
139 reg = <0x1>;
152 reg = <0x100>;
166 reg = <0x101>;
178 reg = <0x102>;
190 reg = <0x103>;
200 L2_CA57: cache-controller-0 {
217 #clock-cells = <0>;
219 clock-frequency = <0>;
224 #clock-cells = <0>;
226 clock-frequency = <0>;
232 #clock-cells = <0>;
233 clock-frequency = <0>;
260 #clock-cells = <0>;
261 clock-frequency = <0>;
274 reg = <0 0xe6020000 0 0x0c>;
285 reg = <0 0xe6050000 0 0x50>;
289 gpio-ranges = <&pfc 0 0 16>;
300 reg = <0 0xe6051000 0 0x50>;
304 gpio-ranges = <&pfc 0 32 29>;
315 reg = <0 0xe6052000 0 0x50>;
319 gpio-ranges = <&pfc 0 64 15>;
330 reg = <0 0xe6053000 0 0x50>;
334 gpio-ranges = <&pfc 0 96 16>;
345 reg = <0 0xe6054000 0 0x50>;
349 gpio-ranges = <&pfc 0 128 18>;
360 reg = <0 0xe6055000 0 0x50>;
364 gpio-ranges = <&pfc 0 160 26>;
375 reg = <0 0xe6055400 0 0x50>;
379 gpio-ranges = <&pfc 0 192 32>;
390 reg = <0 0xe6055800 0 0x50>;
394 gpio-ranges = <&pfc 0 224 4>;
404 reg = <0 0xe6060000 0 0x50c>;
410 reg = <0 0xe60f0000 0 0x1004>;
423 reg = <0 0xe6130000 0 0x1004>;
442 reg = <0 0xe6140000 0 0x1004>;
461 reg = <0 0xe6148000 0 0x1004>;
479 reg = <0 0xe6150000 0 0x0bb0>;
483 #power-domain-cells = <0>;
489 reg = <0 0xe6160000 0 0x018c>;
494 reg = <0 0xe6180000 0 0x0400>;
500 reg = <0 0xe6198000 0 0x100>,
501 <0 0xe61a0000 0 0x100>,
502 <0 0xe61a8000 0 0x100>;
516 reg = <0 0xe61c0000 0 0x200>;
517 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
530 reg = <0 0xe61e0000 0 0x30>;
543 reg = <0 0xe6fc0000 0 0x30>;
556 reg = <0 0xe6fd0000 0 0x30>;
569 reg = <0 0xe6fe0000 0 0x30>;
582 reg = <0 0xffc00000 0 0x30>;
595 #size-cells = <0>;
598 reg = <0 0xe6500000 0 0x40>;
603 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
604 <&dmac2 0x91>, <&dmac2 0x90>;
612 #size-cells = <0>;
615 reg = <0 0xe6508000 0 0x40>;
620 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
621 <&dmac2 0x93>, <&dmac2 0x92>;
629 #size-cells = <0>;
632 reg = <0 0xe6510000 0 0x40>;
637 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
638 <&dmac2 0x95>, <&dmac2 0x94>;
646 #size-cells = <0>;
649 reg = <0 0xe66d0000 0 0x40>;
654 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
662 #size-cells = <0>;
665 reg = <0 0xe66d8000 0 0x40>;
670 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
678 #size-cells = <0>;
681 reg = <0 0xe66e0000 0 0x40>;
686 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
694 #size-cells = <0>;
697 reg = <0 0xe66e8000 0 0x40>;
702 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
710 #size-cells = <0>;
714 reg = <0 0xe60b0000 0 0x425>;
719 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
728 reg = <0 0xe6540000 0 0x60>;
734 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
735 <&dmac2 0x31>, <&dmac2 0x30>;
746 reg = <0 0xe6550000 0 0x60>;
752 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
753 <&dmac2 0x33>, <&dmac2 0x32>;
764 reg = <0 0xe6560000 0 0x60>;
770 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
771 <&dmac2 0x35>, <&dmac2 0x34>;
782 reg = <0 0xe66a0000 0 0x60>;
788 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
799 reg = <0 0xe66b0000 0 0x60>;
805 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
815 reg = <0 0xe6590000 0 0x200>;
818 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
819 <&usb_dmac1 0>, <&usb_dmac1 1>;
832 reg = <0 0xe6590630 0 0x02>;
837 #clock-cells = <0>;
847 reg = <0 0xe65a0000 0 0x100>;
861 reg = <0 0xe65b0000 0 0x100>;
875 reg = <0 0xe65ee000 0 0x90>;
881 #phy-cells = <0>;
888 reg = <0 0xe6700000 0 0x10000>;
917 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
930 reg = <0 0xe7300000 0 0x10000>;
959 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
972 reg = <0 0xe7310000 0 0x10000>;
1013 reg = <0 0xe6740000 0 0x1000>;
1014 renesas,ipmmu-main = <&ipmmu_mm 0>;
1021 reg = <0 0xe7740000 0 0x1000>;
1029 reg = <0 0xe6570000 0 0x1000>;
1037 reg = <0 0xe67b0000 0 0x1000>;
1046 reg = <0 0xec670000 0 0x1000>;
1054 reg = <0 0xfd800000 0 0x1000>;
1062 reg = <0 0xfd950000 0 0x1000>;
1070 reg = <0 0xfe6b0000 0 0x1000>;
1078 reg = <0 0xfebd0000 0 0x1000>;
1087 reg = <0 0xe6800000 0 0x800>;
1125 rx-internal-delay-ps = <0>;
1126 tx-internal-delay-ps = <0>;
1129 #size-cells = <0>;
1136 reg = <0 0xe6c30000 0 0x1000>;
1152 reg = <0 0xe6c38000 0 0x1000>;
1168 reg = <0 0xe66c0000 0 0x8000>;
1193 reg = <0 0xe6e30000 0 0x8>;
1203 reg = <0 0xe6e31000 0 0x8>;
1213 reg = <0 0xe6e32000 0 0x8>;
1223 reg = <0 0xe6e33000 0 0x8>;
1233 reg = <0 0xe6e34000 0 0x8>;
1243 reg = <0 0xe6e35000 0 0x8>;
1253 reg = <0 0xe6e36000 0 0x8>;
1264 reg = <0 0xe6e60000 0 0x40>;
1270 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1271 <&dmac2 0x51>, <&dmac2 0x50>;
1281 reg = <0 0xe6e68000 0 0x40>;
1287 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1288 <&dmac2 0x53>, <&dmac2 0x52>;
1298 reg = <0 0xe6e88000 0 0x40>;
1304 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1305 <&dmac2 0x13>, <&dmac2 0x12>;
1315 reg = <0 0xe6c50000 0 0x40>;
1321 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1331 reg = <0 0xe6c40000 0 0x40>;
1337 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1347 reg = <0 0xe6f30000 0 0x40>;
1353 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
1354 <&dmac2 0x5b>, <&dmac2 0x5a>;
1364 reg = <0 0xe6e90000 0 0x0064>;
1367 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1368 <&dmac2 0x41>, <&dmac2 0x40>;
1373 #size-cells = <0>;
1380 reg = <0 0xe6ea0000 0 0x0064>;
1383 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1384 <&dmac2 0x43>, <&dmac2 0x42>;
1389 #size-cells = <0>;
1396 reg = <0 0xe6c00000 0 0x0064>;
1399 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1404 #size-cells = <0>;
1411 reg = <0 0xe6c10000 0 0x0064>;
1414 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1419 #size-cells = <0>;
1425 reg = <0 0xe6ef0000 0 0x1000>;
1430 renesas,id = <0>;
1435 #size-cells = <0>;
1439 #size-cells = <0>;
1443 vin0csi20: endpoint@0 {
1444 reg = <0>;
1457 reg = <0 0xe6ef1000 0 0x1000>;
1467 #size-cells = <0>;
1471 #size-cells = <0>;
1475 vin1csi20: endpoint@0 {
1476 reg = <0>;
1489 reg = <0 0xe6ef2000 0 0x1000>;
1499 #size-cells = <0>;
1503 #size-cells = <0>;
1507 vin2csi20: endpoint@0 {
1508 reg = <0>;
1521 reg = <0 0xe6ef3000 0 0x1000>;
1531 #size-cells = <0>;
1535 #size-cells = <0>;
1539 vin3csi20: endpoint@0 {
1540 reg = <0>;
1553 reg = <0 0xe6ef4000 0 0x1000>;
1563 #size-cells = <0>;
1567 #size-cells = <0>;
1571 vin4csi20: endpoint@0 {
1572 reg = <0>;
1585 reg = <0 0xe6ef5000 0 0x1000>;
1595 #size-cells = <0>;
1599 #size-cells = <0>;
1603 vin5csi20: endpoint@0 {
1604 reg = <0>;
1617 reg = <0 0xe6ef6000 0 0x1000>;
1627 #size-cells = <0>;
1631 #size-cells = <0>;
1635 vin6csi20: endpoint@0 {
1636 reg = <0>;
1649 reg = <0 0xe6ef7000 0 0x1000>;
1659 #size-cells = <0>;
1663 #size-cells = <0>;
1667 vin7csi20: endpoint@0 {
1668 reg = <0>;
1683 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1689 * clkout : #clock-cells = <0>; <&rcar_sound>;
1693 reg = <0 0xec500000 0 0x1000>, /* SCU */
1694 <0 0xec5a0000 0 0x100>, /* ADG */
1695 <0 0xec540000 0 0x1000>, /* SSIU */
1696 <0 0xec541000 0 0x280>, /* SSI */
1697 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1720 "ssi.1", "ssi.0",
1723 "src.1", "src.0",
1724 "mix.1", "mix.0",
1725 "ctu.1", "ctu.0",
1726 "dvc.0", "dvc.1",
1738 "ssi.1", "ssi.0";
1742 ctu00: ctu-0 { };
1753 dvc0: dvc-0 {
1754 dmas = <&audma1 0xbc>;
1758 dmas = <&audma1 0xbe>;
1764 mix0: mix-0 { };
1769 src0: src-0 {
1771 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1776 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1781 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1786 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1791 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1796 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1801 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1806 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1811 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1816 dmas = <&audma0 0x97>, <&audma1 0xba>;
1822 ssi0: ssi-0 {
1824 dmas = <&audma0 0x01>, <&audma1 0x02>;
1829 dmas = <&audma0 0x03>, <&audma1 0x04>;
1834 dmas = <&audma0 0x05>, <&audma1 0x06>;
1839 dmas = <&audma0 0x07>, <&audma1 0x08>;
1844 dmas = <&audma0 0x09>, <&audma1 0x0a>;
1849 dmas = <&audma0 0x0b>, <&audma1 0x0c>;
1854 dmas = <&audma0 0x0d>, <&audma1 0x0e>;
1859 dmas = <&audma0 0x0f>, <&audma1 0x10>;
1864 dmas = <&audma0 0x11>, <&audma1 0x12>;
1869 dmas = <&audma0 0x13>, <&audma1 0x14>;
1875 ssiu00: ssiu-0 {
1876 dmas = <&audma0 0x15>, <&audma1 0x16>;
1880 dmas = <&audma0 0x35>, <&audma1 0x36>;
1884 dmas = <&audma0 0x37>, <&audma1 0x38>;
1888 dmas = <&audma0 0x47>, <&audma1 0x48>;
1892 dmas = <&audma0 0x3F>, <&audma1 0x40>;
1896 dmas = <&audma0 0x43>, <&audma1 0x44>;
1900 dmas = <&audma0 0x4F>, <&audma1 0x50>;
1904 dmas = <&audma0 0x53>, <&audma1 0x54>;
1908 dmas = <&audma0 0x49>, <&audma1 0x4a>;
1912 dmas = <&audma0 0x4B>, <&audma1 0x4C>;
1916 dmas = <&audma0 0x57>, <&audma1 0x58>;
1920 dmas = <&audma0 0x59>, <&audma1 0x5A>;
1924 dmas = <&audma0 0x5F>, <&audma1 0x60>;
1928 dmas = <&audma0 0xC3>, <&audma1 0xC4>;
1932 dmas = <&audma0 0xC7>, <&audma1 0xC8>;
1936 dmas = <&audma0 0xCB>, <&audma1 0xCC>;
1940 dmas = <&audma0 0x63>, <&audma1 0x64>;
1944 dmas = <&audma0 0x67>, <&audma1 0x68>;
1948 dmas = <&audma0 0x6B>, <&audma1 0x6C>;
1952 dmas = <&audma0 0x6D>, <&audma1 0x6E>;
1956 dmas = <&audma0 0xCF>, <&audma1 0xCE>;
1960 dmas = <&audma0 0xEB>, <&audma1 0xEC>;
1964 dmas = <&audma0 0xED>, <&audma1 0xEE>;
1968 dmas = <&audma0 0xEF>, <&audma1 0xF0>;
1972 dmas = <&audma0 0x6f>, <&audma1 0x70>;
1976 dmas = <&audma0 0x21>, <&audma1 0x22>;
1980 dmas = <&audma0 0x23>, <&audma1 0x24>;
1984 dmas = <&audma0 0x25>, <&audma1 0x26>;
1988 dmas = <&audma0 0x27>, <&audma1 0x28>;
1992 dmas = <&audma0 0x29>, <&audma1 0x2A>;
1996 dmas = <&audma0 0x2B>, <&audma1 0x2C>;
2000 dmas = <&audma0 0x2D>, <&audma1 0x2E>;
2004 dmas = <&audma0 0x71>, <&audma1 0x72>;
2008 dmas = <&audma0 0x17>, <&audma1 0x18>;
2012 dmas = <&audma0 0x19>, <&audma1 0x1A>;
2016 dmas = <&audma0 0x1B>, <&audma1 0x1C>;
2020 dmas = <&audma0 0x1D>, <&audma1 0x1E>;
2024 dmas = <&audma0 0x1F>, <&audma1 0x20>;
2028 dmas = <&audma0 0x31>, <&audma1 0x32>;
2032 dmas = <&audma0 0x33>, <&audma1 0x34>;
2036 dmas = <&audma0 0x73>, <&audma1 0x74>;
2040 dmas = <&audma0 0x75>, <&audma1 0x76>;
2044 dmas = <&audma0 0x79>, <&audma1 0x7a>;
2048 dmas = <&audma0 0x7b>, <&audma1 0x7c>;
2052 dmas = <&audma0 0x7d>, <&audma1 0x7e>;
2056 dmas = <&audma0 0x7F>, <&audma1 0x80>;
2060 dmas = <&audma0 0x81>, <&audma1 0x82>;
2064 dmas = <&audma0 0x83>, <&audma1 0x84>;
2068 dmas = <&audma0 0xA3>, <&audma1 0xA4>;
2072 dmas = <&audma0 0xA5>, <&audma1 0xA6>;
2076 dmas = <&audma0 0xA7>, <&audma1 0xA8>;
2080 dmas = <&audma0 0xA9>, <&audma1 0xAA>;
2089 reg = <0 0xec700000 0 0x10000>;
2118 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
2131 reg = <0 0xec720000 0 0x10000>;
2173 reg = <0 0xee000000 0 0xc00>;
2184 reg = <0 0xee020000 0 0x400>;
2194 reg = <0 0xee080000 0 0x100>;
2206 reg = <0 0xee0a0000 0 0x100>;
2218 reg = <0 0xee080100 0 0x100>;
2231 reg = <0 0xee0a0100 0 0x100>;
2245 reg = <0 0xee080200 0 0x700>;
2257 reg = <0 0xee0a0200 0 0x700>;
2268 reg = <0 0xee100000 0 0x2000>;
2281 reg = <0 0xee120000 0 0x2000>;
2294 reg = <0 0xee140000 0 0x2000>;
2307 reg = <0 0xee160000 0 0x2000>;
2320 reg = <0 0xee200000 0 0x200>,
2321 <0 0x08000000 0 0x4000000>,
2322 <0 0xee208000 0 0x100>;
2329 #size-cells = <0>;
2336 #address-cells = <0>;
2338 reg = <0x0 0xf1010000 0 0x1000>,
2339 <0x0 0xf1020000 0 0x20000>,
2340 <0x0 0xf1040000 0 0x20000>,
2341 <0x0 0xf1060000 0 0x20000>;
2353 reg = <0 0xfe000000 0 0x80000>;
2356 bus-range = <0x00 0xff>;
2358 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
2359 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
2360 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
2361 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
2363 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2368 interrupt-map-mask = <0 0 0 0>;
2369 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
2374 iommu-map = <0 &ipmmu_hc 0 1>;
2375 iommu-map-mask = <0>;
2382 reg = <0 0xee800000 0 0x80000>;
2385 bus-range = <0x00 0xff>;
2387 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
2388 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
2389 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
2390 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
2392 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
2397 interrupt-map-mask = <0 0 0 0>;
2398 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2403 iommu-map = <0 &ipmmu_hc 1 1>;
2404 iommu-map-mask = <0>;
2411 reg = <0x0 0xfe000000 0 0x80000>,
2412 <0x0 0xfe100000 0 0x100000>,
2413 <0x0 0xfe200000 0 0x200000>,
2414 <0x0 0x30000000 0 0x8000000>,
2415 <0x0 0x38000000 0 0x8000000>;
2430 reg = <0x0 0xee800000 0 0x80000>,
2431 <0x0 0xee900000 0 0x100000>,
2432 <0x0 0xeea00000 0 0x200000>,
2433 <0x0 0xc0000000 0 0x8000000>,
2434 <0x0 0xc8000000 0 0x8000000>;
2448 reg = <0 0xfe940000 0 0x2400>;
2458 reg = <0 0xfe950000 0 0x200>;
2466 reg = <0 0xfe96f000 0 0x200>;
2474 reg = <0 0xfea27000 0 0x200>;
2483 reg = <0 0xfea2f000 0 0x200>;
2492 reg = <0 0xfea37000 0 0x200>;
2501 reg = <0 0xfe9af000 0 0x200>;
2510 reg = <0 0xfe960000 0 0x8000>;
2521 reg = <0 0xfea20000 0 0x5000>;
2532 reg = <0 0xfea28000 0 0x5000>;
2543 reg = <0 0xfea30000 0 0x5000>;
2554 reg = <0 0xfe9a0000 0 0x8000>;
2565 reg = <0 0xfea80000 0 0x10000>;
2574 #size-cells = <0>;
2576 port@0 {
2577 reg = <0>;
2582 #size-cells = <0>;
2586 csi20vin0: endpoint@0 {
2587 reg = <0>;
2624 reg = <0 0xfeaa0000 0 0x10000>;
2633 #size-cells = <0>;
2635 port@0 {
2636 reg = <0>;
2641 #size-cells = <0>;
2645 csi40vin0: endpoint@0 {
2646 reg = <0>;
2685 reg = <0 0xfead0000 0 0x10000>;
2696 #size-cells = <0>;
2697 port@0 {
2698 reg = <0>;
2715 reg = <0 0xfeb00000 0 0x70000>;
2721 clock-names = "du.0", "du.1", "du.2";
2723 reset-names = "du.0", "du.2";
2726 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;
2730 #size-cells = <0>;
2732 port@0 {
2733 reg = <0>;
2752 reg = <0 0xfeb90000 0 0x14>;
2760 #size-cells = <0>;
2762 port@0 {
2763 reg = <0>;
2776 reg = <0 0xfff00044 0 4>;
2784 thermal-sensors = <&tsc 0>;
2820 cooling-device = <&a57_0 0 2>;
2825 cooling-device = <&a53_0 0 2>;
2856 #clock-cells = <0>;
2857 clock-frequency = <0>;
2862 #clock-cells = <0>;
2863 clock-frequency = <0>;