Lines Matching +full:tsens +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
11 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/power/qcom,rpmhpd.h>
19 #include <dt-bindings/soc/qcom,gpr.h>
20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
21 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
22 #include <dt-bindings/phy/phy-qcom-qmp.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
39 sleep_clk: sleep-clk {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
44 bi_tcxo_div2: bi-tcxo-div2-clk {
45 #clock-cells = <0>;
46 compatible = "fixed-factor-clock";
48 clock-mult = <1>;
49 clock-div = <2>;
52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
53 #clock-cells = <0>;
54 compatible = "fixed-factor-clock";
56 clock-mult = <1>;
57 clock-div = <2>;
60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
67 #address-cells = <2>;
68 #size-cells = <0>;
72 compatible = "arm,cortex-a510";
75 enable-method = "psci";
76 next-level-cache = <&L2_0>;
77 power-domains = <&CPU_PD0>;
78 power-domain-names = "psci";
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 #cooling-cells = <2>;
83 L2_0: l2-cache {
85 cache-level = <2>;
86 cache-unified;
87 next-level-cache = <&L3_0>;
88 L3_0: l3-cache {
90 cache-level = <3>;
91 cache-unified;
98 compatible = "arm,cortex-a510";
101 enable-method = "psci";
102 next-level-cache = <&L2_100>;
103 power-domains = <&CPU_PD1>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 capacity-dmips-mhz = <1024>;
107 dynamic-power-coefficient = <100>;
108 #cooling-cells = <2>;
109 L2_100: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a510";
122 enable-method = "psci";
123 next-level-cache = <&L2_200>;
124 power-domains = <&CPU_PD2>;
125 power-domain-names = "psci";
126 qcom,freq-domain = <&cpufreq_hw 0>;
127 capacity-dmips-mhz = <1024>;
128 dynamic-power-coefficient = <100>;
129 #cooling-cells = <2>;
130 L2_200: l2-cache {
132 cache-level = <2>;
133 cache-unified;
134 next-level-cache = <&L3_0>;
140 compatible = "arm,cortex-a715";
143 enable-method = "psci";
144 next-level-cache = <&L2_300>;
145 power-domains = <&CPU_PD3>;
146 power-domain-names = "psci";
147 qcom,freq-domain = <&cpufreq_hw 1>;
148 capacity-dmips-mhz = <1792>;
149 dynamic-power-coefficient = <270>;
150 #cooling-cells = <2>;
151 L2_300: l2-cache {
153 cache-level = <2>;
154 cache-unified;
155 next-level-cache = <&L3_0>;
161 compatible = "arm,cortex-a715";
164 enable-method = "psci";
165 next-level-cache = <&L2_400>;
166 power-domains = <&CPU_PD4>;
167 power-domain-names = "psci";
168 qcom,freq-domain = <&cpufreq_hw 1>;
169 capacity-dmips-mhz = <1792>;
170 dynamic-power-coefficient = <270>;
171 #cooling-cells = <2>;
172 L2_400: l2-cache {
174 cache-level = <2>;
175 cache-unified;
176 next-level-cache = <&L3_0>;
182 compatible = "arm,cortex-a710";
185 enable-method = "psci";
186 next-level-cache = <&L2_500>;
187 power-domains = <&CPU_PD5>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 1>;
190 capacity-dmips-mhz = <1792>;
191 dynamic-power-coefficient = <270>;
192 #cooling-cells = <2>;
193 L2_500: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
203 compatible = "arm,cortex-a710";
206 enable-method = "psci";
207 next-level-cache = <&L2_600>;
208 power-domains = <&CPU_PD6>;
209 power-domain-names = "psci";
210 qcom,freq-domain = <&cpufreq_hw 1>;
211 capacity-dmips-mhz = <1792>;
212 dynamic-power-coefficient = <270>;
213 #cooling-cells = <2>;
214 L2_600: l2-cache {
216 cache-level = <2>;
217 cache-unified;
218 next-level-cache = <&L3_0>;
224 compatible = "arm,cortex-x3";
227 enable-method = "psci";
228 next-level-cache = <&L2_700>;
229 power-domains = <&CPU_PD7>;
230 power-domain-names = "psci";
231 qcom,freq-domain = <&cpufreq_hw 2>;
232 capacity-dmips-mhz = <1894>;
233 dynamic-power-coefficient = <588>;
234 #cooling-cells = <2>;
235 L2_700: l2-cache {
237 cache-level = <2>;
238 cache-unified;
239 next-level-cache = <&L3_0>;
243 cpu-map {
279 idle-states {
280 entry-method = "psci";
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "silver-rail-power-collapse";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <800>;
287 exit-latency-us = <750>;
288 min-residency-us = <4090>;
289 local-timer-stop;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 idle-state-name = "gold-rail-power-collapse";
295 arm,psci-suspend-param = <0x40000004>;
296 entry-latency-us = <600>;
297 exit-latency-us = <1550>;
298 min-residency-us = <4791>;
299 local-timer-stop;
303 domain-idle-states {
304 CLUSTER_SLEEP_0: cluster-sleep-0 {
305 compatible = "domain-idle-state";
306 arm,psci-suspend-param = <0x41000044>;
307 entry-latency-us = <1050>;
308 exit-latency-us = <2500>;
309 min-residency-us = <5309>;
312 CLUSTER_SLEEP_1: cluster-sleep-1 {
313 compatible = "domain-idle-state";
314 arm,psci-suspend-param = <0x4100c344>;
315 entry-latency-us = <2700>;
316 exit-latency-us = <3500>;
317 min-residency-us = <13959>;
324 compatible = "qcom,scm-sm8550", "qcom,scm";
329 clk_virt: interconnect-0 {
330 compatible = "qcom,sm8550-clk-virt";
331 #interconnect-cells = <2>;
332 qcom,bcm-voters = <&apps_bcm_voter>;
335 mc_virt: interconnect-1 {
336 compatible = "qcom,sm8550-mc-virt";
337 #interconnect-cells = <2>;
338 qcom,bcm-voters = <&apps_bcm_voter>;
348 compatible = "arm,armv8-pmuv3";
353 compatible = "arm,psci-1.0";
356 CPU_PD0: power-domain-cpu0 {
357 #power-domain-cells = <0>;
358 power-domains = <&CLUSTER_PD>;
359 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
362 CPU_PD1: power-domain-cpu1 {
363 #power-domain-cells = <0>;
364 power-domains = <&CLUSTER_PD>;
365 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
368 CPU_PD2: power-domain-cpu2 {
369 #power-domain-cells = <0>;
370 power-domains = <&CLUSTER_PD>;
371 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
374 CPU_PD3: power-domain-cpu3 {
375 #power-domain-cells = <0>;
376 power-domains = <&CLUSTER_PD>;
377 domain-idle-states = <&BIG_CPU_SLEEP_0>;
380 CPU_PD4: power-domain-cpu4 {
381 #power-domain-cells = <0>;
382 power-domains = <&CLUSTER_PD>;
383 domain-idle-states = <&BIG_CPU_SLEEP_0>;
386 CPU_PD5: power-domain-cpu5 {
387 #power-domain-cells = <0>;
388 power-domains = <&CLUSTER_PD>;
389 domain-idle-states = <&BIG_CPU_SLEEP_0>;
392 CPU_PD6: power-domain-cpu6 {
393 #power-domain-cells = <0>;
394 power-domains = <&CLUSTER_PD>;
395 domain-idle-states = <&BIG_CPU_SLEEP_0>;
398 CPU_PD7: power-domain-cpu7 {
399 #power-domain-cells = <0>;
400 power-domains = <&CLUSTER_PD>;
401 domain-idle-states = <&BIG_CPU_SLEEP_0>;
404 CLUSTER_PD: power-domain-cluster {
405 #power-domain-cells = <0>;
406 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
410 reserved_memory: reserved-memory {
411 #address-cells = <2>;
412 #size-cells = <2>;
415 hyp_mem: hyp-region@80000000 {
417 no-map;
420 cpusys_vm_mem: cpusys-vm-region@80a00000 {
422 no-map;
425 hyp_tags_mem: hyp-tags-region@80e00000 {
427 no-map;
430 xbl_sc_mem: xbl-sc-region@d8100000 {
432 no-map;
435 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
437 no-map;
441 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
443 no-map;
446 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
447 compatible = "qcom,cmd-db";
449 no-map;
453 aop_config_merged_mem: aop-config-merged-region@81c80000 {
455 no-map;
463 no-map;
466 adsp_mhi_mem: adsp-mhi-region@81f00000 {
468 no-map;
471 global_sync_mem: global-sync-region@82600000 {
473 no-map;
476 tz_stat_mem: tz-stat-region@82700000 {
478 no-map;
481 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
483 no-map;
486 mpss_mem: mpss-region@8a800000 {
488 no-map;
491 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
493 no-map;
496 ipa_fw_mem: ipa-fw-region@9b080000 {
498 no-map;
501 ipa_gsi_mem: ipa-gsi-region@9b090000 {
503 no-map;
506 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
508 no-map;
511 spss_region_mem: spss-region@9b100000 {
513 no-map;
517 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
519 no-map;
523 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
525 no-map;
528 camera_mem: camera-region@9b300000 {
530 no-map;
533 video_mem: video-region@9bb00000 {
535 no-map;
538 cvp_mem: cvp-region@9c200000 {
540 no-map;
543 cdsp_mem: cdsp-region@9c900000 {
545 no-map;
548 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
550 no-map;
553 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
555 no-map;
558 adspslpi_mem: adspslpi-region@9ea00000 {
560 no-map;
567 rmtfs_mem: rmtfs-region@d4a80000 {
568 compatible = "qcom,rmtfs-mem";
570 no-map;
572 qcom,client-id = <1>;
576 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
578 no-map;
581 tz_reserved_mem: tz-reserved-region@d8000000 {
583 no-map;
586 cpucp_fw_mem: cpucp-fw-region@d8140000 {
588 no-map;
591 qtee_mem: qtee-region@d8300000 {
593 no-map;
596 ta_mem: ta-region@d8800000 {
598 no-map;
601 tz_tags_mem: tz-tags-region@e1200000 {
603 no-map;
606 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
608 no-map;
611 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
613 no-map;
616 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
618 no-map;
621 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
623 no-map;
626 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
628 no-map;
631 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
633 no-map;
636 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
638 no-map;
641 oem_vm_mem: oem-vm-region@f8400000 {
643 no-map;
646 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
648 no-map;
651 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
653 no-map;
656 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
658 no-map;
661 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
663 no-map;
667 smp2p-adsp {
670 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
676 qcom,local-pid = <0>;
677 qcom,remote-pid = <2>;
679 smp2p_adsp_out: master-kernel {
680 qcom,entry-name = "master-kernel";
681 #qcom,smem-state-cells = <1>;
684 smp2p_adsp_in: slave-kernel {
685 qcom,entry-name = "slave-kernel";
686 interrupt-controller;
687 #interrupt-cells = <2>;
691 smp2p-cdsp {
694 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
700 qcom,local-pid = <0>;
701 qcom,remote-pid = <5>;
703 smp2p_cdsp_out: master-kernel {
704 qcom,entry-name = "master-kernel";
705 #qcom,smem-state-cells = <1>;
708 smp2p_cdsp_in: slave-kernel {
709 qcom,entry-name = "slave-kernel";
710 interrupt-controller;
711 #interrupt-cells = <2>;
715 smp2p-modem {
718 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
724 qcom,local-pid = <0>;
725 qcom,remote-pid = <1>;
727 smp2p_modem_out: master-kernel {
728 qcom,entry-name = "master-kernel";
729 #qcom,smem-state-cells = <1>;
732 smp2p_modem_in: slave-kernel {
733 qcom,entry-name = "slave-kernel";
734 interrupt-controller;
735 #interrupt-cells = <2>;
738 ipa_smp2p_out: ipa-ap-to-modem {
739 qcom,entry-name = "ipa";
740 #qcom,smem-state-cells = <1>;
743 ipa_smp2p_in: ipa-modem-to-ap {
744 qcom,entry-name = "ipa";
745 interrupt-controller;
746 #interrupt-cells = <2>;
751 compatible = "simple-bus";
753 dma-ranges = <0 0 0 0 0x10 0>;
755 #address-cells = <2>;
756 #size-cells = <2>;
758 gcc: clock-controller@100000 {
759 compatible = "qcom,sm8550-gcc";
761 #clock-cells = <1>;
762 #reset-cells = <1>;
763 #power-domain-cells = <1>;
775 compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
778 interrupt-controller;
779 #interrupt-cells = <3>;
780 #mbox-cells = <2>;
783 gpi_dma2: dma-controller@800000 {
784 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
785 #dma-cells = <3>;
799 dma-channels = <12>;
800 dma-channel-mask = <0x3e>;
806 compatible = "qcom,geni-se-qup";
809 clock-names = "m-ahb", "s-ahb";
813 #address-cells = <2>;
814 #size-cells = <2>;
818 compatible = "qcom,geni-i2c";
820 clock-names = "se";
822 pinctrl-names = "default";
823 pinctrl-0 = <&qup_i2c8_data_clk>;
825 #address-cells = <1>;
826 #size-cells = <0>;
830 interconnect-names = "qup-core", "qup-config", "qup-memory";
833 dma-names = "tx", "rx";
838 compatible = "qcom,geni-spi";
840 clock-names = "se";
843 pinctrl-names = "default";
844 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
848 interconnect-names = "qup-core", "qup-config", "qup-memory";
851 dma-names = "tx", "rx";
852 #address-cells = <1>;
853 #size-cells = <0>;
858 compatible = "qcom,geni-i2c";
860 clock-names = "se";
862 pinctrl-names = "default";
863 pinctrl-0 = <&qup_i2c9_data_clk>;
865 #address-cells = <1>;
866 #size-cells = <0>;
870 interconnect-names = "qup-core", "qup-config", "qup-memory";
873 dma-names = "tx", "rx";
878 compatible = "qcom,geni-spi";
880 clock-names = "se";
883 pinctrl-names = "default";
884 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
888 interconnect-names = "qup-core", "qup-config", "qup-memory";
891 dma-names = "tx", "rx";
892 #address-cells = <1>;
893 #size-cells = <0>;
898 compatible = "qcom,geni-i2c";
900 clock-names = "se";
902 pinctrl-names = "default";
903 pinctrl-0 = <&qup_i2c10_data_clk>;
905 #address-cells = <1>;
906 #size-cells = <0>;
910 interconnect-names = "qup-core", "qup-config", "qup-memory";
913 dma-names = "tx", "rx";
918 compatible = "qcom,geni-spi";
920 clock-names = "se";
923 pinctrl-names = "default";
924 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
928 interconnect-names = "qup-core", "qup-config", "qup-memory";
931 dma-names = "tx", "rx";
932 #address-cells = <1>;
933 #size-cells = <0>;
938 compatible = "qcom,geni-i2c";
940 clock-names = "se";
942 pinctrl-names = "default";
943 pinctrl-0 = <&qup_i2c11_data_clk>;
945 #address-cells = <1>;
946 #size-cells = <0>;
950 interconnect-names = "qup-core", "qup-config", "qup-memory";
953 dma-names = "tx", "rx";
958 compatible = "qcom,geni-spi";
960 clock-names = "se";
963 pinctrl-names = "default";
964 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
968 interconnect-names = "qup-core", "qup-config", "qup-memory";
971 dma-names = "tx", "rx";
972 #address-cells = <1>;
973 #size-cells = <0>;
978 compatible = "qcom,geni-i2c";
980 clock-names = "se";
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c12_data_clk>;
985 #address-cells = <1>;
986 #size-cells = <0>;
990 interconnect-names = "qup-core", "qup-config", "qup-memory";
993 dma-names = "tx", "rx";
998 compatible = "qcom,geni-spi";
1000 clock-names = "se";
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1008 interconnect-names = "qup-core", "qup-config", "qup-memory";
1011 dma-names = "tx", "rx";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1018 compatible = "qcom,geni-i2c";
1020 clock-names = "se";
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_i2c13_data_clk>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1030 interconnect-names = "qup-core", "qup-config", "qup-memory";
1033 dma-names = "tx", "rx";
1038 compatible = "qcom,geni-spi";
1040 clock-names = "se";
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1048 interconnect-names = "qup-core", "qup-config", "qup-memory";
1051 dma-names = "tx", "rx";
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1058 compatible = "qcom,geni-i2c";
1060 clock-names = "se";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_i2c15_data_clk>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1070 interconnect-names = "qup-core", "qup-config", "qup-memory";
1073 dma-names = "tx", "rx";
1078 compatible = "qcom,geni-spi";
1080 clock-names = "se";
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1088 interconnect-names = "qup-core", "qup-config", "qup-memory";
1091 dma-names = "tx", "rx";
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1099 compatible = "qcom,geni-se-i2c-master-hub";
1101 clock-names = "s-ahb";
1103 #address-cells = <2>;
1104 #size-cells = <2>;
1109 compatible = "qcom,geni-i2c-master-hub";
1111 clock-names = "se", "core";
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&hub_i2c0_data_clk>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1121 interconnect-names = "qup-core", "qup-config";
1126 compatible = "qcom,geni-i2c-master-hub";
1128 clock-names = "se", "core";
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&hub_i2c1_data_clk>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1138 interconnect-names = "qup-core", "qup-config";
1143 compatible = "qcom,geni-i2c-master-hub";
1145 clock-names = "se", "core";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&hub_i2c2_data_clk>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1155 interconnect-names = "qup-core", "qup-config";
1160 compatible = "qcom,geni-i2c-master-hub";
1162 clock-names = "se", "core";
1165 pinctrl-names = "default";
1166 pinctrl-0 = <&hub_i2c3_data_clk>;
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1172 interconnect-names = "qup-core", "qup-config";
1177 compatible = "qcom,geni-i2c-master-hub";
1179 clock-names = "se", "core";
1182 pinctrl-names = "default";
1183 pinctrl-0 = <&hub_i2c4_data_clk>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1189 interconnect-names = "qup-core", "qup-config";
1194 compatible = "qcom,geni-i2c-master-hub";
1196 clock-names = "se", "core";
1199 pinctrl-names = "default";
1200 pinctrl-0 = <&hub_i2c5_data_clk>;
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1206 interconnect-names = "qup-core", "qup-config";
1211 compatible = "qcom,geni-i2c-master-hub";
1213 clock-names = "se", "core";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&hub_i2c6_data_clk>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1223 interconnect-names = "qup-core", "qup-config";
1228 compatible = "qcom,geni-i2c-master-hub";
1230 clock-names = "se", "core";
1233 pinctrl-names = "default";
1234 pinctrl-0 = <&hub_i2c7_data_clk>;
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1240 interconnect-names = "qup-core", "qup-config";
1245 compatible = "qcom,geni-i2c-master-hub";
1247 clock-names = "se", "core";
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&hub_i2c8_data_clk>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1257 interconnect-names = "qup-core", "qup-config";
1262 compatible = "qcom,geni-i2c-master-hub";
1264 clock-names = "se", "core";
1267 pinctrl-names = "default";
1268 pinctrl-0 = <&hub_i2c9_data_clk>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1274 interconnect-names = "qup-core", "qup-config";
1279 gpi_dma1: dma-controller@a00000 {
1280 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1281 #dma-cells = <3>;
1295 dma-channels = <12>;
1296 dma-channel-mask = <0x1e>;
1302 compatible = "qcom,geni-se-qup";
1305 clock-names = "m-ahb", "s-ahb";
1310 interconnect-names = "qup-core";
1311 #address-cells = <2>;
1312 #size-cells = <2>;
1316 compatible = "qcom,geni-i2c";
1318 clock-names = "se";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_i2c0_data_clk>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1328 interconnect-names = "qup-core", "qup-config", "qup-memory";
1331 dma-names = "tx", "rx";
1336 compatible = "qcom,geni-spi";
1338 clock-names = "se";
1341 pinctrl-names = "default";
1342 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1346 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dma-names = "tx", "rx";
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1356 compatible = "qcom,geni-i2c";
1358 clock-names = "se";
1360 pinctrl-names = "default";
1361 pinctrl-0 = <&qup_i2c1_data_clk>;
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1368 interconnect-names = "qup-core", "qup-config", "qup-memory";
1371 dma-names = "tx", "rx";
1376 compatible = "qcom,geni-spi";
1378 clock-names = "se";
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1386 interconnect-names = "qup-core", "qup-config", "qup-memory";
1389 dma-names = "tx", "rx";
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1396 compatible = "qcom,geni-i2c";
1398 clock-names = "se";
1400 pinctrl-names = "default";
1401 pinctrl-0 = <&qup_i2c2_data_clk>;
1403 #address-cells = <1>;
1404 #size-cells = <0>;
1408 interconnect-names = "qup-core", "qup-config", "qup-memory";
1411 dma-names = "tx", "rx";
1416 compatible = "qcom,geni-spi";
1418 clock-names = "se";
1421 pinctrl-names = "default";
1422 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1426 interconnect-names = "qup-core", "qup-config", "qup-memory";
1429 dma-names = "tx", "rx";
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1436 compatible = "qcom,geni-i2c";
1438 clock-names = "se";
1440 pinctrl-names = "default";
1441 pinctrl-0 = <&qup_i2c3_data_clk>;
1443 #address-cells = <1>;
1444 #size-cells = <0>;
1448 interconnect-names = "qup-core", "qup-config", "qup-memory";
1451 dma-names = "tx", "rx";
1456 compatible = "qcom,geni-spi";
1458 clock-names = "se";
1461 pinctrl-names = "default";
1462 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1466 interconnect-names = "qup-core", "qup-config", "qup-memory";
1469 dma-names = "tx", "rx";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1476 compatible = "qcom,geni-i2c";
1478 clock-names = "se";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_i2c4_data_clk>;
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1488 interconnect-names = "qup-core", "qup-config", "qup-memory";
1491 dma-names = "tx", "rx";
1496 compatible = "qcom,geni-spi";
1498 clock-names = "se";
1501 pinctrl-names = "default";
1502 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1506 interconnect-names = "qup-core", "qup-config", "qup-memory";
1509 dma-names = "tx", "rx";
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1516 compatible = "qcom,geni-i2c";
1518 clock-names = "se";
1520 pinctrl-names = "default";
1521 pinctrl-0 = <&qup_i2c5_data_clk>;
1526 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 dma-names = "tx", "rx";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1536 compatible = "qcom,geni-spi";
1538 clock-names = "se";
1541 pinctrl-names = "default";
1542 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1546 interconnect-names = "qup-core", "qup-config", "qup-memory";
1549 dma-names = "tx", "rx";
1550 #address-cells = <1>;
1551 #size-cells = <0>;
1556 compatible = "qcom,geni-i2c";
1558 clock-names = "se";
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_i2c6_data_clk>;
1566 interconnect-names = "qup-core", "qup-config", "qup-memory";
1569 dma-names = "tx", "rx";
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1576 compatible = "qcom,geni-spi";
1578 clock-names = "se";
1581 pinctrl-names = "default";
1582 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1586 interconnect-names = "qup-core", "qup-config", "qup-memory";
1589 dma-names = "tx", "rx";
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1596 compatible = "qcom,geni-debug-uart";
1598 clock-names = "se";
1600 pinctrl-names = "default";
1601 pinctrl-0 = <&qup_uart7_default>;
1603 interconnect-names = "qup-core", "qup-config";
1611 compatible = "qcom,sm8550-cnoc-main";
1613 #interconnect-cells = <2>;
1614 qcom,bcm-voters = <&apps_bcm_voter>;
1618 compatible = "qcom,sm8550-config-noc";
1620 #interconnect-cells = <2>;
1621 qcom,bcm-voters = <&apps_bcm_voter>;
1625 compatible = "qcom,sm8550-system-noc";
1627 #interconnect-cells = <2>;
1628 qcom,bcm-voters = <&apps_bcm_voter>;
1632 compatible = "qcom,sm8550-pcie-anoc";
1634 #interconnect-cells = <2>;
1637 qcom,bcm-voters = <&apps_bcm_voter>;
1641 compatible = "qcom,sm8550-aggre1-noc";
1643 #interconnect-cells = <2>;
1646 qcom,bcm-voters = <&apps_bcm_voter>;
1650 compatible = "qcom,sm8550-aggre2-noc";
1652 #interconnect-cells = <2>;
1654 qcom,bcm-voters = <&apps_bcm_voter>;
1658 compatible = "qcom,sm8550-mmss-noc";
1660 #interconnect-cells = <2>;
1661 qcom,bcm-voters = <&apps_bcm_voter>;
1666 compatible = "qcom,pcie-sm8550";
1672 reg-names = "parf", "dbi", "elbi", "atu", "config";
1673 #address-cells = <3>;
1674 #size-cells = <2>;
1677 bus-range = <0x00 0xff>;
1679 dma-coherent;
1681 linux,pci-domain = <0>;
1682 num-lanes = <2>;
1685 interrupt-names = "msi";
1687 #interrupt-cells = <1>;
1688 interrupt-map-mask = <0 0 0 0x7>;
1689 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1701 clock-names = "aux",
1711 interconnect-names = "pcie-mem", "cpu-pcie";
1713 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1717 reset-names = "pci";
1719 power-domains = <&gcc PCIE_0_GDSC>;
1722 phy-names = "pciephy";
1728 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1736 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1740 reset-names = "phy";
1742 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1743 assigned-clock-rates = <100000000>;
1745 power-domains = <&gcc PCIE_0_PHY_GDSC>;
1747 #clock-cells = <0>;
1748 clock-output-names = "pcie0_pipe_clk";
1750 #phy-cells = <0>;
1757 compatible = "qcom,pcie-sm8550";
1763 reg-names = "parf", "dbi", "elbi", "atu", "config";
1764 #address-cells = <3>;
1765 #size-cells = <2>;
1768 bus-range = <0x00 0xff>;
1770 dma-coherent;
1772 linux,pci-domain = <1>;
1773 num-lanes = <2>;
1776 interrupt-names = "msi";
1778 #interrupt-cells = <1>;
1779 interrupt-map-mask = <0 0 0 0x7>;
1780 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1793 clock-names = "aux",
1802 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1803 assigned-clock-rates = <19200000>;
1807 interconnect-names = "pcie-mem", "cpu-pcie";
1809 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1814 reset-names = "pci", "link_down";
1816 power-domains = <&gcc PCIE_1_GDSC>;
1819 phy-names = "pciephy";
1825 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1833 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1838 reset-names = "phy", "phy_nocsr";
1840 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1841 assigned-clock-rates = <100000000>;
1843 power-domains = <&gcc PCIE_1_PHY_GDSC>;
1845 #clock-cells = <0>;
1846 clock-output-names = "pcie1_pipe_clk";
1848 #phy-cells = <0>;
1853 cryptobam: dma-controller@1dc4000 {
1854 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1857 #dma-cells = <1>;
1859 qcom,controlled-remotely;
1865 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1868 dma-names = "rx", "tx";
1872 interconnect-names = "memory";
1876 compatible = "qcom,sm8550-qmp-ufs-phy";
1880 clock-names = "ref", "ref_aux";
1882 power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1885 reset-names = "ufsphy";
1887 #clock-cells = <1>;
1888 #phy-cells = <0>;
1894 compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1895 "jedec,ufs-2.0";
1899 phy-names = "ufsphy";
1900 lanes-per-direction = <2>;
1901 #reset-cells = <1>;
1903 reset-names = "rst";
1905 power-domains = <&gcc UFS_PHY_GDSC>;
1906 required-opps = <&rpmhpd_opp_nom>;
1909 dma-coherent;
1914 interconnect-names = "ufs-ddr", "cpu-ufs";
1915 clock-names = "core_clk",
1931 freq-table-hz =
1946 compatible = "qcom,sm8550-inline-crypto-engine",
1947 "qcom,inline-crypto-engine";
1953 compatible = "qcom,tcsr-mutex";
1955 #hwlock-cells = <1>;
1958 tcsr: clock-controller@1fc0000 {
1959 compatible = "qcom,sm8550-tcsr", "syscon";
1962 #clock-cells = <1>;
1963 #reset-cells = <1>;
1966 gpucc: clock-controller@3d90000 {
1967 compatible = "qcom,sm8550-gpucc";
1972 #clock-cells = <1>;
1973 #reset-cells = <1>;
1974 #power-domain-cells = <1>;
1978 compatible = "qcom,sm8550-mpss-pas";
1981 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
1987 interrupt-names = "wdog", "fatal", "ready", "handover",
1988 "stop-ack", "shutdown-ack";
1991 clock-names = "xo";
1993 power-domains = <&rpmhpd RPMHPD_CX>,
1995 power-domain-names = "cx", "mss";
1999 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2003 qcom,smem-states = <&smp2p_modem_out 0>;
2004 qcom,smem-state-names = "stop";
2008 glink-edge {
2009 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2015 qcom,remote-pid = <1>;
2020 compatible = "qcom,sm8550-lpass-wsa-macro";
2026 clock-names = "mclk", "macro", "dcodec", "fsgen";
2027 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2028 assigned-clock-rates = <19200000>;
2030 #clock-cells = <0>;
2031 clock-output-names = "wsa2-mclk";
2032 pinctrl-names = "default";
2033 pinctrl-0 = <&wsa2_swr_active>;
2034 #sound-dai-cells = <1>;
2037 swr3: soundwire-controller@6ab0000 {
2038 compatible = "qcom,soundwire-v2.0.0";
2042 clock-names = "iface";
2045 qcom,din-ports = <4>;
2046 qcom,dout-ports = <9>;
2048 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2049 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2050 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2051 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2052 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2053 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2054 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2055 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2056 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2058 #address-cells = <2>;
2059 #size-cells = <0>;
2060 #sound-dai-cells = <1>;
2065 compatible = "qcom,sm8550-lpass-rx-macro";
2071 clock-names = "mclk", "macro", "dcodec", "fsgen";
2073 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2074 assigned-clock-rates = <19200000>;
2076 #clock-cells = <0>;
2077 clock-output-names = "mclk";
2078 pinctrl-names = "default";
2079 pinctrl-0 = <&rx_swr_active>;
2080 #sound-dai-cells = <1>;
2083 swr1: soundwire-controller@6ad0000 {
2084 compatible = "qcom,soundwire-v2.0.0";
2088 clock-names = "iface";
2091 qcom,din-ports = <0>;
2092 qcom,dout-ports = <10>;
2094 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2095 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2096 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2097 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2098 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2099 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2100 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2101 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2102 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2104 #address-cells = <2>;
2105 #size-cells = <0>;
2106 #sound-dai-cells = <1>;
2111 compatible = "qcom,sm8550-lpass-tx-macro";
2117 clock-names = "mclk", "macro", "dcodec", "fsgen";
2118 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2120 assigned-clock-rates = <19200000>;
2122 #clock-cells = <0>;
2123 clock-output-names = "mclk";
2124 pinctrl-names = "default";
2125 pinctrl-0 = <&tx_swr_active>;
2126 #sound-dai-cells = <1>;
2130 compatible = "qcom,sm8550-lpass-wsa-macro";
2136 clock-names = "mclk", "macro", "dcodec", "fsgen";
2138 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2139 assigned-clock-rates = <19200000>;
2141 #clock-cells = <0>;
2142 clock-output-names = "mclk";
2143 pinctrl-names = "default";
2144 pinctrl-0 = <&wsa_swr_active>;
2145 #sound-dai-cells = <1>;
2148 swr0: soundwire-controller@6b10000 {
2149 compatible = "qcom,soundwire-v2.0.0";
2153 clock-names = "iface";
2156 qcom,din-ports = <4>;
2157 qcom,dout-ports = <9>;
2159 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2160 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2161 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2162 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2163 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2164 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2165 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2166 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2167 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2169 #address-cells = <2>;
2170 #size-cells = <0>;
2171 #sound-dai-cells = <1>;
2175 swr2: soundwire-controller@6d30000 {
2176 compatible = "qcom,soundwire-v2.0.0";
2180 interrupt-names = "core", "wakeup";
2182 clock-names = "iface";
2185 qcom,din-ports = <4>;
2186 qcom,dout-ports = <0>;
2187 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2188 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2189 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2190 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2191 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2192 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2193 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2194 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2195 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2197 #address-cells = <2>;
2198 #size-cells = <0>;
2199 #sound-dai-cells = <1>;
2204 compatible = "qcom,sm8550-lpass-va-macro";
2209 clock-names = "mclk", "macro", "dcodec";
2211 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2212 assigned-clock-rates = <19200000>;
2214 #clock-cells = <0>;
2215 clock-output-names = "fsgen";
2216 #sound-dai-cells = <1>;
2220 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2223 gpio-controller;
2224 #gpio-cells = <2>;
2225 gpio-ranges = <&lpass_tlmm 0 0 23>;
2229 clock-names = "core", "audio";
2231 tx_swr_active: tx-swr-active-state {
2232 clk-pins {
2235 drive-strength = <2>;
2236 slew-rate = <1>;
2237 bias-disable;
2240 data-pins {
2243 drive-strength = <2>;
2244 slew-rate = <1>;
2245 bias-bus-hold;
2249 rx_swr_active: rx-swr-active-state {
2250 clk-pins {
2253 drive-strength = <2>;
2254 slew-rate = <1>;
2255 bias-disable;
2258 data-pins {
2261 drive-strength = <2>;
2262 slew-rate = <1>;
2263 bias-bus-hold;
2267 dmic01_default: dmic01-default-state {
2268 clk-pins {
2271 drive-strength = <8>;
2272 output-high;
2275 data-pins {
2278 drive-strength = <8>;
2279 input-enable;
2283 dmic02_default: dmic02-default-state {
2284 clk-pins {
2287 drive-strength = <8>;
2288 output-high;
2291 data-pins {
2294 drive-strength = <8>;
2295 input-enable;
2299 wsa_swr_active: wsa-swr-active-state {
2300 clk-pins {
2303 drive-strength = <2>;
2304 slew-rate = <1>;
2305 bias-disable;
2308 data-pins {
2311 drive-strength = <2>;
2312 slew-rate = <1>;
2313 bias-bus-hold;
2317 wsa2_swr_active: wsa2-swr-active-state {
2318 clk-pins {
2321 drive-strength = <2>;
2322 slew-rate = <1>;
2323 bias-disable;
2326 data-pins {
2329 drive-strength = <2>;
2330 slew-rate = <1>;
2331 bias-bus-hold;
2337 compatible = "qcom,sm8550-lpass-lpiaon-noc";
2339 #interconnect-cells = <2>;
2340 qcom,bcm-voters = <&apps_bcm_voter>;
2344 compatible = "qcom,sm8550-lpass-lpicx-noc";
2346 #interconnect-cells = <2>;
2347 qcom,bcm-voters = <&apps_bcm_voter>;
2351 compatible = "qcom,sm8550-lpass-ag-noc";
2353 #interconnect-cells = <2>;
2354 qcom,bcm-voters = <&apps_bcm_voter>;
2358 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2363 interrupt-names = "hc_irq", "pwr_irq";
2368 clock-names = "iface", "core", "xo";
2370 qcom,dll-config = <0x0007642c>;
2371 qcom,ddr-config = <0x80040868>;
2372 power-domains = <&rpmhpd RPMHPD_CX>;
2373 operating-points-v2 = <&sdhc2_opp_table>;
2377 interconnect-names = "sdhc-ddr", "cpu-sdhc";
2378 bus-width = <4>;
2379 dma-coherent;
2381 /* Forbid SDR104/SDR50 - broken hw! */
2382 sdhci-caps-mask = <0x3 0>;
2386 sdhc2_opp_table: opp-table {
2387 compatible = "operating-points-v2";
2389 opp-19200000 {
2390 opp-hz = /bits/ 64 <19200000>;
2391 required-opps = <&rpmhpd_opp_min_svs>;
2394 opp-50000000 {
2395 opp-hz = /bits/ 64 <50000000>;
2396 required-opps = <&rpmhpd_opp_low_svs>;
2399 opp-100000000 {
2400 opp-hz = /bits/ 64 <100000000>;
2401 required-opps = <&rpmhpd_opp_svs>;
2404 opp-202000000 {
2405 opp-hz = /bits/ 64 <202000000>;
2406 required-opps = <&rpmhpd_opp_svs_l1>;
2411 videocc: clock-controller@aaf0000 {
2412 compatible = "qcom,sm8550-videocc";
2416 power-domains = <&rpmhpd RPMHPD_MMCX>;
2417 required-opps = <&rpmhpd_opp_low_svs>;
2418 #clock-cells = <1>;
2419 #reset-cells = <1>;
2420 #power-domain-cells = <1>;
2423 mdss: display-subsystem@ae00000 {
2424 compatible = "qcom,sm8550-mdss";
2426 reg-names = "mdss";
2429 interrupt-controller;
2430 #interrupt-cells = <1>;
2439 power-domains = <&dispcc MDSS_GDSC>;
2443 interconnect-names = "mdp0-mem", "mdp1-mem";
2447 #address-cells = <2>;
2448 #size-cells = <2>;
2453 mdss_mdp: display-controller@ae01000 {
2454 compatible = "qcom,sm8550-dpu";
2457 reg-names = "mdp", "vbif";
2459 interrupt-parent = <&mdss>;
2468 clock-names = "bus",
2475 power-domains = <&rpmhpd RPMHPD_MMCX>;
2477 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2478 assigned-clock-rates = <19200000>;
2480 operating-points-v2 = <&mdp_opp_table>;
2483 #address-cells = <1>;
2484 #size-cells = <0>;
2489 remote-endpoint = <&mdss_dsi0_in>;
2496 remote-endpoint = <&mdss_dsi1_in>;
2503 remote-endpoint = <&mdss_dp0_in>;
2508 mdp_opp_table: opp-table {
2509 compatible = "operating-points-v2";
2511 opp-200000000 {
2512 opp-hz = /bits/ 64 <200000000>;
2513 required-opps = <&rpmhpd_opp_low_svs>;
2516 opp-325000000 {
2517 opp-hz = /bits/ 64 <325000000>;
2518 required-opps = <&rpmhpd_opp_svs>;
2521 opp-375000000 {
2522 opp-hz = /bits/ 64 <375000000>;
2523 required-opps = <&rpmhpd_opp_svs_l1>;
2526 opp-514000000 {
2527 opp-hz = /bits/ 64 <514000000>;
2528 required-opps = <&rpmhpd_opp_nom>;
2533 mdss_dp0: displayport-controller@ae90000 {
2534 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2540 interrupt-parent = <&mdss>;
2547 clock-names = "core_iface",
2553 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2555 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2559 phy-names = "dp";
2561 #sound-dai-cells = <0>;
2563 operating-points-v2 = <&dp_opp_table>;
2564 power-domains = <&rpmhpd RPMHPD_MMCX>;
2569 #address-cells = <1>;
2570 #size-cells = <0>;
2575 remote-endpoint = <&dpu_intf0_out>;
2586 dp_opp_table: opp-table {
2587 compatible = "operating-points-v2";
2589 opp-162000000 {
2590 opp-hz = /bits/ 64 <162000000>;
2591 required-opps = <&rpmhpd_opp_low_svs_d1>;
2594 opp-270000000 {
2595 opp-hz = /bits/ 64 <270000000>;
2596 required-opps = <&rpmhpd_opp_low_svs>;
2599 opp-540000000 {
2600 opp-hz = /bits/ 64 <540000000>;
2601 required-opps = <&rpmhpd_opp_svs_l1>;
2604 opp-810000000 {
2605 opp-hz = /bits/ 64 <810000000>;
2606 required-opps = <&rpmhpd_opp_nom>;
2612 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2614 reg-names = "dsi_ctrl";
2616 interrupt-parent = <&mdss>;
2625 clock-names = "byte",
2632 power-domains = <&rpmhpd RPMHPD_MMCX>;
2634 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2636 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2639 operating-points-v2 = <&mdss_dsi_opp_table>;
2642 phy-names = "dsi";
2644 #address-cells = <1>;
2645 #size-cells = <0>;
2650 #address-cells = <1>;
2651 #size-cells = <0>;
2656 remote-endpoint = <&dpu_intf1_out>;
2667 mdss_dsi_opp_table: opp-table {
2668 compatible = "operating-points-v2";
2670 opp-187500000 {
2671 opp-hz = /bits/ 64 <187500000>;
2672 required-opps = <&rpmhpd_opp_low_svs>;
2675 opp-300000000 {
2676 opp-hz = /bits/ 64 <300000000>;
2677 required-opps = <&rpmhpd_opp_svs>;
2680 opp-358000000 {
2681 opp-hz = /bits/ 64 <358000000>;
2682 required-opps = <&rpmhpd_opp_svs_l1>;
2688 compatible = "qcom,sm8550-dsi-phy-4nm";
2692 reg-names = "dsi_phy",
2698 clock-names = "iface", "ref";
2700 #clock-cells = <1>;
2701 #phy-cells = <0>;
2707 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2709 reg-names = "dsi_ctrl";
2711 interrupt-parent = <&mdss>;
2720 clock-names = "byte",
2727 power-domains = <&rpmhpd RPMHPD_MMCX>;
2729 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2731 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2734 operating-points-v2 = <&mdss_dsi_opp_table>;
2737 phy-names = "dsi";
2739 #address-cells = <1>;
2740 #size-cells = <0>;
2745 #address-cells = <1>;
2746 #size-cells = <0>;
2751 remote-endpoint = <&dpu_intf2_out>;
2764 compatible = "qcom,sm8550-dsi-phy-4nm";
2768 reg-names = "dsi_phy",
2774 clock-names = "iface", "ref";
2776 #clock-cells = <1>;
2777 #phy-cells = <0>;
2783 dispcc: clock-controller@af00000 {
2784 compatible = "qcom,sm8550-dispcc";
2802 power-domains = <&rpmhpd RPMHPD_MMCX>;
2803 required-opps = <&rpmhpd_opp_low_svs>;
2804 #clock-cells = <1>;
2805 #reset-cells = <1>;
2806 #power-domain-cells = <1>;
2810 compatible = "qcom,sm8550-snps-eusb2-phy";
2812 #phy-cells = <0>;
2815 clock-names = "ref";
2823 compatible = "qcom,sm8550-qmp-usb3-dp-phy";
2830 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2832 power-domains = <&gcc USB3_PHY_GDSC>;
2836 reset-names = "phy", "common";
2838 #clock-cells = <1>;
2839 #phy-cells = <1>;
2844 #address-cells = <1>;
2845 #size-cells = <0>;
2871 compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
2873 #address-cells = <2>;
2874 #size-cells = <2>;
2883 clock-names = "cfg_noc",
2890 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2892 assigned-clock-rates = <19200000>, <200000000>;
2894 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2898 interrupt-names = "hs_phy_irq",
2903 power-domains = <&gcc USB30_PRIM_GDSC>;
2904 required-opps = <&rpmhpd_opp_nom>;
2910 interconnect-names = "usb-ddr", "apps-usb";
2924 phy-names = "usb2-phy", "usb3-phy";
2927 #address-cells = <1>;
2928 #size-cells = <0>;
2947 pdc: interrupt-controller@b220000 {
2948 compatible = "qcom,sm8550-pdc", "qcom,pdc";
2950 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2953 #interrupt-cells = <2>;
2954 interrupt-parent = <&intc>;
2955 interrupt-controller;
2958 tsens0: thermal-sensor@c271000 {
2959 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2965 interrupt-names = "uplow", "critical";
2966 #thermal-sensor-cells = <1>;
2969 tsens1: thermal-sensor@c272000 {
2970 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2976 interrupt-names = "uplow", "critical";
2977 #thermal-sensor-cells = <1>;
2980 tsens2: thermal-sensor@c273000 {
2981 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
2987 interrupt-names = "uplow", "critical";
2988 #thermal-sensor-cells = <1>;
2991 aoss_qmp: power-management@c300000 {
2992 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
2994 interrupt-parent = <&ipcc>;
2995 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2999 #clock-cells = <0>;
3003 compatible = "qcom,rpmh-stats";
3008 compatible = "qcom,spmi-pmic-arb";
3014 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3015 interrupt-names = "periph_irq";
3016 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3019 qcom,bus-id = <0>;
3020 #address-cells = <2>;
3021 #size-cells = <0>;
3022 interrupt-controller;
3023 #interrupt-cells = <4>;
3027 compatible = "qcom,sm8550-tlmm";
3030 gpio-controller;
3031 #gpio-cells = <2>;
3032 interrupt-controller;
3033 #interrupt-cells = <2>;
3034 gpio-ranges = <&tlmm 0 0 211>;
3035 wakeup-parent = <&pdc>;
3037 hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3041 drive-strength = <2>;
3042 bias-pull-up;
3045 hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3049 drive-strength = <2>;
3050 bias-pull-up;
3053 hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3057 drive-strength = <2>;
3058 bias-pull-up;
3061 hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3065 drive-strength = <2>;
3066 bias-pull-up;
3069 hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3073 drive-strength = <2>;
3074 bias-pull-up;
3077 hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3081 drive-strength = <2>;
3082 bias-pull-up;
3085 hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3089 drive-strength = <2>;
3090 bias-pull-up;
3093 hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3097 drive-strength = <2>;
3098 bias-pull-up;
3101 hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3105 drive-strength = <2>;
3106 bias-pull-up;
3109 hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3113 drive-strength = <2>;
3114 bias-pull-up;
3117 pcie0_default_state: pcie0-default-state {
3118 perst-pins {
3121 drive-strength = <2>;
3122 bias-pull-down;
3125 clkreq-pins {
3128 drive-strength = <2>;
3129 bias-pull-up;
3132 wake-pins {
3135 drive-strength = <2>;
3136 bias-pull-up;
3140 pcie1_default_state: pcie1-default-state {
3141 perst-pins {
3144 drive-strength = <2>;
3145 bias-pull-down;
3148 clkreq-pins {
3151 drive-strength = <2>;
3152 bias-pull-up;
3155 wake-pins {
3158 drive-strength = <2>;
3159 bias-pull-up;
3163 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3167 drive-strength = <2>;
3168 bias-pull-up = <2200>;
3171 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3175 drive-strength = <2>;
3176 bias-pull-up = <2200>;
3179 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3183 drive-strength = <2>;
3184 bias-pull-up = <2200>;
3187 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3191 drive-strength = <2>;
3192 bias-pull-up = <2200>;
3195 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3199 drive-strength = <2>;
3200 bias-pull-up = <2200>;
3203 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3207 drive-strength = <2>;
3208 bias-pull-up = <2200>;
3211 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3215 drive-strength = <2>;
3216 bias-pull-up = <2200>;
3219 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3220 scl-pins {
3223 drive-strength = <2>;
3224 bias-pull-up = <2200>;
3227 sda-pins {
3230 drive-strength = <2>;
3231 bias-pull-up = <2200>;
3235 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3239 drive-strength = <2>;
3240 bias-pull-up = <2200>;
3243 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3247 drive-strength = <2>;
3248 bias-pull-up = <2200>;
3251 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3255 drive-strength = <2>;
3256 bias-pull-up = <2200>;
3259 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3263 drive-strength = <2>;
3264 bias-pull-up = <2200>;
3267 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3271 drive-strength = <2>;
3272 bias-pull-up = <2200>;
3275 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3279 drive-strength = <2>;
3280 bias-pull-up = <2200>;
3283 qup_spi0_cs: qup-spi0-cs-state {
3286 drive-strength = <6>;
3287 bias-disable;
3290 qup_spi0_data_clk: qup-spi0-data-clk-state {
3294 drive-strength = <6>;
3295 bias-disable;
3298 qup_spi1_cs: qup-spi1-cs-state {
3301 drive-strength = <6>;
3302 bias-disable;
3305 qup_spi1_data_clk: qup-spi1-data-clk-state {
3309 drive-strength = <6>;
3310 bias-disable;
3313 qup_spi2_cs: qup-spi2-cs-state {
3316 drive-strength = <6>;
3317 bias-disable;
3320 qup_spi2_data_clk: qup-spi2-data-clk-state {
3324 drive-strength = <6>;
3325 bias-disable;
3328 qup_spi3_cs: qup-spi3-cs-state {
3331 drive-strength = <6>;
3332 bias-disable;
3335 qup_spi3_data_clk: qup-spi3-data-clk-state {
3339 drive-strength = <6>;
3340 bias-disable;
3343 qup_spi4_cs: qup-spi4-cs-state {
3346 drive-strength = <6>;
3347 bias-disable;
3350 qup_spi4_data_clk: qup-spi4-data-clk-state {
3354 drive-strength = <6>;
3355 bias-disable;
3358 qup_spi5_cs: qup-spi5-cs-state {
3361 drive-strength = <6>;
3362 bias-disable;
3365 qup_spi5_data_clk: qup-spi5-data-clk-state {
3369 drive-strength = <6>;
3370 bias-disable;
3373 qup_spi6_cs: qup-spi6-cs-state {
3376 drive-strength = <6>;
3377 bias-disable;
3380 qup_spi6_data_clk: qup-spi6-data-clk-state {
3384 drive-strength = <6>;
3385 bias-disable;
3388 qup_spi8_cs: qup-spi8-cs-state {
3391 drive-strength = <6>;
3392 bias-disable;
3395 qup_spi8_data_clk: qup-spi8-data-clk-state {
3399 drive-strength = <6>;
3400 bias-disable;
3403 qup_spi9_cs: qup-spi9-cs-state {
3406 drive-strength = <6>;
3407 bias-disable;
3410 qup_spi9_data_clk: qup-spi9-data-clk-state {
3414 drive-strength = <6>;
3415 bias-disable;
3418 qup_spi10_cs: qup-spi10-cs-state {
3421 drive-strength = <6>;
3422 bias-disable;
3425 qup_spi10_data_clk: qup-spi10-data-clk-state {
3429 drive-strength = <6>;
3430 bias-disable;
3433 qup_spi11_cs: qup-spi11-cs-state {
3436 drive-strength = <6>;
3437 bias-disable;
3440 qup_spi11_data_clk: qup-spi11-data-clk-state {
3444 drive-strength = <6>;
3445 bias-disable;
3448 qup_spi12_cs: qup-spi12-cs-state {
3451 drive-strength = <6>;
3452 bias-disable;
3455 qup_spi12_data_clk: qup-spi12-data-clk-state {
3459 drive-strength = <6>;
3460 bias-disable;
3463 qup_spi13_cs: qup-spi13-cs-state {
3466 drive-strength = <6>;
3467 bias-disable;
3470 qup_spi13_data_clk: qup-spi13-data-clk-state {
3474 drive-strength = <6>;
3475 bias-disable;
3478 qup_spi15_cs: qup-spi15-cs-state {
3481 drive-strength = <6>;
3482 bias-disable;
3485 qup_spi15_data_clk: qup-spi15-data-clk-state {
3489 drive-strength = <6>;
3490 bias-disable;
3493 qup_uart7_default: qup-uart7-default-state {
3497 drive-strength = <2>;
3498 bias-disable;
3501 sdc2_sleep: sdc2-sleep-state {
3502 clk-pins {
3504 bias-disable;
3505 drive-strength = <2>;
3508 cmd-pins {
3510 bias-pull-up;
3511 drive-strength = <2>;
3514 data-pins {
3516 bias-pull-up;
3517 drive-strength = <2>;
3521 sdc2_default: sdc2-default-state {
3522 clk-pins {
3524 bias-disable;
3525 drive-strength = <16>;
3528 cmd-pins {
3530 bias-pull-up;
3531 drive-strength = <10>;
3534 data-pins {
3536 bias-pull-up;
3537 drive-strength = <10>;
3543 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3545 #iommu-cells = <2>;
3546 #global-interrupts = <1>;
3646 intc: interrupt-controller@17100000 {
3647 compatible = "arm,gic-v3";
3651 #interrupt-cells = <3>;
3652 interrupt-controller;
3653 #redistributor-regions = <1>;
3654 redistributor-stride = <0 0x40000>;
3656 #address-cells = <2>;
3657 #size-cells = <2>;
3659 gic_its: msi-controller@17140000 {
3660 compatible = "arm,gic-v3-its";
3662 msi-controller;
3663 #msi-cells = <1>;
3668 compatible = "arm,armv7-timer-mem";
3671 #address-cells = <1>;
3672 #size-cells = <1>;
3677 frame-number = <0>;
3684 frame-number = <1>;
3691 frame-number = <2>;
3698 frame-number = <3>;
3705 frame-number = <4>;
3712 frame-number = <5>;
3719 frame-number = <6>;
3727 compatible = "qcom,rpmh-rsc";
3732 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3736 qcom,tcs-offset = <0xd00>;
3737 qcom,drv-id = <2>;
3738 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
3740 power-domains = <&CLUSTER_PD>;
3742 apps_bcm_voter: bcm-voter {
3743 compatible = "qcom,bcm-voter";
3746 rpmhcc: clock-controller {
3747 compatible = "qcom,sm8550-rpmh-clk";
3748 #clock-cells = <1>;
3749 clock-names = "xo";
3753 rpmhpd: power-controller {
3754 compatible = "qcom,sm8550-rpmhpd";
3755 #power-domain-cells = <1>;
3756 operating-points-v2 = <&rpmhpd_opp_table>;
3758 rpmhpd_opp_table: opp-table {
3759 compatible = "operating-points-v2";
3761 rpmhpd_opp_ret: opp-16 {
3762 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3765 rpmhpd_opp_min_svs: opp-48 {
3766 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3769 rpmhpd_opp_low_svs_d2: opp-52 {
3770 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
3773 rpmhpd_opp_low_svs_d1: opp-56 {
3774 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
3777 rpmhpd_opp_low_svs_d0: opp-60 {
3778 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
3781 rpmhpd_opp_low_svs: opp-64 {
3782 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3785 rpmhpd_opp_low_svs_l1: opp-80 {
3786 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
3789 rpmhpd_opp_svs: opp-128 {
3790 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3793 rpmhpd_opp_svs_l0: opp-144 {
3794 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
3797 rpmhpd_opp_svs_l1: opp-192 {
3798 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3801 rpmhpd_opp_nom: opp-256 {
3802 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3805 rpmhpd_opp_nom_l1: opp-320 {
3806 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3809 rpmhpd_opp_nom_l2: opp-336 {
3810 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3813 rpmhpd_opp_turbo: opp-384 {
3814 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3817 rpmhpd_opp_turbo_l1: opp-416 {
3818 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3825 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
3829 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
3831 clock-names = "xo", "alternate";
3835 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3836 #freq-domain-cells = <1>;
3837 #clock-cells = <1>;
3841 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3846 operating-points-v2 = <&llcc_bwmon_opp_table>;
3848 llcc_bwmon_opp_table: opp-table {
3849 compatible = "operating-points-v2";
3851 opp-0 {
3852 opp-peak-kBps = <2086000>;
3855 opp-1 {
3856 opp-peak-kBps = <2929000>;
3859 opp-2 {
3860 opp-peak-kBps = <5931000>;
3863 opp-3 {
3864 opp-peak-kBps = <6515000>;
3867 opp-4 {
3868 opp-peak-kBps = <7980000>;
3871 opp-5 {
3872 opp-peak-kBps = <10437000>;
3875 opp-6 {
3876 opp-peak-kBps = <12157000>;
3879 opp-7 {
3880 opp-peak-kBps = <14060000>;
3883 opp-8 {
3884 opp-peak-kBps = <16113000>;
3890 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
3895 operating-points-v2 = <&cpu_bwmon_opp_table>;
3897 cpu_bwmon_opp_table: opp-table {
3898 compatible = "operating-points-v2";
3900 opp-0 {
3901 opp-peak-kBps = <4577000>;
3904 opp-1 {
3905 opp-peak-kBps = <7110000>;
3908 opp-2 {
3909 opp-peak-kBps = <9155000>;
3912 opp-3 {
3913 opp-peak-kBps = <12298000>;
3916 opp-4 {
3917 opp-peak-kBps = <14236000>;
3920 opp-5 {
3921 opp-peak-kBps = <16265000>;
3927 compatible = "qcom,sm8550-gem-noc";
3929 #interconnect-cells = <2>;
3930 qcom,bcm-voters = <&apps_bcm_voter>;
3933 system-cache-controller@25000000 {
3934 compatible = "qcom,sm8550-llcc";
3940 reg-names = "llcc0_base",
3949 compatible = "qcom,sm8550-adsp-pas";
3952 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
3957 interrupt-names = "wdog", "fatal", "ready",
3958 "handover", "stop-ack";
3961 clock-names = "xo";
3963 power-domains = <&rpmhpd RPMHPD_LCX>,
3965 power-domain-names = "lcx", "lmx";
3969 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
3973 qcom,smem-states = <&smp2p_adsp_out 0>;
3974 qcom,smem-state-names = "stop";
3978 remoteproc_adsp_glink: glink-edge {
3979 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
3986 qcom,remote-pid = <2>;
3990 qcom,glink-channels = "fastrpcglink-apps-dsp";
3992 #address-cells = <1>;
3993 #size-cells = <0>;
3995 compute-cb@3 {
3996 compatible = "qcom,fastrpc-compute-cb";
4002 compute-cb@4 {
4003 compatible = "qcom,fastrpc-compute-cb";
4009 compute-cb@5 {
4010 compatible = "qcom,fastrpc-compute-cb";
4016 compute-cb@6 {
4017 compatible = "qcom,fastrpc-compute-cb";
4023 compute-cb@7 {
4024 compatible = "qcom,fastrpc-compute-cb";
4033 qcom,glink-channels = "adsp_apps";
4036 #address-cells = <1>;
4037 #size-cells = <0>;
4042 #sound-dai-cells = <0>;
4043 qcom,protection-domain = "avs/audio",
4047 compatible = "qcom,q6apm-dais";
4053 compatible = "qcom,q6apm-lpass-dais";
4054 #sound-dai-cells = <1>;
4061 qcom,protection-domain = "avs/audio",
4064 q6prmcc: clock-controller {
4065 compatible = "qcom,q6prm-lpass-clocks";
4066 #clock-cells = <2>;
4074 compatible = "qcom,sm8550-nsp-noc";
4076 #interconnect-cells = <2>;
4077 qcom,bcm-voters = <&apps_bcm_voter>;
4081 compatible = "qcom,sm8550-cdsp-pas";
4084 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4089 interrupt-names = "wdog", "fatal", "ready",
4090 "handover", "stop-ack";
4093 clock-names = "xo";
4095 power-domains = <&rpmhpd RPMHPD_CX>,
4098 power-domain-names = "cx", "mxc", "nsp";
4102 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4106 qcom,smem-states = <&smp2p_cdsp_out 0>;
4107 qcom,smem-state-names = "stop";
4111 glink-edge {
4112 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4119 qcom,remote-pid = <5>;
4123 qcom,glink-channels = "fastrpcglink-apps-dsp";
4125 #address-cells = <1>;
4126 #size-cells = <0>;
4128 compute-cb@1 {
4129 compatible = "qcom,fastrpc-compute-cb";
4136 compute-cb@2 {
4137 compatible = "qcom,fastrpc-compute-cb";
4144 compute-cb@3 {
4145 compatible = "qcom,fastrpc-compute-cb";
4152 compute-cb@4 {
4153 compatible = "qcom,fastrpc-compute-cb";
4160 compute-cb@5 {
4161 compatible = "qcom,fastrpc-compute-cb";
4168 compute-cb@6 {
4169 compatible = "qcom,fastrpc-compute-cb";
4176 compute-cb@7 {
4177 compatible = "qcom,fastrpc-compute-cb";
4184 compute-cb@8 {
4185 compatible = "qcom,fastrpc-compute-cb";
4198 thermal-zones {
4199 aoss0-thermal {
4200 polling-delay-passive = <0>;
4201 polling-delay = <0>;
4202 thermal-sensors = <&tsens0 0>;
4205 thermal-engine-config {
4211 reset-mon-config {
4219 cpuss0-thermal {
4220 polling-delay-passive = <0>;
4221 polling-delay = <0>;
4222 thermal-sensors = <&tsens0 1>;
4225 thermal-engine-config {
4231 reset-mon-config {
4239 cpuss1-thermal {
4240 polling-delay-passive = <0>;
4241 polling-delay = <0>;
4242 thermal-sensors = <&tsens0 2>;
4245 thermal-engine-config {
4251 reset-mon-config {
4259 cpuss2-thermal {
4260 polling-delay-passive = <0>;
4261 polling-delay = <0>;
4262 thermal-sensors = <&tsens0 3>;
4265 thermal-engine-config {
4271 reset-mon-config {
4279 cpuss3-thermal {
4280 polling-delay-passive = <0>;
4281 polling-delay = <0>;
4282 thermal-sensors = <&tsens0 4>;
4285 thermal-engine-config {
4291 reset-mon-config {
4299 cpu3-top-thermal {
4300 polling-delay-passive = <0>;
4301 polling-delay = <0>;
4302 thermal-sensors = <&tsens0 5>;
4305 cpu3_top_alert0: trip-point0 {
4311 cpu3_top_alert1: trip-point1 {
4317 cpu3_top_crit: cpu-critical {
4325 cpu3-bottom-thermal {
4326 polling-delay-passive = <0>;
4327 polling-delay = <0>;
4328 thermal-sensors = <&tsens0 6>;
4331 cpu3_bottom_alert0: trip-point0 {
4337 cpu3_bottom_alert1: trip-point1 {
4343 cpu3_bottom_crit: cpu-critical {
4351 cpu4-top-thermal {
4352 polling-delay-passive = <0>;
4353 polling-delay = <0>;
4354 thermal-sensors = <&tsens0 7>;
4357 cpu4_top_alert0: trip-point0 {
4363 cpu4_top_alert1: trip-point1 {
4369 cpu4_top_crit: cpu-critical {
4377 cpu4-bottom-thermal {
4378 polling-delay-passive = <0>;
4379 polling-delay = <0>;
4380 thermal-sensors = <&tsens0 8>;
4383 cpu4_bottom_alert0: trip-point0 {
4389 cpu4_bottom_alert1: trip-point1 {
4395 cpu4_bottom_crit: cpu-critical {
4403 cpu5-top-thermal {
4404 polling-delay-passive = <0>;
4405 polling-delay = <0>;
4406 thermal-sensors = <&tsens0 9>;
4409 cpu5_top_alert0: trip-point0 {
4415 cpu5_top_alert1: trip-point1 {
4421 cpu5_top_crit: cpu-critical {
4429 cpu5-bottom-thermal {
4430 polling-delay-passive = <0>;
4431 polling-delay = <0>;
4432 thermal-sensors = <&tsens0 10>;
4435 cpu5_bottom_alert0: trip-point0 {
4441 cpu5_bottom_alert1: trip-point1 {
4447 cpu5_bottom_crit: cpu-critical {
4455 cpu6-top-thermal {
4456 polling-delay-passive = <0>;
4457 polling-delay = <0>;
4458 thermal-sensors = <&tsens0 11>;
4461 cpu6_top_alert0: trip-point0 {
4467 cpu6_top_alert1: trip-point1 {
4473 cpu6_top_crit: cpu-critical {
4481 cpu6-bottom-thermal {
4482 polling-delay-passive = <0>;
4483 polling-delay = <0>;
4484 thermal-sensors = <&tsens0 12>;
4487 cpu6_bottom_alert0: trip-point0 {
4493 cpu6_bottom_alert1: trip-point1 {
4499 cpu6_bottom_crit: cpu-critical {
4507 cpu7-top-thermal {
4508 polling-delay-passive = <0>;
4509 polling-delay = <0>;
4510 thermal-sensors = <&tsens0 13>;
4513 cpu7_top_alert0: trip-point0 {
4519 cpu7_top_alert1: trip-point1 {
4525 cpu7_top_crit: cpu-critical {
4533 cpu7-middle-thermal {
4534 polling-delay-passive = <0>;
4535 polling-delay = <0>;
4536 thermal-sensors = <&tsens0 14>;
4539 cpu7_middle_alert0: trip-point0 {
4545 cpu7_middle_alert1: trip-point1 {
4551 cpu7_middle_crit: cpu-critical {
4559 cpu7-bottom-thermal {
4560 polling-delay-passive = <0>;
4561 polling-delay = <0>;
4562 thermal-sensors = <&tsens0 15>;
4565 cpu7_bottom_alert0: trip-point0 {
4571 cpu7_bottom_alert1: trip-point1 {
4577 cpu7_bottom_crit: cpu-critical {
4585 aoss1-thermal {
4586 polling-delay-passive = <0>;
4587 polling-delay = <0>;
4588 thermal-sensors = <&tsens1 0>;
4591 thermal-engine-config {
4597 reset-mon-config {
4605 cpu0-thermal {
4606 polling-delay-passive = <0>;
4607 polling-delay = <0>;
4608 thermal-sensors = <&tsens1 1>;
4611 cpu0_alert0: trip-point0 {
4617 cpu0_alert1: trip-point1 {
4623 cpu0_crit: cpu-critical {
4631 cpu1-thermal {
4632 polling-delay-passive = <0>;
4633 polling-delay = <0>;
4634 thermal-sensors = <&tsens1 2>;
4637 cpu1_alert0: trip-point0 {
4643 cpu1_alert1: trip-point1 {
4649 cpu1_crit: cpu-critical {
4657 cpu2-thermal {
4658 polling-delay-passive = <0>;
4659 polling-delay = <0>;
4660 thermal-sensors = <&tsens1 3>;
4663 cpu2_alert0: trip-point0 {
4669 cpu2_alert1: trip-point1 {
4675 cpu2_crit: cpu-critical {
4683 cdsp0-thermal {
4684 polling-delay-passive = <10>;
4685 polling-delay = <0>;
4686 thermal-sensors = <&tsens2 4>;
4689 thermal-engine-config {
4695 thermal-hal-config {
4701 reset-mon-config {
4707 cdsp0_junction_config: junction-config {
4715 cdsp1-thermal {
4716 polling-delay-passive = <10>;
4717 polling-delay = <0>;
4718 thermal-sensors = <&tsens2 5>;
4721 thermal-engine-config {
4727 thermal-hal-config {
4733 reset-mon-config {
4739 cdsp1_junction_config: junction-config {
4747 cdsp2-thermal {
4748 polling-delay-passive = <10>;
4749 polling-delay = <0>;
4750 thermal-sensors = <&tsens2 6>;
4753 thermal-engine-config {
4759 thermal-hal-config {
4765 reset-mon-config {
4771 cdsp2_junction_config: junction-config {
4779 cdsp3-thermal {
4780 polling-delay-passive = <10>;
4781 polling-delay = <0>;
4782 thermal-sensors = <&tsens2 7>;
4785 thermal-engine-config {
4791 thermal-hal-config {
4797 reset-mon-config {
4803 cdsp3_junction_config: junction-config {
4811 video-thermal {
4812 polling-delay-passive = <0>;
4813 polling-delay = <0>;
4814 thermal-sensors = <&tsens1 8>;
4817 thermal-engine-config {
4823 reset-mon-config {
4831 mem-thermal {
4832 polling-delay-passive = <10>;
4833 polling-delay = <0>;
4834 thermal-sensors = <&tsens1 9>;
4837 thermal-engine-config {
4843 ddr_config0: ddr0-config {
4849 reset-mon-config {
4857 modem0-thermal {
4858 polling-delay-passive = <0>;
4859 polling-delay = <0>;
4860 thermal-sensors = <&tsens1 10>;
4863 thermal-engine-config {
4869 mdmss0_config0: mdmss0-config0 {
4875 mdmss0_config1: mdmss0-config1 {
4881 reset-mon-config {
4889 modem1-thermal {
4890 polling-delay-passive = <0>;
4891 polling-delay = <0>;
4892 thermal-sensors = <&tsens1 11>;
4895 thermal-engine-config {
4901 mdmss1_config0: mdmss1-config0 {
4907 mdmss1_config1: mdmss1-config1 {
4913 reset-mon-config {
4921 modem2-thermal {
4922 polling-delay-passive = <0>;
4923 polling-delay = <0>;
4924 thermal-sensors = <&tsens1 12>;
4927 thermal-engine-config {
4933 mdmss2_config0: mdmss2-config0 {
4939 mdmss2_config1: mdmss2-config1 {
4945 reset-mon-config {
4953 modem3-thermal {
4954 polling-delay-passive = <0>;
4955 polling-delay = <0>;
4956 thermal-sensors = <&tsens1 13>;
4959 thermal-engine-config {
4965 mdmss3_config0: mdmss3-config0 {
4971 mdmss3_config1: mdmss3-config1 {
4977 reset-mon-config {
4985 camera0-thermal {
4986 polling-delay-passive = <0>;
4987 polling-delay = <0>;
4988 thermal-sensors = <&tsens1 14>;
4991 thermal-engine-config {
4997 reset-mon-config {
5005 camera1-thermal {
5006 polling-delay-passive = <0>;
5007 polling-delay = <0>;
5008 thermal-sensors = <&tsens1 15>;
5011 thermal-engine-config {
5017 reset-mon-config {
5025 aoss2-thermal {
5026 polling-delay-passive = <0>;
5027 polling-delay = <0>;
5028 thermal-sensors = <&tsens2 0>;
5031 thermal-engine-config {
5037 reset-mon-config {
5045 gpuss-0-thermal {
5046 polling-delay-passive = <10>;
5047 polling-delay = <0>;
5048 thermal-sensors = <&tsens2 1>;
5051 thermal-engine-config {
5057 thermal-hal-config {
5063 reset-mon-config {
5069 gpu0_junction_config: junction-config {
5077 gpuss-1-thermal {
5078 polling-delay-passive = <10>;
5079 polling-delay = <0>;
5080 thermal-sensors = <&tsens2 2>;
5083 thermal-engine-config {
5089 thermal-hal-config {
5095 reset-mon-config {
5101 gpu1_junction_config: junction-config {
5109 gpuss-2-thermal {
5110 polling-delay-passive = <10>;
5111 polling-delay = <0>;
5112 thermal-sensors = <&tsens2 3>;
5115 thermal-engine-config {
5121 thermal-hal-config {
5127 reset-mon-config {
5133 gpu2_junction_config: junction-config {
5141 gpuss-3-thermal {
5142 polling-delay-passive = <10>;
5143 polling-delay = <0>;
5144 thermal-sensors = <&tsens2 4>;
5147 thermal-engine-config {
5153 thermal-hal-config {
5159 reset-mon-config {
5165 gpu3_junction_config: junction-config {
5173 gpuss-4-thermal {
5174 polling-delay-passive = <10>;
5175 polling-delay = <0>;
5176 thermal-sensors = <&tsens2 5>;
5179 thermal-engine-config {
5185 thermal-hal-config {
5191 reset-mon-config {
5197 gpu4_junction_config: junction-config {
5205 gpuss-5-thermal {
5206 polling-delay-passive = <10>;
5207 polling-delay = <0>;
5208 thermal-sensors = <&tsens2 6>;
5211 thermal-engine-config {
5217 thermal-hal-config {
5223 reset-mon-config {
5229 gpu5_junction_config: junction-config {
5237 gpuss-6-thermal {
5238 polling-delay-passive = <10>;
5239 polling-delay = <0>;
5240 thermal-sensors = <&tsens2 7>;
5243 thermal-engine-config {
5249 thermal-hal-config {
5255 reset-mon-config {
5261 gpu6_junction_config: junction-config {
5269 gpuss-7-thermal {
5270 polling-delay-passive = <10>;
5271 polling-delay = <0>;
5272 thermal-sensors = <&tsens2 8>;
5275 thermal-engine-config {
5281 thermal-hal-config {
5287 reset-mon-config {
5293 gpu7_junction_config: junction-config {
5303 compatible = "arm,armv8-timer";