Lines Matching +full:0 +full:x40100000
36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0 0x100>;
100 clocks = <&cpufreq_hw 0>;
105 qcom,freq-domain = <&cpufreq_hw 0>;
120 reg = <0 0x200>;
121 clocks = <&cpufreq_hw 0>;
126 qcom,freq-domain = <&cpufreq_hw 0>;
141 reg = <0 0x300>;
162 reg = <0 0x400>;
183 reg = <0 0x500>;
204 reg = <0 0x600>;
225 reg = <0 0x700>;
282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
285 arm,psci-suspend-param = <0x40000004>;
292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
295 arm,psci-suspend-param = <0x40000004>;
304 CLUSTER_SLEEP_0: cluster-sleep-0 {
306 arm,psci-suspend-param = <0x41000044>;
314 arm,psci-suspend-param = <0x4100c344>;
325 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
329 clk_virt: interconnect-0 {
344 reg = <0 0xa0000000 0 0>;
357 #power-domain-cells = <0>;
363 #power-domain-cells = <0>;
369 #power-domain-cells = <0>;
375 #power-domain-cells = <0>;
381 #power-domain-cells = <0>;
387 #power-domain-cells = <0>;
393 #power-domain-cells = <0>;
399 #power-domain-cells = <0>;
405 #power-domain-cells = <0>;
416 reg = <0 0x80000000 0 0xa00000>;
421 reg = <0 0x80a00000 0 0x400000>;
426 reg = <0 0x80e00000 0 0x3d0000>;
431 reg = <0 0xd8100000 0 0x40000>;
436 reg = <0 0x811d0000 0 0x30000>;
442 reg = <0 0x81a00000 0 0x260000>;
448 reg = <0 0x81c60000 0 0x20000>;
454 reg = <0 0x81c80000 0 0x74000>;
461 reg = <0 0x81d00000 0 0x200000>;
467 reg = <0 0x81f00000 0 0x20000>;
472 reg = <0 0x82600000 0 0x100000>;
477 reg = <0 0x82700000 0 0x100000>;
482 reg = <0 0x82800000 0 0x4600000>;
487 reg = <0 0x8a800000 0 0x10800000>;
492 reg = <0 0x9b000000 0 0x80000>;
497 reg = <0 0x9b080000 0 0x10000>;
502 reg = <0 0x9b090000 0 0xa000>;
507 reg = <0 0x9b09a000 0 0x2000>;
512 reg = <0 0x9b100000 0 0x180000>;
518 reg = <0 0x9b280000 0 0x60000>;
524 reg = <0 0x9b2e0000 0 0x20000>;
529 reg = <0 0x9b300000 0 0x800000>;
534 reg = <0 0x9bb00000 0 0x700000>;
539 reg = <0 0x9c200000 0 0x700000>;
544 reg = <0 0x9c900000 0 0x2000000>;
549 reg = <0 0x9e900000 0 0x80000>;
554 reg = <0 0x9e980000 0 0x80000>;
559 reg = <0 0x9ea00000 0 0x4080000>;
565 /* Linux kernel image is loaded at 0xa8000000 */
569 reg = <0x0 0xd4a80000 0x0 0x280000>;
577 reg = <0 0xd4d00000 0 0x3300000>;
582 reg = <0 0xd8000000 0 0x100000>;
587 reg = <0 0xd8140000 0 0x1c0000>;
592 reg = <0 0xd8300000 0 0x500000>;
597 reg = <0 0xd8800000 0 0x8a00000>;
602 reg = <0 0xe1200000 0 0x2740000>;
607 reg = <0 0xe6440000 0 0x279000>;
612 reg = <0 0xf3600000 0 0x4aee000>;
617 reg = <0 0xf80ee000 0 0x1000>;
622 reg = <0 0xf80ef000 0 0x9000>;
627 reg = <0 0xf80f8000 0 0x4000>;
632 reg = <0 0xf80fc000 0 0x4000>;
637 reg = <0 0xf8100000 0 0x100000>;
642 reg = <0 0xf8400000 0 0x4800000>;
647 reg = <0 0xfcc00000 0 0x4000>;
652 reg = <0 0xfcc04000 0 0x100000>;
657 reg = <0 0xfce00000 0 0x2900000>;
662 reg = <0 0xff700000 0 0x100000>;
676 qcom,local-pid = <0>;
700 qcom,local-pid = <0>;
724 qcom,local-pid = <0>;
750 soc: soc@0 {
752 ranges = <0 0 0 0 0x10 0>;
753 dma-ranges = <0 0 0 0 0x10 0>;
760 reg = <0 0x00100000 0 0x1f4200>;
768 <&ufs_mem_phy 0>,
776 reg = <0 0x00408000 0 0x1000>;
786 reg = <0 0x00800000 0 0x60000>;
800 dma-channel-mask = <0x3e>;
801 iommus = <&apps_smmu 0x436 0>;
807 reg = <0 0x008c0000 0 0x2000>;
812 iommus = <&apps_smmu 0x423 0>;
819 reg = <0 0x00880000 0 0x4000>;
823 pinctrl-0 = <&qup_i2c8_data_clk>;
826 #size-cells = <0>;
827 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
828 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
829 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
831 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
832 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
839 reg = <0 0x00880000 0 0x4000>;
844 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
845 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
846 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
847 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
849 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
850 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
853 #size-cells = <0>;
859 reg = <0 0x00884000 0 0x4000>;
863 pinctrl-0 = <&qup_i2c9_data_clk>;
866 #size-cells = <0>;
867 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
868 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
869 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
871 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
879 reg = <0 0x00884000 0 0x4000>;
884 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
885 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
886 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
887 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
889 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
893 #size-cells = <0>;
899 reg = <0 0x00888000 0 0x4000>;
903 pinctrl-0 = <&qup_i2c10_data_clk>;
906 #size-cells = <0>;
907 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
908 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
909 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
911 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
919 reg = <0 0x00888000 0 0x4000>;
924 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
927 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
929 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
933 #size-cells = <0>;
939 reg = <0 0x0088c000 0 0x4000>;
943 pinctrl-0 = <&qup_i2c11_data_clk>;
946 #size-cells = <0>;
947 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
948 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
949 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
951 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
959 reg = <0 0x0088c000 0 0x4000>;
964 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
967 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
969 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
973 #size-cells = <0>;
979 reg = <0 0x00890000 0 0x4000>;
983 pinctrl-0 = <&qup_i2c12_data_clk>;
986 #size-cells = <0>;
987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
989 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
991 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
999 reg = <0 0x00890000 0 0x4000>;
1004 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1007 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1009 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1013 #size-cells = <0>;
1019 reg = <0 0x00894000 0 0x4000>;
1023 pinctrl-0 = <&qup_i2c13_data_clk>;
1026 #size-cells = <0>;
1027 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1028 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1029 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1031 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1039 reg = <0 0x00894000 0 0x4000>;
1044 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1045 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1047 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1049 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1053 #size-cells = <0>;
1059 reg = <0 0x0089c000 0 0x4000>;
1063 pinctrl-0 = <&qup_i2c15_data_clk>;
1066 #size-cells = <0>;
1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1069 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1071 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1079 reg = <0 0x0089c000 0 0x4000>;
1084 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1085 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1087 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1089 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1093 #size-cells = <0>;
1100 reg = <0x0 0x009c0000 0x0 0x2000>;
1110 reg = <0x0 0x00980000 0x0 0x4000>;
1115 pinctrl-0 = <&hub_i2c0_data_clk>;
1118 #size-cells = <0>;
1119 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1120 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1127 reg = <0x0 0x00984000 0x0 0x4000>;
1132 pinctrl-0 = <&hub_i2c1_data_clk>;
1135 #size-cells = <0>;
1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1137 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1144 reg = <0x0 0x00988000 0x0 0x4000>;
1149 pinctrl-0 = <&hub_i2c2_data_clk>;
1152 #size-cells = <0>;
1153 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1161 reg = <0x0 0x0098c000 0x0 0x4000>;
1166 pinctrl-0 = <&hub_i2c3_data_clk>;
1169 #size-cells = <0>;
1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1171 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1178 reg = <0x0 0x00990000 0x0 0x4000>;
1183 pinctrl-0 = <&hub_i2c4_data_clk>;
1186 #size-cells = <0>;
1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1188 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1195 reg = <0 0x00994000 0 0x4000>;
1200 pinctrl-0 = <&hub_i2c5_data_clk>;
1203 #size-cells = <0>;
1204 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1205 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1212 reg = <0 0x00998000 0 0x4000>;
1217 pinctrl-0 = <&hub_i2c6_data_clk>;
1220 #size-cells = <0>;
1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1229 reg = <0 0x0099c000 0 0x4000>;
1234 pinctrl-0 = <&hub_i2c7_data_clk>;
1237 #size-cells = <0>;
1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1239 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1246 reg = <0 0x009a0000 0 0x4000>;
1251 pinctrl-0 = <&hub_i2c8_data_clk>;
1254 #size-cells = <0>;
1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1256 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1263 reg = <0 0x009a4000 0 0x4000>;
1268 pinctrl-0 = <&hub_i2c9_data_clk>;
1271 #size-cells = <0>;
1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1282 reg = <0 0x00a00000 0 0x60000>;
1296 dma-channel-mask = <0x1e>;
1297 iommus = <&apps_smmu 0xb6 0>;
1303 reg = <0 0x00ac0000 0 0x2000>;
1308 iommus = <&apps_smmu 0xa3 0>;
1309 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1317 reg = <0 0x00a80000 0 0x4000>;
1321 pinctrl-0 = <&qup_i2c0_data_clk>;
1324 #size-cells = <0>;
1325 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1327 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1329 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1330 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1337 reg = <0 0x00a80000 0 0x4000>;
1342 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1344 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1345 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1347 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1348 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1351 #size-cells = <0>;
1357 reg = <0 0x00a84000 0 0x4000>;
1361 pinctrl-0 = <&qup_i2c1_data_clk>;
1364 #size-cells = <0>;
1365 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1366 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1367 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1369 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1377 reg = <0 0x00a84000 0 0x4000>;
1382 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1383 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1384 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1385 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1387 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1391 #size-cells = <0>;
1397 reg = <0 0x00a88000 0 0x4000>;
1401 pinctrl-0 = <&qup_i2c2_data_clk>;
1404 #size-cells = <0>;
1405 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1406 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1407 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1409 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1417 reg = <0 0x00a88000 0 0x4000>;
1422 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1423 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1424 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1425 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1427 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1431 #size-cells = <0>;
1437 reg = <0 0x00a8c000 0 0x4000>;
1441 pinctrl-0 = <&qup_i2c3_data_clk>;
1444 #size-cells = <0>;
1445 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1446 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1447 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1449 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1457 reg = <0 0x00a8c000 0 0x4000>;
1462 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1463 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1465 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1467 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1471 #size-cells = <0>;
1477 reg = <0 0x00a90000 0 0x4000>;
1481 pinctrl-0 = <&qup_i2c4_data_clk>;
1484 #size-cells = <0>;
1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1487 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1489 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1497 reg = <0 0x00a90000 0 0x4000>;
1502 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1504 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1505 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1507 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1511 #size-cells = <0>;
1517 reg = <0 0x00a94000 0 0x4000>;
1521 pinctrl-0 = <&qup_i2c5_data_clk>;
1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1524 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1525 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1527 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1531 #size-cells = <0>;
1537 reg = <0 0x00a94000 0 0x4000>;
1542 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1547 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1551 #size-cells = <0>;
1557 reg = <0 0x00a98000 0 0x4000>;
1561 pinctrl-0 = <&qup_i2c6_data_clk>;
1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1564 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1565 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1567 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1571 #size-cells = <0>;
1577 reg = <0 0x00a98000 0 0x4000>;
1582 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1584 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1585 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1587 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1591 #size-cells = <0>;
1597 reg = <0 0x00a9c000 0 0x4000>;
1601 pinctrl-0 = <&qup_uart7_default>;
1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1612 reg = <0 0x01500000 0 0x13080>;
1619 reg = <0 0x01600000 0 0x6200>;
1626 reg = <0 0x01680000 0 0x1d080>;
1633 reg = <0 0x016c0000 0 0x12200>;
1642 reg = <0 0x016e0000 0 0x14400>;
1651 reg = <0 0x01700000 0 0x1e400>;
1659 reg = <0 0x01780000 0 0x5b800>;
1667 reg = <0 0x01c00000 0 0x3000>,
1668 <0 0x60000000 0 0xf1d>,
1669 <0 0x60000f20 0 0xa8>,
1670 <0 0x60001000 0 0x1000>,
1671 <0 0x60100000 0 0x100000>;
1675 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1676 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1677 bus-range = <0x00 0xff>;
1681 linux,pci-domain = <0>;
1688 interrupt-map-mask = <0 0 0 0x7>;
1689 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1690 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1691 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1692 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1709 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1710 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1713 iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
1714 <0x100 &apps_smmu 0x1401 0x1>;
1729 reg = <0 0x01c06000 0 0x2000>;
1747 #clock-cells = <0>;
1750 #phy-cells = <0>;
1758 reg = <0x0 0x01c08000 0x0 0x3000>,
1759 <0x0 0x40000000 0x0 0xf1d>,
1760 <0x0 0x40000f20 0x0 0xa8>,
1761 <0x0 0x40001000 0x0 0x1000>,
1762 <0x0 0x40100000 0x0 0x100000>;
1766 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1767 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1768 bus-range = <0x00 0xff>;
1779 interrupt-map-mask = <0 0 0 0x7>;
1780 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1781 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1782 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1783 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1805 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1809 iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
1810 <0x100 &apps_smmu 0x1481 0x1>;
1826 reg = <0x0 0x01c0e000 0x0 0x2000>;
1845 #clock-cells = <0>;
1848 #phy-cells = <0>;
1855 reg = <0x0 0x01dc4000 0x0 0x28000>;
1858 qcom,ee = <0>;
1860 iommus = <&apps_smmu 0x480 0x0>,
1861 <&apps_smmu 0x481 0x0>;
1866 reg = <0x0 0x01dfa000 0x0 0x6000>;
1869 iommus = <&apps_smmu 0x480 0x0>,
1870 <&apps_smmu 0x481 0x0>;
1871 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1877 reg = <0x0 0x01d80000 0x0 0x2000>;
1884 resets = <&ufs_mem_hc 0>;
1888 #phy-cells = <0>;
1896 reg = <0x0 0x01d84000 0x0 0x3000>;
1908 iommus = <&apps_smmu 0x60 0x0>;
1911 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1912 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1933 <0 0>,
1934 <0 0>,
1937 <0 0>,
1938 <0 0>,
1939 <0 0>;
1948 reg = <0 0x01d88000 0 0x8000>;
1954 reg = <0 0x01f40000 0 0x20000>;
1960 reg = <0 0x01fc0000 0 0x30000>;
1968 reg = <0 0x03d90000 0 0xa000>;
1979 reg = <0x0 0x04080000 0x0 0x4040>;
1982 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1997 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2003 qcom,smem-states = <&smp2p_modem_out 0>;
2021 reg = <0 0x06aa0000 0 0x1000>;
2030 #clock-cells = <0>;
2033 pinctrl-0 = <&wsa2_swr_active>;
2039 reg = <0 0x06ab0000 0 0x10000>;
2048 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2049 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2050 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2051 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2052 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2053 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2054 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2055 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2056 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2059 #size-cells = <0>;
2066 reg = <0 0x06ac0000 0 0x1000>;
2076 #clock-cells = <0>;
2079 pinctrl-0 = <&rx_swr_active>;
2085 reg = <0 0x06ad0000 0 0x10000>;
2091 qcom,din-ports = <0>;
2094 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
2095 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
2096 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2097 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2098 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
2099 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>;
2100 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>;
2101 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>;
2102 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
2105 #size-cells = <0>;
2112 reg = <0 0x06ae0000 0 0x1000>;
2122 #clock-cells = <0>;
2125 pinctrl-0 = <&tx_swr_active>;
2131 reg = <0 0x06b00000 0 0x1000>;
2141 #clock-cells = <0>;
2144 pinctrl-0 = <&wsa_swr_active>;
2150 reg = <0 0x06b10000 0 0x10000>;
2159 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x…
2160 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2161 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2162 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2163 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2164 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
2165 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
2166 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2167 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
2170 #size-cells = <0>;
2177 reg = <0 0x06d30000 0 0x10000>;
2186 qcom,dout-ports = <0>;
2187 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2188 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2189 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2190 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2191 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2192 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2193 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2194 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2195 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2198 #size-cells = <0>;
2205 reg = <0 0x06d44000 0 0x1000>;
2214 #clock-cells = <0>;
2221 reg = <0 0x06e80000 0 0x20000>,
2222 <0 0x07250000 0 0x10000>;
2225 gpio-ranges = <&lpass_tlmm 0 0 23>;
2338 reg = <0 0x07400000 0 0x19080>;
2345 reg = <0 0x07430000 0 0x3a200>;
2352 reg = <0 0x07e40000 0 0xe080>;
2359 reg = <0 0x08804000 0 0x1000>;
2369 iommus = <&apps_smmu 0x540 0>;
2370 qcom,dll-config = <0x0007642c>;
2371 qcom,ddr-config = <0x80040868>;
2375 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2376 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2382 sdhci-caps-mask = <0x3 0>;
2413 reg = <0 0x0aaf0000 0 0x10000>;
2425 reg = <0 0x0ae00000 0 0x1000>;
2441 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2442 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2445 iommus = <&apps_smmu 0x1c00 0x2>;
2455 reg = <0 0x0ae01000 0 0x8f000>,
2456 <0 0x0aeb0000 0 0x2008>;
2460 interrupts = <0>;
2484 #size-cells = <0>;
2486 port@0 {
2487 reg = <0>;
2535 reg = <0 0xae90000 0 0x200>,
2536 <0 0xae90200 0 0x200>,
2537 <0 0xae90400 0 0xc00>,
2538 <0 0xae91000 0 0x400>,
2539 <0 0xae91400 0 0x400>;
2561 #sound-dai-cells = <0>;
2570 #size-cells = <0>;
2572 port@0 {
2573 reg = <0>;
2613 reg = <0 0x0ae94000 0 0x400>;
2636 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2645 #size-cells = <0>;
2651 #size-cells = <0>;
2653 port@0 {
2654 reg = <0>;
2689 reg = <0 0x0ae95000 0 0x200>,
2690 <0 0x0ae95200 0 0x280>,
2691 <0 0x0ae95500 0 0x400>;
2701 #phy-cells = <0>;
2708 reg = <0 0x0ae96000 0 0x400>;
2731 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2740 #size-cells = <0>;
2746 #size-cells = <0>;
2748 port@0 {
2749 reg = <0>;
2765 reg = <0 0x0ae97000 0 0x200>,
2766 <0 0x0ae97200 0 0x280>,
2767 <0 0x0ae97500 0 0x400>;
2777 #phy-cells = <0>;
2785 reg = <0 0x0af00000 0 0x20000>;
2790 <&mdss_dsi0_phy 0>,
2792 <&mdss_dsi1_phy 0>,
2796 <0>, /* dp1 */
2797 <0>,
2798 <0>, /* dp2 */
2799 <0>,
2800 <0>, /* dp3 */
2801 <0>;
2811 reg = <0x0 0x088e3000 0x0 0x154>;
2812 #phy-cells = <0>;
2824 reg = <0x0 0x088e8000 0x0 0x3000>;
2845 #size-cells = <0>;
2847 port@0 {
2848 reg = <0>;
2872 reg = <0x0 0x0a6f8800 0x0 0x400>;
2908 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2909 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2916 reg = <0x0 0x0a600000 0x0 0xcd00>;
2918 iommus = <&apps_smmu 0x40 0x0>;
2928 #size-cells = <0>;
2930 port@0 {
2931 reg = <0>;
2949 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
2950 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2960 reg = <0 0x0c271000 0 0x1000>, /* TM */
2961 <0 0x0c222000 0 0x1000>; /* SROT */
2971 reg = <0 0x0c272000 0 0x1000>, /* TM */
2972 <0 0x0c223000 0 0x1000>; /* SROT */
2982 reg = <0 0x0c273000 0 0x1000>, /* TM */
2983 <0 0x0c224000 0 0x1000>; /* SROT */
2993 reg = <0 0x0c300000 0 0x400>;
2999 #clock-cells = <0>;
3004 reg = <0 0x0c3f0000 0 0x400>;
3009 reg = <0 0x0c400000 0 0x3000>,
3010 <0 0x0c500000 0 0x4000000>,
3011 <0 0x0c440000 0 0x80000>,
3012 <0 0x0c4c0000 0 0x20000>,
3013 <0 0x0c42d000 0 0x4000>;
3017 qcom,ee = <0>;
3018 qcom,channel = <0>;
3019 qcom,bus-id = <0>;
3021 #size-cells = <0>;
3028 reg = <0 0x0f100000 0 0x300000>;
3034 gpio-ranges = <&tlmm 0 0 211>;
3544 reg = <0 0x15000000 0 0x100000>;
3648 reg = <0 0x17100000 0 0x10000>, /* GICD */
3649 <0 0x17180000 0 0x200000>; /* GICR * 8 */
3654 redistributor-stride = <0 0x40000>;
3661 reg = <0 0x17140000 0 0x20000>;
3669 reg = <0 0x17420000 0 0x1000>;
3670 ranges = <0 0 0 0x20000000>;
3675 reg = <0x17421000 0x1000>,
3676 <0x17422000 0x1000>;
3677 frame-number = <0>;
3683 reg = <0x17423000 0x1000>;
3690 reg = <0x17425000 0x1000>;
3697 reg = <0x17427000 0x1000>;
3704 reg = <0x17429000 0x1000>;
3711 reg = <0x1742b000 0x1000>;
3718 reg = <0x1742d000 0x1000>;
3728 reg = <0 0x17a00000 0 0x10000>,
3729 <0 0x17a10000 0 0x10000>,
3730 <0 0x17a20000 0 0x10000>,
3731 <0 0x17a30000 0 0x10000>;
3732 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3736 qcom,tcs-offset = <0xd00>;
3739 <WAKE_TCS 2>, <CONTROL_TCS 0>;
3826 reg = <0 0x17d91000 0 0x1000>,
3827 <0 0x17d92000 0 0x1000>,
3828 <0 0x17d93000 0 0x1000>;
3835 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
3842 reg = <0 0x24091000 0 0x1000>;
3851 opp-0 {
3891 reg = <0 0x240b6400 0 0x600>;
3900 opp-0 {
3928 reg = <0 0x24100000 0 0xbb800>;
3935 reg = <0 0x25000000 0 0x200000>,
3936 <0 0x25200000 0 0x200000>,
3937 <0 0x25400000 0 0x200000>,
3938 <0 0x25600000 0 0x200000>,
3939 <0 0x25800000 0 0x200000>;
3950 reg = <0x0 0x30000000 0x0 0x100>;
3953 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
3967 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
3973 qcom,smem-states = <&smp2p_adsp_out 0>;
3993 #size-cells = <0>;
3998 iommus = <&apps_smmu 0x1003 0x80>,
3999 <&apps_smmu 0x1063 0x0>;
4005 iommus = <&apps_smmu 0x1004 0x80>,
4006 <&apps_smmu 0x1064 0x0>;
4012 iommus = <&apps_smmu 0x1005 0x80>,
4013 <&apps_smmu 0x1065 0x0>;
4019 iommus = <&apps_smmu 0x1006 0x80>,
4020 <&apps_smmu 0x1066 0x0>;
4026 iommus = <&apps_smmu 0x1007 0x80>,
4027 <&apps_smmu 0x1067 0x0>;
4037 #size-cells = <0>;
4042 #sound-dai-cells = <0>;
4048 iommus = <&apps_smmu 0x1001 0x80>,
4049 <&apps_smmu 0x1061 0x0>;
4075 reg = <0 0x320c0000 0 0xe080>;
4082 reg = <0x0 0x32300000 0x0 0x1400000>;
4085 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4100 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4106 qcom,smem-states = <&smp2p_cdsp_out 0>;
4126 #size-cells = <0>;
4131 iommus = <&apps_smmu 0x1961 0x0>,
4132 <&apps_smmu 0x0c01 0x20>,
4133 <&apps_smmu 0x19c1 0x10>;
4139 iommus = <&apps_smmu 0x1962 0x0>,
4140 <&apps_smmu 0x0c02 0x20>,
4141 <&apps_smmu 0x19c2 0x10>;
4147 iommus = <&apps_smmu 0x1963 0x0>,
4148 <&apps_smmu 0x0c03 0x20>,
4149 <&apps_smmu 0x19c3 0x10>;
4155 iommus = <&apps_smmu 0x1964 0x0>,
4156 <&apps_smmu 0x0c04 0x20>,
4157 <&apps_smmu 0x19c4 0x10>;
4163 iommus = <&apps_smmu 0x1965 0x0>,
4164 <&apps_smmu 0x0c05 0x20>,
4165 <&apps_smmu 0x19c5 0x10>;
4171 iommus = <&apps_smmu 0x1966 0x0>,
4172 <&apps_smmu 0x0c06 0x20>,
4173 <&apps_smmu 0x19c6 0x10>;
4179 iommus = <&apps_smmu 0x1967 0x0>,
4180 <&apps_smmu 0x0c07 0x20>,
4181 <&apps_smmu 0x19c7 0x10>;
4187 iommus = <&apps_smmu 0x1968 0x0>,
4188 <&apps_smmu 0x0c08 0x20>,
4189 <&apps_smmu 0x19c8 0x10>;
4200 polling-delay-passive = <0>;
4201 polling-delay = <0>;
4202 thermal-sensors = <&tsens0 0>;
4220 polling-delay-passive = <0>;
4221 polling-delay = <0>;
4240 polling-delay-passive = <0>;
4241 polling-delay = <0>;
4260 polling-delay-passive = <0>;
4261 polling-delay = <0>;
4280 polling-delay-passive = <0>;
4281 polling-delay = <0>;
4300 polling-delay-passive = <0>;
4301 polling-delay = <0>;
4326 polling-delay-passive = <0>;
4327 polling-delay = <0>;
4352 polling-delay-passive = <0>;
4353 polling-delay = <0>;
4378 polling-delay-passive = <0>;
4379 polling-delay = <0>;
4404 polling-delay-passive = <0>;
4405 polling-delay = <0>;
4430 polling-delay-passive = <0>;
4431 polling-delay = <0>;
4456 polling-delay-passive = <0>;
4457 polling-delay = <0>;
4482 polling-delay-passive = <0>;
4483 polling-delay = <0>;
4508 polling-delay-passive = <0>;
4509 polling-delay = <0>;
4534 polling-delay-passive = <0>;
4535 polling-delay = <0>;
4560 polling-delay-passive = <0>;
4561 polling-delay = <0>;
4586 polling-delay-passive = <0>;
4587 polling-delay = <0>;
4588 thermal-sensors = <&tsens1 0>;
4606 polling-delay-passive = <0>;
4607 polling-delay = <0>;
4632 polling-delay-passive = <0>;
4633 polling-delay = <0>;
4658 polling-delay-passive = <0>;
4659 polling-delay = <0>;
4685 polling-delay = <0>;
4717 polling-delay = <0>;
4749 polling-delay = <0>;
4781 polling-delay = <0>;
4812 polling-delay-passive = <0>;
4813 polling-delay = <0>;
4833 polling-delay = <0>;
4858 polling-delay-passive = <0>;
4859 polling-delay = <0>;
4890 polling-delay-passive = <0>;
4891 polling-delay = <0>;
4922 polling-delay-passive = <0>;
4923 polling-delay = <0>;
4954 polling-delay-passive = <0>;
4955 polling-delay = <0>;
4986 polling-delay-passive = <0>;
4987 polling-delay = <0>;
5006 polling-delay-passive = <0>;
5007 polling-delay = <0>;
5026 polling-delay-passive = <0>;
5027 polling-delay = <0>;
5028 thermal-sensors = <&tsens2 0>;
5045 gpuss-0-thermal {
5047 polling-delay = <0>;
5079 polling-delay = <0>;
5111 polling-delay = <0>;
5143 polling-delay = <0>;
5175 polling-delay = <0>;
5207 polling-delay = <0>;
5239 polling-delay = <0>;
5271 polling-delay = <0>;