Lines Matching +full:dout +full:- +full:gpios
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h>
12 #include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8250.h>
17 #include <dt-bindings/mailbox/qcom-ipcc.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/power/qcom,rpmhpd.h>
20 #include <dt-bindings/soc/qcom,apr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6afe.h>
23 #include <dt-bindings/thermal/thermal.h>
24 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
25 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
28 interrupt-parent = <&intc>;
30 #address-cells = <2>;
31 #size-cells = <2>;
79 xo_board: xo-board {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <38400000>;
83 clock-output-names = "xo_board";
86 sleep_clk: sleep-clk {
87 compatible = "fixed-clock";
88 clock-frequency = <32768>;
89 #clock-cells = <0>;
94 #address-cells = <2>;
95 #size-cells = <0>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <448>;
104 dynamic-power-coefficient = <105>;
105 next-level-cache = <&L2_0>;
106 power-domains = <&CPU_PD0>;
107 power-domain-names = "psci";
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 #cooling-cells = <2>;
113 L2_0: l2-cache {
115 cache-level = <2>;
116 cache-size = <0x20000>;
117 cache-unified;
118 next-level-cache = <&L3_0>;
119 L3_0: l3-cache {
121 cache-level = <3>;
122 cache-size = <0x400000>;
123 cache-unified;
133 enable-method = "psci";
134 capacity-dmips-mhz = <448>;
135 dynamic-power-coefficient = <105>;
136 next-level-cache = <&L2_100>;
137 power-domains = <&CPU_PD1>;
138 power-domain-names = "psci";
139 qcom,freq-domain = <&cpufreq_hw 0>;
140 operating-points-v2 = <&cpu0_opp_table>;
143 #cooling-cells = <2>;
144 L2_100: l2-cache {
146 cache-level = <2>;
147 cache-size = <0x20000>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 capacity-dmips-mhz = <448>;
160 dynamic-power-coefficient = <105>;
161 next-level-cache = <&L2_200>;
162 power-domains = <&CPU_PD2>;
163 power-domain-names = "psci";
164 qcom,freq-domain = <&cpufreq_hw 0>;
165 operating-points-v2 = <&cpu0_opp_table>;
168 #cooling-cells = <2>;
169 L2_200: l2-cache {
171 cache-level = <2>;
172 cache-size = <0x20000>;
173 cache-unified;
174 next-level-cache = <&L3_0>;
183 enable-method = "psci";
184 capacity-dmips-mhz = <448>;
185 dynamic-power-coefficient = <105>;
186 next-level-cache = <&L2_300>;
187 power-domains = <&CPU_PD3>;
188 power-domain-names = "psci";
189 qcom,freq-domain = <&cpufreq_hw 0>;
190 operating-points-v2 = <&cpu0_opp_table>;
193 #cooling-cells = <2>;
194 L2_300: l2-cache {
196 cache-level = <2>;
197 cache-size = <0x20000>;
198 cache-unified;
199 next-level-cache = <&L3_0>;
208 enable-method = "psci";
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <379>;
211 next-level-cache = <&L2_400>;
212 power-domains = <&CPU_PD4>;
213 power-domain-names = "psci";
214 qcom,freq-domain = <&cpufreq_hw 1>;
215 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 L2_400: l2-cache {
221 cache-level = <2>;
222 cache-size = <0x40000>;
223 cache-unified;
224 next-level-cache = <&L3_0>;
233 enable-method = "psci";
234 capacity-dmips-mhz = <1024>;
235 dynamic-power-coefficient = <379>;
236 next-level-cache = <&L2_500>;
237 power-domains = <&CPU_PD5>;
238 power-domain-names = "psci";
239 qcom,freq-domain = <&cpufreq_hw 1>;
240 operating-points-v2 = <&cpu4_opp_table>;
243 #cooling-cells = <2>;
244 L2_500: l2-cache {
246 cache-level = <2>;
247 cache-size = <0x40000>;
248 cache-unified;
249 next-level-cache = <&L3_0>;
258 enable-method = "psci";
259 capacity-dmips-mhz = <1024>;
260 dynamic-power-coefficient = <379>;
261 next-level-cache = <&L2_600>;
262 power-domains = <&CPU_PD6>;
263 power-domain-names = "psci";
264 qcom,freq-domain = <&cpufreq_hw 1>;
265 operating-points-v2 = <&cpu4_opp_table>;
268 #cooling-cells = <2>;
269 L2_600: l2-cache {
271 cache-level = <2>;
272 cache-size = <0x40000>;
273 cache-unified;
274 next-level-cache = <&L3_0>;
283 enable-method = "psci";
284 capacity-dmips-mhz = <1024>;
285 dynamic-power-coefficient = <444>;
286 next-level-cache = <&L2_700>;
287 power-domains = <&CPU_PD7>;
288 power-domain-names = "psci";
289 qcom,freq-domain = <&cpufreq_hw 2>;
290 operating-points-v2 = <&cpu7_opp_table>;
293 #cooling-cells = <2>;
294 L2_700: l2-cache {
296 cache-level = <2>;
297 cache-size = <0x80000>;
298 cache-unified;
299 next-level-cache = <&L3_0>;
303 cpu-map {
339 idle-states {
340 entry-method = "psci";
342 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
343 compatible = "arm,idle-state";
344 idle-state-name = "silver-rail-power-collapse";
345 arm,psci-suspend-param = <0x40000004>;
346 entry-latency-us = <360>;
347 exit-latency-us = <531>;
348 min-residency-us = <3934>;
349 local-timer-stop;
352 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
353 compatible = "arm,idle-state";
354 idle-state-name = "gold-rail-power-collapse";
355 arm,psci-suspend-param = <0x40000004>;
356 entry-latency-us = <702>;
357 exit-latency-us = <1061>;
358 min-residency-us = <4488>;
359 local-timer-stop;
363 domain-idle-states {
364 CLUSTER_SLEEP_0: cluster-sleep-0 {
365 compatible = "domain-idle-state";
366 arm,psci-suspend-param = <0x4100c244>;
367 entry-latency-us = <3264>;
368 exit-latency-us = <6562>;
369 min-residency-us = <9987>;
374 cpu0_opp_table: opp-table-cpu0 {
375 compatible = "operating-points-v2";
376 opp-shared;
378 cpu0_opp1: opp-300000000 {
379 opp-hz = /bits/ 64 <300000000>;
380 opp-peak-kBps = <800000 9600000>;
383 cpu0_opp2: opp-403200000 {
384 opp-hz = /bits/ 64 <403200000>;
385 opp-peak-kBps = <800000 9600000>;
388 cpu0_opp3: opp-518400000 {
389 opp-hz = /bits/ 64 <518400000>;
390 opp-peak-kBps = <800000 16588800>;
393 cpu0_opp4: opp-614400000 {
394 opp-hz = /bits/ 64 <614400000>;
395 opp-peak-kBps = <800000 16588800>;
398 cpu0_opp5: opp-691200000 {
399 opp-hz = /bits/ 64 <691200000>;
400 opp-peak-kBps = <800000 19660800>;
403 cpu0_opp6: opp-787200000 {
404 opp-hz = /bits/ 64 <787200000>;
405 opp-peak-kBps = <1804000 19660800>;
408 cpu0_opp7: opp-883200000 {
409 opp-hz = /bits/ 64 <883200000>;
410 opp-peak-kBps = <1804000 23347200>;
413 cpu0_opp8: opp-979200000 {
414 opp-hz = /bits/ 64 <979200000>;
415 opp-peak-kBps = <1804000 26419200>;
418 cpu0_opp9: opp-1075200000 {
419 opp-hz = /bits/ 64 <1075200000>;
420 opp-peak-kBps = <1804000 29491200>;
423 cpu0_opp10: opp-1171200000 {
424 opp-hz = /bits/ 64 <1171200000>;
425 opp-peak-kBps = <1804000 32563200>;
428 cpu0_opp11: opp-1248000000 {
429 opp-hz = /bits/ 64 <1248000000>;
430 opp-peak-kBps = <1804000 36249600>;
433 cpu0_opp12: opp-1344000000 {
434 opp-hz = /bits/ 64 <1344000000>;
435 opp-peak-kBps = <2188000 36249600>;
438 cpu0_opp13: opp-1420800000 {
439 opp-hz = /bits/ 64 <1420800000>;
440 opp-peak-kBps = <2188000 39321600>;
443 cpu0_opp14: opp-1516800000 {
444 opp-hz = /bits/ 64 <1516800000>;
445 opp-peak-kBps = <3072000 42393600>;
448 cpu0_opp15: opp-1612800000 {
449 opp-hz = /bits/ 64 <1612800000>;
450 opp-peak-kBps = <3072000 42393600>;
453 cpu0_opp16: opp-1708800000 {
454 opp-hz = /bits/ 64 <1708800000>;
455 opp-peak-kBps = <4068000 42393600>;
458 cpu0_opp17: opp-1804800000 {
459 opp-hz = /bits/ 64 <1804800000>;
460 opp-peak-kBps = <4068000 42393600>;
464 cpu4_opp_table: opp-table-cpu4 {
465 compatible = "operating-points-v2";
466 opp-shared;
468 cpu4_opp1: opp-710400000 {
469 opp-hz = /bits/ 64 <710400000>;
470 opp-peak-kBps = <1804000 19660800>;
473 cpu4_opp2: opp-825600000 {
474 opp-hz = /bits/ 64 <825600000>;
475 opp-peak-kBps = <2188000 23347200>;
478 cpu4_opp3: opp-940800000 {
479 opp-hz = /bits/ 64 <940800000>;
480 opp-peak-kBps = <2188000 26419200>;
483 cpu4_opp4: opp-1056000000 {
484 opp-hz = /bits/ 64 <1056000000>;
485 opp-peak-kBps = <3072000 26419200>;
488 cpu4_opp5: opp-1171200000 {
489 opp-hz = /bits/ 64 <1171200000>;
490 opp-peak-kBps = <3072000 29491200>;
493 cpu4_opp6: opp-1286400000 {
494 opp-hz = /bits/ 64 <1286400000>;
495 opp-peak-kBps = <4068000 29491200>;
498 cpu4_opp7: opp-1382400000 {
499 opp-hz = /bits/ 64 <1382400000>;
500 opp-peak-kBps = <4068000 32563200>;
503 cpu4_opp8: opp-1478400000 {
504 opp-hz = /bits/ 64 <1478400000>;
505 opp-peak-kBps = <4068000 32563200>;
508 cpu4_opp9: opp-1574400000 {
509 opp-hz = /bits/ 64 <1574400000>;
510 opp-peak-kBps = <5412000 39321600>;
513 cpu4_opp10: opp-1670400000 {
514 opp-hz = /bits/ 64 <1670400000>;
515 opp-peak-kBps = <5412000 42393600>;
518 cpu4_opp11: opp-1766400000 {
519 opp-hz = /bits/ 64 <1766400000>;
520 opp-peak-kBps = <5412000 45465600>;
523 cpu4_opp12: opp-1862400000 {
524 opp-hz = /bits/ 64 <1862400000>;
525 opp-peak-kBps = <6220000 45465600>;
528 cpu4_opp13: opp-1958400000 {
529 opp-hz = /bits/ 64 <1958400000>;
530 opp-peak-kBps = <6220000 48537600>;
533 cpu4_opp14: opp-2054400000 {
534 opp-hz = /bits/ 64 <2054400000>;
535 opp-peak-kBps = <7216000 48537600>;
538 cpu4_opp15: opp-2150400000 {
539 opp-hz = /bits/ 64 <2150400000>;
540 opp-peak-kBps = <7216000 51609600>;
543 cpu4_opp16: opp-2246400000 {
544 opp-hz = /bits/ 64 <2246400000>;
545 opp-peak-kBps = <7216000 51609600>;
548 cpu4_opp17: opp-2342400000 {
549 opp-hz = /bits/ 64 <2342400000>;
550 opp-peak-kBps = <8368000 51609600>;
553 cpu4_opp18: opp-2419200000 {
554 opp-hz = /bits/ 64 <2419200000>;
555 opp-peak-kBps = <8368000 51609600>;
559 cpu7_opp_table: opp-table-cpu7 {
560 compatible = "operating-points-v2";
561 opp-shared;
563 cpu7_opp1: opp-844800000 {
564 opp-hz = /bits/ 64 <844800000>;
565 opp-peak-kBps = <2188000 19660800>;
568 cpu7_opp2: opp-960000000 {
569 opp-hz = /bits/ 64 <960000000>;
570 opp-peak-kBps = <2188000 26419200>;
573 cpu7_opp3: opp-1075200000 {
574 opp-hz = /bits/ 64 <1075200000>;
575 opp-peak-kBps = <3072000 26419200>;
578 cpu7_opp4: opp-1190400000 {
579 opp-hz = /bits/ 64 <1190400000>;
580 opp-peak-kBps = <3072000 29491200>;
583 cpu7_opp5: opp-1305600000 {
584 opp-hz = /bits/ 64 <1305600000>;
585 opp-peak-kBps = <4068000 32563200>;
588 cpu7_opp6: opp-1401600000 {
589 opp-hz = /bits/ 64 <1401600000>;
590 opp-peak-kBps = <4068000 32563200>;
593 cpu7_opp7: opp-1516800000 {
594 opp-hz = /bits/ 64 <1516800000>;
595 opp-peak-kBps = <4068000 36249600>;
598 cpu7_opp8: opp-1632000000 {
599 opp-hz = /bits/ 64 <1632000000>;
600 opp-peak-kBps = <5412000 39321600>;
603 cpu7_opp9: opp-1747200000 {
604 opp-hz = /bits/ 64 <1708800000>;
605 opp-peak-kBps = <5412000 42393600>;
608 cpu7_opp10: opp-1862400000 {
609 opp-hz = /bits/ 64 <1862400000>;
610 opp-peak-kBps = <6220000 45465600>;
613 cpu7_opp11: opp-1977600000 {
614 opp-hz = /bits/ 64 <1977600000>;
615 opp-peak-kBps = <6220000 48537600>;
618 cpu7_opp12: opp-2073600000 {
619 opp-hz = /bits/ 64 <2073600000>;
620 opp-peak-kBps = <7216000 48537600>;
623 cpu7_opp13: opp-2169600000 {
624 opp-hz = /bits/ 64 <2169600000>;
625 opp-peak-kBps = <7216000 51609600>;
628 cpu7_opp14: opp-2265600000 {
629 opp-hz = /bits/ 64 <2265600000>;
630 opp-peak-kBps = <7216000 51609600>;
633 cpu7_opp15: opp-2361600000 {
634 opp-hz = /bits/ 64 <2361600000>;
635 opp-peak-kBps = <8368000 51609600>;
638 cpu7_opp16: opp-2457600000 {
639 opp-hz = /bits/ 64 <2457600000>;
640 opp-peak-kBps = <8368000 51609600>;
643 cpu7_opp17: opp-2553600000 {
644 opp-hz = /bits/ 64 <2553600000>;
645 opp-peak-kBps = <8368000 51609600>;
648 cpu7_opp18: opp-2649600000 {
649 opp-hz = /bits/ 64 <2649600000>;
650 opp-peak-kBps = <8368000 51609600>;
653 cpu7_opp19: opp-2745600000 {
654 opp-hz = /bits/ 64 <2745600000>;
655 opp-peak-kBps = <8368000 51609600>;
658 cpu7_opp20: opp-2841600000 {
659 opp-hz = /bits/ 64 <2841600000>;
660 opp-peak-kBps = <8368000 51609600>;
666 compatible = "qcom,scm-sm8250", "qcom,scm";
667 #reset-cells = <1>;
678 compatible = "arm,armv8-pmuv3";
683 compatible = "arm,psci-1.0";
686 CPU_PD0: power-domain-cpu0 {
687 #power-domain-cells = <0>;
688 power-domains = <&CLUSTER_PD>;
689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
692 CPU_PD1: power-domain-cpu1 {
693 #power-domain-cells = <0>;
694 power-domains = <&CLUSTER_PD>;
695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
698 CPU_PD2: power-domain-cpu2 {
699 #power-domain-cells = <0>;
700 power-domains = <&CLUSTER_PD>;
701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
704 CPU_PD3: power-domain-cpu3 {
705 #power-domain-cells = <0>;
706 power-domains = <&CLUSTER_PD>;
707 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
710 CPU_PD4: power-domain-cpu4 {
711 #power-domain-cells = <0>;
712 power-domains = <&CLUSTER_PD>;
713 domain-idle-states = <&BIG_CPU_SLEEP_0>;
716 CPU_PD5: power-domain-cpu5 {
717 #power-domain-cells = <0>;
718 power-domains = <&CLUSTER_PD>;
719 domain-idle-states = <&BIG_CPU_SLEEP_0>;
722 CPU_PD6: power-domain-cpu6 {
723 #power-domain-cells = <0>;
724 power-domains = <&CLUSTER_PD>;
725 domain-idle-states = <&BIG_CPU_SLEEP_0>;
728 CPU_PD7: power-domain-cpu7 {
729 #power-domain-cells = <0>;
730 power-domains = <&CLUSTER_PD>;
731 domain-idle-states = <&BIG_CPU_SLEEP_0>;
734 CLUSTER_PD: power-domain-cpu-cluster0 {
735 #power-domain-cells = <0>;
736 domain-idle-states = <&CLUSTER_SLEEP_0>;
740 qup_opp_table: opp-table-qup {
741 compatible = "operating-points-v2";
743 opp-50000000 {
744 opp-hz = /bits/ 64 <50000000>;
745 required-opps = <&rpmhpd_opp_min_svs>;
748 opp-75000000 {
749 opp-hz = /bits/ 64 <75000000>;
750 required-opps = <&rpmhpd_opp_low_svs>;
753 opp-120000000 {
754 opp-hz = /bits/ 64 <120000000>;
755 required-opps = <&rpmhpd_opp_svs>;
759 reserved-memory {
760 #address-cells = <2>;
761 #size-cells = <2>;
766 no-map;
771 no-map;
775 compatible = "qcom,cmd-db";
777 no-map;
782 no-map;
787 no-map;
792 no-map;
797 no-map;
802 no-map;
807 no-map;
812 no-map;
817 no-map;
822 no-map;
827 no-map;
832 no-map;
837 no-map;
842 no-map;
847 no-map;
852 no-map;
858 memory-region = <&smem_mem>;
862 smp2p-adsp {
865 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
871 qcom,local-pid = <0>;
872 qcom,remote-pid = <2>;
874 smp2p_adsp_out: master-kernel {
875 qcom,entry-name = "master-kernel";
876 #qcom,smem-state-cells = <1>;
879 smp2p_adsp_in: slave-kernel {
880 qcom,entry-name = "slave-kernel";
881 interrupt-controller;
882 #interrupt-cells = <2>;
886 smp2p-cdsp {
889 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
895 qcom,local-pid = <0>;
896 qcom,remote-pid = <5>;
898 smp2p_cdsp_out: master-kernel {
899 qcom,entry-name = "master-kernel";
900 #qcom,smem-state-cells = <1>;
903 smp2p_cdsp_in: slave-kernel {
904 qcom,entry-name = "slave-kernel";
905 interrupt-controller;
906 #interrupt-cells = <2>;
910 smp2p-slpi {
913 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
919 qcom,local-pid = <0>;
920 qcom,remote-pid = <3>;
922 smp2p_slpi_out: master-kernel {
923 qcom,entry-name = "master-kernel";
924 #qcom,smem-state-cells = <1>;
927 smp2p_slpi_in: slave-kernel {
928 qcom,entry-name = "slave-kernel";
929 interrupt-controller;
930 #interrupt-cells = <2>;
935 #address-cells = <2>;
936 #size-cells = <2>;
938 dma-ranges = <0 0 0 0 0x10 0>;
939 compatible = "simple-bus";
941 gcc: clock-controller@100000 {
942 compatible = "qcom,gcc-sm8250";
944 #clock-cells = <1>;
945 #reset-cells = <1>;
946 #power-domain-cells = <1>;
947 clock-names = "bi_tcxo",
956 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
959 interrupt-controller;
960 #interrupt-cells = <3>;
961 #mbox-cells = <2>;
965 compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
967 #address-cells = <1>;
968 #size-cells = <1>;
977 compatible = "qcom,prng-ee";
980 clock-names = "core";
983 gpi_dma2: dma-controller@800000 {
984 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
996 dma-channels = <10>;
997 dma-channel-mask = <0x3f>;
999 #dma-cells = <3>;
1004 compatible = "qcom,geni-se-qup";
1006 clock-names = "m-ahb", "s-ahb";
1009 #address-cells = <2>;
1010 #size-cells = <2>;
1016 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c14_default>;
1025 dma-names = "tx", "rx";
1026 #address-cells = <1>;
1027 #size-cells = <0>;
1032 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1039 dma-names = "tx", "rx";
1040 power-domains = <&rpmhpd RPMHPD_CX>;
1041 operating-points-v2 = <&qup_opp_table>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1048 compatible = "qcom,geni-i2c";
1050 clock-names = "se";
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&qup_i2c15_default>;
1057 dma-names = "tx", "rx";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1064 compatible = "qcom,geni-spi";
1066 clock-names = "se";
1071 dma-names = "tx", "rx";
1072 power-domains = <&rpmhpd RPMHPD_CX>;
1073 operating-points-v2 = <&qup_opp_table>;
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1080 compatible = "qcom,geni-i2c";
1082 clock-names = "se";
1084 pinctrl-names = "default";
1085 pinctrl-0 = <&qup_i2c16_default>;
1089 dma-names = "tx", "rx";
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1096 compatible = "qcom,geni-spi";
1098 clock-names = "se";
1103 dma-names = "tx", "rx";
1104 power-domains = <&rpmhpd RPMHPD_CX>;
1105 operating-points-v2 = <&qup_opp_table>;
1106 #address-cells = <1>;
1107 #size-cells = <0>;
1112 compatible = "qcom,geni-i2c";
1114 clock-names = "se";
1116 pinctrl-names = "default";
1117 pinctrl-0 = <&qup_i2c17_default>;
1121 dma-names = "tx", "rx";
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-spi";
1130 clock-names = "se";
1135 dma-names = "tx", "rx";
1136 power-domains = <&rpmhpd RPMHPD_CX>;
1137 operating-points-v2 = <&qup_opp_table>;
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1144 compatible = "qcom,geni-uart";
1146 clock-names = "se";
1148 pinctrl-names = "default";
1149 pinctrl-0 = <&qup_uart17_default>;
1151 power-domains = <&rpmhpd RPMHPD_CX>;
1152 operating-points-v2 = <&qup_opp_table>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&qup_i2c18_default>;
1166 dma-names = "tx", "rx";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "qcom,geni-spi";
1175 clock-names = "se";
1180 dma-names = "tx", "rx";
1181 power-domains = <&rpmhpd RPMHPD_CX>;
1182 operating-points-v2 = <&qup_opp_table>;
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1189 compatible = "qcom,geni-uart";
1191 clock-names = "se";
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_uart18_default>;
1196 power-domains = <&rpmhpd RPMHPD_CX>;
1197 operating-points-v2 = <&qup_opp_table>;
1202 compatible = "qcom,geni-i2c";
1204 clock-names = "se";
1206 pinctrl-names = "default";
1207 pinctrl-0 = <&qup_i2c19_default>;
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "qcom,geni-spi";
1220 clock-names = "se";
1225 dma-names = "tx", "rx";
1226 power-domains = <&rpmhpd RPMHPD_CX>;
1227 operating-points-v2 = <&qup_opp_table>;
1228 #address-cells = <1>;
1229 #size-cells = <0>;
1234 gpi_dma0: dma-controller@900000 {
1235 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1250 dma-channels = <15>;
1251 dma-channel-mask = <0x7ff>;
1253 #dma-cells = <3>;
1258 compatible = "qcom,geni-se-qup";
1260 clock-names = "m-ahb", "s-ahb";
1263 #address-cells = <2>;
1264 #size-cells = <2>;
1270 compatible = "qcom,geni-i2c";
1272 clock-names = "se";
1274 pinctrl-names = "default";
1275 pinctrl-0 = <&qup_i2c0_default>;
1279 dma-names = "tx", "rx";
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1286 compatible = "qcom,geni-spi";
1288 clock-names = "se";
1293 dma-names = "tx", "rx";
1294 power-domains = <&rpmhpd RPMHPD_CX>;
1295 operating-points-v2 = <&qup_opp_table>;
1296 #address-cells = <1>;
1297 #size-cells = <0>;
1302 compatible = "qcom,geni-i2c";
1304 clock-names = "se";
1306 pinctrl-names = "default";
1307 pinctrl-0 = <&qup_i2c1_default>;
1311 dma-names = "tx", "rx";
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1318 compatible = "qcom,geni-spi";
1320 clock-names = "se";
1325 dma-names = "tx", "rx";
1326 power-domains = <&rpmhpd RPMHPD_CX>;
1327 operating-points-v2 = <&qup_opp_table>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "qcom,geni-i2c";
1336 clock-names = "se";
1338 pinctrl-names = "default";
1339 pinctrl-0 = <&qup_i2c2_default>;
1343 dma-names = "tx", "rx";
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1350 compatible = "qcom,geni-spi";
1352 clock-names = "se";
1357 dma-names = "tx", "rx";
1358 power-domains = <&rpmhpd RPMHPD_CX>;
1359 operating-points-v2 = <&qup_opp_table>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1366 compatible = "qcom,geni-debug-uart";
1368 clock-names = "se";
1370 pinctrl-names = "default";
1371 pinctrl-0 = <&qup_uart2_default>;
1373 power-domains = <&rpmhpd RPMHPD_CX>;
1374 operating-points-v2 = <&qup_opp_table>;
1379 compatible = "qcom,geni-i2c";
1381 clock-names = "se";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&qup_i2c3_default>;
1388 dma-names = "tx", "rx";
1389 #address-cells = <1>;
1390 #size-cells = <0>;
1395 compatible = "qcom,geni-spi";
1397 clock-names = "se";
1402 dma-names = "tx", "rx";
1403 power-domains = <&rpmhpd RPMHPD_CX>;
1404 operating-points-v2 = <&qup_opp_table>;
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1411 compatible = "qcom,geni-i2c";
1413 clock-names = "se";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_i2c4_default>;
1420 dma-names = "tx", "rx";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1427 compatible = "qcom,geni-spi";
1429 clock-names = "se";
1434 dma-names = "tx", "rx";
1435 power-domains = <&rpmhpd RPMHPD_CX>;
1436 operating-points-v2 = <&qup_opp_table>;
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1443 compatible = "qcom,geni-i2c";
1445 clock-names = "se";
1447 pinctrl-names = "default";
1448 pinctrl-0 = <&qup_i2c5_default>;
1452 dma-names = "tx", "rx";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1459 compatible = "qcom,geni-spi";
1461 clock-names = "se";
1466 dma-names = "tx", "rx";
1467 power-domains = <&rpmhpd RPMHPD_CX>;
1468 operating-points-v2 = <&qup_opp_table>;
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1475 compatible = "qcom,geni-i2c";
1477 clock-names = "se";
1479 pinctrl-names = "default";
1480 pinctrl-0 = <&qup_i2c6_default>;
1484 dma-names = "tx", "rx";
1485 #address-cells = <1>;
1486 #size-cells = <0>;
1491 compatible = "qcom,geni-spi";
1493 clock-names = "se";
1498 dma-names = "tx", "rx";
1499 power-domains = <&rpmhpd RPMHPD_CX>;
1500 operating-points-v2 = <&qup_opp_table>;
1501 #address-cells = <1>;
1502 #size-cells = <0>;
1507 compatible = "qcom,geni-uart";
1509 clock-names = "se";
1511 pinctrl-names = "default";
1512 pinctrl-0 = <&qup_uart6_default>;
1514 power-domains = <&rpmhpd RPMHPD_CX>;
1515 operating-points-v2 = <&qup_opp_table>;
1520 compatible = "qcom,geni-i2c";
1522 clock-names = "se";
1524 pinctrl-names = "default";
1525 pinctrl-0 = <&qup_i2c7_default>;
1529 dma-names = "tx", "rx";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1536 compatible = "qcom,geni-spi";
1538 clock-names = "se";
1543 dma-names = "tx", "rx";
1544 power-domains = <&rpmhpd RPMHPD_CX>;
1545 operating-points-v2 = <&qup_opp_table>;
1546 #address-cells = <1>;
1547 #size-cells = <0>;
1552 gpi_dma1: dma-controller@a00000 {
1553 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma";
1565 dma-channels = <10>;
1566 dma-channel-mask = <0x3f>;
1568 #dma-cells = <3>;
1573 compatible = "qcom,geni-se-qup";
1575 clock-names = "m-ahb", "s-ahb";
1578 #address-cells = <2>;
1579 #size-cells = <2>;
1585 compatible = "qcom,geni-i2c";
1587 clock-names = "se";
1589 pinctrl-names = "default";
1590 pinctrl-0 = <&qup_i2c8_default>;
1594 dma-names = "tx", "rx";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1601 compatible = "qcom,geni-spi";
1603 clock-names = "se";
1608 dma-names = "tx", "rx";
1609 power-domains = <&rpmhpd RPMHPD_CX>;
1610 operating-points-v2 = <&qup_opp_table>;
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1617 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c9_default>;
1626 dma-names = "tx", "rx";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1633 compatible = "qcom,geni-spi";
1635 clock-names = "se";
1640 dma-names = "tx", "rx";
1641 power-domains = <&rpmhpd RPMHPD_CX>;
1642 operating-points-v2 = <&qup_opp_table>;
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1649 compatible = "qcom,geni-i2c";
1651 clock-names = "se";
1653 pinctrl-names = "default";
1654 pinctrl-0 = <&qup_i2c10_default>;
1658 dma-names = "tx", "rx";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1665 compatible = "qcom,geni-spi";
1667 clock-names = "se";
1672 dma-names = "tx", "rx";
1673 power-domains = <&rpmhpd RPMHPD_CX>;
1674 operating-points-v2 = <&qup_opp_table>;
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1681 compatible = "qcom,geni-i2c";
1683 clock-names = "se";
1685 pinctrl-names = "default";
1686 pinctrl-0 = <&qup_i2c11_default>;
1690 dma-names = "tx", "rx";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1697 compatible = "qcom,geni-spi";
1699 clock-names = "se";
1704 dma-names = "tx", "rx";
1705 power-domains = <&rpmhpd RPMHPD_CX>;
1706 operating-points-v2 = <&qup_opp_table>;
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1713 compatible = "qcom,geni-i2c";
1715 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_i2c12_default>;
1722 dma-names = "tx", "rx";
1723 #address-cells = <1>;
1724 #size-cells = <0>;
1729 compatible = "qcom,geni-spi";
1731 clock-names = "se";
1736 dma-names = "tx", "rx";
1737 power-domains = <&rpmhpd RPMHPD_CX>;
1738 operating-points-v2 = <&qup_opp_table>;
1739 #address-cells = <1>;
1740 #size-cells = <0>;
1745 compatible = "qcom,geni-debug-uart";
1747 clock-names = "se";
1749 pinctrl-names = "default";
1750 pinctrl-0 = <&qup_uart12_default>;
1752 power-domains = <&rpmhpd RPMHPD_CX>;
1753 operating-points-v2 = <&qup_opp_table>;
1758 compatible = "qcom,geni-i2c";
1760 clock-names = "se";
1762 pinctrl-names = "default";
1763 pinctrl-0 = <&qup_i2c13_default>;
1767 dma-names = "tx", "rx";
1768 #address-cells = <1>;
1769 #size-cells = <0>;
1774 compatible = "qcom,geni-spi";
1776 clock-names = "se";
1781 dma-names = "tx", "rx";
1782 power-domains = <&rpmhpd RPMHPD_CX>;
1783 operating-points-v2 = <&qup_opp_table>;
1784 #address-cells = <1>;
1785 #size-cells = <0>;
1791 compatible = "qcom,sm8250-config-noc";
1793 #interconnect-cells = <2>;
1794 qcom,bcm-voters = <&apps_bcm_voter>;
1798 compatible = "qcom,sm8250-system-noc";
1800 #interconnect-cells = <2>;
1801 qcom,bcm-voters = <&apps_bcm_voter>;
1805 compatible = "qcom,sm8250-mc-virt";
1807 #interconnect-cells = <2>;
1808 qcom,bcm-voters = <&apps_bcm_voter>;
1812 compatible = "qcom,sm8250-aggre1-noc";
1814 #interconnect-cells = <2>;
1815 qcom,bcm-voters = <&apps_bcm_voter>;
1819 compatible = "qcom,sm8250-aggre2-noc";
1821 #interconnect-cells = <2>;
1822 qcom,bcm-voters = <&apps_bcm_voter>;
1826 compatible = "qcom,sm8250-compute-noc";
1828 #interconnect-cells = <2>;
1829 qcom,bcm-voters = <&apps_bcm_voter>;
1833 compatible = "qcom,sm8250-mmss-noc";
1835 #interconnect-cells = <2>;
1836 qcom,bcm-voters = <&apps_bcm_voter>;
1840 compatible = "qcom,pcie-sm8250";
1847 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1849 linux,pci-domain = <0>;
1850 bus-range = <0x00 0xff>;
1851 num-lanes = <1>;
1853 #address-cells = <3>;
1854 #size-cells = <2>;
1867 interrupt-names = "msi0", "msi1", "msi2", "msi3",
1869 #interrupt-cells = <1>;
1870 interrupt-map-mask = <0 0 0 0x7>;
1871 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1884 clock-names = "pipe",
1893 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1897 reset-names = "pci";
1899 power-domains = <&gcc PCIE_0_GDSC>;
1902 phy-names = "pciephy";
1904 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
1905 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
1907 pinctrl-names = "default";
1908 pinctrl-0 = <&pcie0_default_state>;
1909 dma-coherent;
1915 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy";
1917 #address-cells = <2>;
1918 #size-cells = <2>;
1924 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1927 reset-names = "phy";
1929 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1930 assigned-clock-rates = <100000000>;
1940 clock-names = "pipe0";
1942 #phy-cells = <0>;
1944 #clock-cells = <0>;
1945 clock-output-names = "pcie_0_pipe_clk";
1950 compatible = "qcom,pcie-sm8250";
1957 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1959 linux,pci-domain = <1>;
1960 bus-range = <0x00 0xff>;
1961 num-lanes = <2>;
1963 #address-cells = <3>;
1964 #size-cells = <2>;
1970 interrupt-names = "msi";
1971 #interrupt-cells = <1>;
1972 interrupt-map-mask = <0 0 0 0x7>;
1973 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1987 clock-names = "pipe",
1997 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1998 assigned-clock-rates = <19200000>;
2000 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2004 reset-names = "pci";
2006 power-domains = <&gcc PCIE_1_GDSC>;
2009 phy-names = "pciephy";
2011 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
2012 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
2014 pinctrl-names = "default";
2015 pinctrl-0 = <&pcie1_default_state>;
2016 dma-coherent;
2022 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2024 #address-cells = <2>;
2025 #size-cells = <2>;
2031 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2034 reset-names = "phy";
2036 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2037 assigned-clock-rates = <100000000>;
2049 clock-names = "pipe0";
2051 #phy-cells = <0>;
2053 #clock-cells = <0>;
2054 clock-output-names = "pcie_1_pipe_clk";
2059 compatible = "qcom,pcie-sm8250";
2066 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2068 linux,pci-domain = <2>;
2069 bus-range = <0x00 0xff>;
2070 num-lanes = <2>;
2072 #address-cells = <3>;
2073 #size-cells = <2>;
2079 interrupt-names = "msi";
2080 #interrupt-cells = <1>;
2081 interrupt-map-mask = <0 0 0 0x7>;
2082 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2096 clock-names = "pipe",
2106 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2107 assigned-clock-rates = <19200000>;
2109 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2113 reset-names = "pci";
2115 power-domains = <&gcc PCIE_2_GDSC>;
2118 phy-names = "pciephy";
2120 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
2121 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
2123 pinctrl-names = "default";
2124 pinctrl-0 = <&pcie2_default_state>;
2125 dma-coherent;
2131 compatible = "qcom,sm8250-qmp-modem-pcie-phy";
2133 #address-cells = <2>;
2134 #size-cells = <2>;
2140 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2143 reset-names = "phy";
2145 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2146 assigned-clock-rates = <100000000>;
2158 clock-names = "pipe0";
2160 #phy-cells = <0>;
2162 #clock-cells = <0>;
2163 clock-output-names = "pcie_2_pipe_clk";
2168 compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
2169 "jedec,ufs-2.0";
2173 phy-names = "ufsphy";
2174 lanes-per-direction = <2>;
2175 #reset-cells = <1>;
2177 reset-names = "rst";
2179 power-domains = <&gcc UFS_PHY_GDSC>;
2183 clock-names =
2201 freq-table-hz =
2213 interconnect-names = "ufs-ddr", "cpu-ufs";
2219 compatible = "qcom,sm8250-qmp-ufs-phy";
2221 #address-cells = <2>;
2222 #size-cells = <2>;
2224 clock-names = "ref",
2230 reset-names = "ufsphy";
2239 #phy-cells = <0>;
2243 cryptobam: dma-controller@1dc4000 {
2244 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2247 #dma-cells = <1>;
2249 qcom,controlled-remotely;
2250 num-channels = <8>;
2251 qcom,num-ees = <2>;
2261 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce";
2264 dma-names = "rx", "tx";
2272 interconnect-names = "memory";
2276 compatible = "qcom,tcsr-mutex";
2278 #hwlock-cells = <1>;
2282 compatible = "qcom,sm8250-lpass-wsa-macro";
2291 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen";
2293 #clock-cells = <0>;
2294 clock-output-names = "mclk";
2295 #sound-dai-cells = <1>;
2297 pinctrl-names = "default";
2298 pinctrl-0 = <&wsa_swr_active>;
2303 swr0: soundwire-controller@3250000 {
2305 compatible = "qcom,soundwire-v1.5.1";
2308 clock-names = "iface";
2310 qcom,din-ports = <2>;
2311 qcom,dout-ports = <6>;
2313 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2314 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2315 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2316 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2318 #sound-dai-cells = <1>;
2319 #address-cells = <2>;
2320 #size-cells = <0>;
2325 audiocc: clock-controller@3300000 {
2326 compatible = "qcom,sm8250-lpass-audiocc";
2328 #clock-cells = <1>;
2332 clock-names = "core", "audio", "bus";
2336 compatible = "qcom,sm8250-lpass-va-macro";
2342 clock-names = "mclk", "macro", "dcodec";
2344 #clock-cells = <0>;
2345 clock-output-names = "fsgen";
2346 #sound-dai-cells = <1>;
2350 pinctrl-names = "default";
2351 pinctrl-0 = <&rx_swr_active>;
2352 compatible = "qcom,sm8250-lpass-rx-macro";
2362 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2364 #clock-cells = <0>;
2365 clock-output-names = "mclk";
2366 #sound-dai-cells = <1>;
2369 swr1: soundwire-controller@3210000 {
2371 compatible = "qcom,soundwire-v1.5.1";
2375 clock-names = "iface";
2377 qcom,din-ports = <0>;
2378 qcom,dout-ports = <5>;
2380 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2381 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2382 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2383 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2384 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2385 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2386 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2387 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2388 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2390 #sound-dai-cells = <1>;
2391 #address-cells = <2>;
2392 #size-cells = <0>;
2396 pinctrl-names = "default";
2397 pinctrl-0 = <&tx_swr_active>;
2398 compatible = "qcom,sm8250-lpass-tx-macro";
2408 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2410 #clock-cells = <0>;
2411 clock-output-names = "mclk";
2412 #sound-dai-cells = <1>;
2416 swr2: soundwire-controller@3230000 {
2418 compatible = "qcom,soundwire-v1.5.1";
2420 interrupt-names = "core";
2424 clock-names = "iface";
2427 qcom,din-ports = <5>;
2428 qcom,dout-ports = <0>;
2429 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2430 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2431 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2432 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2433 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2434 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2435 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2436 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2437 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2438 #sound-dai-cells = <1>;
2439 #address-cells = <2>;
2440 #size-cells = <0>;
2443 aoncc: clock-controller@3380000 {
2444 compatible = "qcom,sm8250-lpass-aoncc";
2446 #clock-cells = <1>;
2450 clock-names = "core", "audio", "bus";
2454 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
2457 gpio-controller;
2458 #gpio-cells = <2>;
2459 gpio-ranges = <&lpass_tlmm 0 0 14>;
2463 clock-names = "core", "audio";
2465 wsa_swr_active: wsa-swr-active-state {
2466 clk-pins {
2469 drive-strength = <2>;
2470 slew-rate = <1>;
2471 bias-disable;
2474 data-pins {
2477 drive-strength = <2>;
2478 slew-rate = <1>;
2479 bias-bus-hold;
2483 wsa_swr_sleep: wsa-swr-sleep-state {
2484 clk-pins {
2487 drive-strength = <2>;
2488 bias-pull-down;
2491 data-pins {
2494 drive-strength = <2>;
2495 bias-pull-down;
2499 dmic01_active: dmic01-active-state {
2500 clk-pins {
2503 drive-strength = <8>;
2504 output-high;
2506 data-pins {
2509 drive-strength = <8>;
2513 dmic01_sleep: dmic01-sleep-state {
2514 clk-pins {
2517 drive-strength = <2>;
2518 bias-disable;
2519 output-low;
2522 data-pins {
2525 drive-strength = <2>;
2526 bias-pull-down;
2530 rx_swr_active: rx-swr-active-state {
2531 clk-pins {
2534 drive-strength = <2>;
2535 slew-rate = <1>;
2536 bias-disable;
2539 data-pins {
2542 drive-strength = <2>;
2543 slew-rate = <1>;
2544 bias-bus-hold;
2548 tx_swr_active: tx-swr-active-state {
2549 clk-pins {
2552 drive-strength = <2>;
2553 slew-rate = <1>;
2554 bias-disable;
2557 data-pins {
2560 drive-strength = <2>;
2561 slew-rate = <1>;
2562 bias-bus-hold;
2566 tx_swr_sleep: tx-swr-sleep-state {
2567 clk-pins {
2570 drive-strength = <2>;
2571 bias-pull-down;
2574 data1-pins {
2577 drive-strength = <2>;
2578 bias-bus-hold;
2581 data2-pins {
2584 drive-strength = <2>;
2585 bias-pull-down;
2591 compatible = "qcom,adreno-650.2",
2595 reg-names = "kgsl_3d0_reg_memory";
2601 operating-points-v2 = <&gpu_opp_table>;
2605 nvmem-cells = <&gpu_speed_bin>;
2606 nvmem-cell-names = "speed_bin";
2610 zap-shader {
2611 memory-region = <&gpu_mem>;
2614 gpu_opp_table: opp-table {
2615 compatible = "operating-points-v2";
2617 opp-670000000 {
2618 opp-hz = /bits/ 64 <670000000>;
2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2620 opp-supported-hw = <0xa>;
2623 opp-587000000 {
2624 opp-hz = /bits/ 64 <587000000>;
2625 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2626 opp-supported-hw = <0xb>;
2629 opp-525000000 {
2630 opp-hz = /bits/ 64 <525000000>;
2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2632 opp-supported-hw = <0xf>;
2635 opp-490000000 {
2636 opp-hz = /bits/ 64 <490000000>;
2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2638 opp-supported-hw = <0xf>;
2641 opp-441600000 {
2642 opp-hz = /bits/ 64 <441600000>;
2643 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2644 opp-supported-hw = <0xf>;
2647 opp-400000000 {
2648 opp-hz = /bits/ 64 <400000000>;
2649 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2650 opp-supported-hw = <0xf>;
2653 opp-305000000 {
2654 opp-hz = /bits/ 64 <305000000>;
2655 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2656 opp-supported-hw = <0xf>;
2662 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2668 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2672 interrupt-names = "hfi", "gmu";
2679 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2681 power-domains = <&gpucc GPU_CX_GDSC>,
2683 power-domain-names = "cx", "gx";
2687 operating-points-v2 = <&gmu_opp_table>;
2691 gmu_opp_table: opp-table {
2692 compatible = "operating-points-v2";
2694 opp-200000000 {
2695 opp-hz = /bits/ 64 <200000000>;
2696 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2701 gpucc: clock-controller@3d90000 {
2702 compatible = "qcom,sm8250-gpucc";
2707 clock-names = "bi_tcxo",
2710 #clock-cells = <1>;
2711 #reset-cells = <1>;
2712 #power-domain-cells = <1>;
2716 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu",
2717 "qcom,smmu-500", "arm,mmu-500";
2719 #iommu-cells = <2>;
2720 #global-interrupts = <2>;
2734 clock-names = "ahb", "bus", "iface";
2736 power-domains = <&gpucc GPU_CX_GDSC>;
2737 dma-coherent;
2741 compatible = "qcom,sm8250-slpi-pas";
2744 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2749 interrupt-names = "wdog", "fatal", "ready",
2750 "handover", "stop-ack";
2753 clock-names = "xo";
2755 power-domains = <&rpmhpd RPMHPD_LCX>,
2757 power-domain-names = "lcx", "lmx";
2759 memory-region = <&slpi_mem>;
2763 qcom,smem-states = <&smp2p_slpi_out 0>;
2764 qcom,smem-state-names = "stop";
2768 glink-edge {
2769 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2776 qcom,remote-pid = <3>;
2780 qcom,glink-channels = "fastrpcglink-apps-dsp";
2782 qcom,non-secure-domain;
2783 #address-cells = <1>;
2784 #size-cells = <0>;
2786 compute-cb@1 {
2787 compatible = "qcom,fastrpc-compute-cb";
2792 compute-cb@2 {
2793 compatible = "qcom,fastrpc-compute-cb";
2798 compute-cb@3 {
2799 compatible = "qcom,fastrpc-compute-cb";
2802 /* note: shared-cb = <4> in downstream */
2809 compatible = "arm,coresight-stm", "arm,primecell";
2811 reg-names = "stm-base", "stm-stimulus-base";
2814 clock-names = "apb_pclk";
2816 out-ports {
2819 remote-endpoint = <&funnel0_in7>;
2826 compatible = "qcom,coresight-tpda", "arm,primecell";
2830 clock-names = "apb_pclk";
2832 out-ports {
2833 #address-cells = <1>;
2834 #size-cells = <0>;
2839 remote-endpoint = <&funnel_qatb_in_tpda>;
2844 in-ports {
2845 #address-cells = <1>;
2846 #size-cells = <0>;
2851 remote-endpoint = <&tpdm_mm_out_tpda9>;
2858 remote-endpoint = <&tpdm_prng_out_tpda_23>;
2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2869 clock-names = "apb_pclk";
2871 out-ports {
2874 remote-endpoint = <&funnel_in0_in_funnel_qatb>;
2879 in-ports {
2880 #address-cells = <1>;
2881 #size-cells = <0>;
2886 remote-endpoint = <&tpda_out_funnel_qatb>;
2893 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2897 clock-names = "apb_pclk";
2899 out-ports {
2902 remote-endpoint = <&funnel_merg_in_funnel_in0>;
2907 in-ports {
2908 #address-cells = <1>;
2909 #size-cells = <0>;
2914 remote-endpoint = <&funnel_qatb_out_funnel_in0>;
2921 remote-endpoint = <&stm_out>;
2928 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2932 clock-names = "apb_pclk";
2934 out-ports {
2937 remote-endpoint = <&funnel_merg_in_funnel_in1>;
2942 in-ports {
2943 #address-cells = <1>;
2944 #size-cells = <0>;
2949 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>;
2956 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2960 clock-names = "apb_pclk";
2962 out-ports {
2965 remote-endpoint = <&funnel_swao_in_funnel_merg>;
2970 in-ports {
2971 #address-cells = <1>;
2972 #size-cells = <0>;
2977 remote-endpoint = <&funnel_in0_out_funnel_merg>;
2984 remote-endpoint = <&funnel_in1_out_funnel_merg>;
2991 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2995 clock-names = "apb_pclk";
2997 out-ports {
3000 remote-endpoint = <&etr_in>;
3005 in-ports {
3008 remote-endpoint = <&replicator_swao_out_cx_in>;
3015 compatible = "arm,coresight-tmc", "arm,primecell";
3019 clock-names = "apb_pclk";
3020 arm,scatter-gather;
3022 in-ports {
3025 remote-endpoint = <&replicator_out>;
3032 compatible = "qcom,coresight-tpdm", "arm,primecell";
3036 clock-names = "apb_pclk";
3038 out-ports {
3041 remote-endpoint = <&tpda_23_in_tpdm_prng>;
3048 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3049 arm,primecell-periphid = <0x000bb908>;
3054 clock-names = "apb_pclk";
3056 out-ports {
3059 remote-endpoint = <&etf_in_funnel_swao_out>;
3064 in-ports {
3065 #address-cells = <1>;
3066 #size-cells = <0>;
3071 remote-endpoint = <&funnel_merg_out_funnel_swao>;
3078 compatible = "arm,coresight-tmc", "arm,primecell";
3082 clock-names = "apb_pclk";
3084 out-ports {
3087 remote-endpoint = <&replicator_in>;
3092 in-ports {
3093 #address-cells = <1>;
3094 #size-cells = <0>;
3099 remote-endpoint = <&funnel_swao_out_etf>;
3106 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3110 clock-names = "apb_pclk";
3112 out-ports {
3115 remote-endpoint = <&replicator_cx_in_swao_out>;
3120 in-ports {
3123 remote-endpoint = <&etf_out>;
3130 compatible = "qcom,coresight-tpdm", "arm,primecell";
3134 clock-names = "apb_pclk";
3136 out-ports {
3139 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
3146 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3150 clock-names = "apb_pclk";
3152 out-ports {
3155 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>;
3160 in-ports {
3161 #address-cells = <1>;
3162 #size-cells = <0>;
3167 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>;
3174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3178 clock-names = "apb_pclk";
3180 out-ports {
3181 #address-cells = <1>;
3182 #size-cells = <0>;
3185 remote-endpoint = <&tpda_9_in_tpdm_mm>;
3190 in-ports {
3191 #address-cells = <1>;
3192 #size-cells = <0>;
3197 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>;
3204 compatible = "arm,coresight-etm4x", "arm,primecell";
3210 clock-names = "apb_pclk";
3211 arm,coresight-loses-context-with-cpu;
3213 out-ports {
3216 remote-endpoint = <&apss_funnel_in0>;
3223 compatible = "arm,coresight-etm4x", "arm,primecell";
3229 clock-names = "apb_pclk";
3230 arm,coresight-loses-context-with-cpu;
3232 out-ports {
3235 remote-endpoint = <&apss_funnel_in1>;
3242 compatible = "arm,coresight-etm4x", "arm,primecell";
3248 clock-names = "apb_pclk";
3249 arm,coresight-loses-context-with-cpu;
3251 out-ports {
3254 remote-endpoint = <&apss_funnel_in2>;
3261 compatible = "arm,coresight-etm4x", "arm,primecell";
3267 clock-names = "apb_pclk";
3268 arm,coresight-loses-context-with-cpu;
3270 out-ports {
3273 remote-endpoint = <&apss_funnel_in3>;
3280 compatible = "arm,coresight-etm4x", "arm,primecell";
3286 clock-names = "apb_pclk";
3287 arm,coresight-loses-context-with-cpu;
3289 out-ports {
3292 remote-endpoint = <&apss_funnel_in4>;
3299 compatible = "arm,coresight-etm4x", "arm,primecell";
3305 clock-names = "apb_pclk";
3306 arm,coresight-loses-context-with-cpu;
3308 out-ports {
3311 remote-endpoint = <&apss_funnel_in5>;
3318 compatible = "arm,coresight-etm4x", "arm,primecell";
3324 clock-names = "apb_pclk";
3325 arm,coresight-loses-context-with-cpu;
3327 out-ports {
3330 remote-endpoint = <&apss_funnel_in6>;
3337 compatible = "arm,coresight-etm4x", "arm,primecell";
3343 clock-names = "apb_pclk";
3344 arm,coresight-loses-context-with-cpu;
3346 out-ports {
3349 remote-endpoint = <&apss_funnel_in7>;
3356 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3360 clock-names = "apb_pclk";
3362 out-ports {
3365 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>;
3370 in-ports {
3371 #address-cells = <1>;
3372 #size-cells = <0>;
3377 remote-endpoint = <&etm0_out>;
3384 remote-endpoint = <&etm1_out>;
3391 remote-endpoint = <&etm2_out>;
3398 remote-endpoint = <&etm3_out>;
3405 remote-endpoint = <&etm4_out>;
3412 remote-endpoint = <&etm5_out>;
3419 remote-endpoint = <&etm6_out>;
3426 remote-endpoint = <&etm7_out>;
3433 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3437 clock-names = "apb_pclk";
3439 out-ports {
3442 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>;
3447 in-ports {
3448 #address-cells = <1>;
3449 #size-cells = <0>;
3454 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>;
3461 compatible = "qcom,sm8250-cdsp-pas";
3464 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3469 interrupt-names = "wdog", "fatal", "ready",
3470 "handover", "stop-ack";
3473 clock-names = "xo";
3475 power-domains = <&rpmhpd RPMHPD_CX>;
3477 memory-region = <&cdsp_mem>;
3481 qcom,smem-states = <&smp2p_cdsp_out 0>;
3482 qcom,smem-state-names = "stop";
3486 glink-edge {
3487 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
3494 qcom,remote-pid = <5>;
3498 qcom,glink-channels = "fastrpcglink-apps-dsp";
3500 qcom,non-secure-domain;
3501 #address-cells = <1>;
3502 #size-cells = <0>;
3504 compute-cb@1 {
3505 compatible = "qcom,fastrpc-compute-cb";
3510 compute-cb@2 {
3511 compatible = "qcom,fastrpc-compute-cb";
3516 compute-cb@3 {
3517 compatible = "qcom,fastrpc-compute-cb";
3522 compute-cb@4 {
3523 compatible = "qcom,fastrpc-compute-cb";
3528 compute-cb@5 {
3529 compatible = "qcom,fastrpc-compute-cb";
3534 compute-cb@6 {
3535 compatible = "qcom,fastrpc-compute-cb";
3540 compute-cb@7 {
3541 compatible = "qcom,fastrpc-compute-cb";
3546 compute-cb@8 {
3547 compatible = "qcom,fastrpc-compute-cb";
3558 compatible = "qcom,sm8250-usb-hs-phy",
3559 "qcom,usb-snps-hs-7nm-phy";
3562 #phy-cells = <0>;
3565 clock-names = "ref";
3571 compatible = "qcom,sm8250-usb-hs-phy",
3572 "qcom,usb-snps-hs-7nm-phy";
3575 #phy-cells = <0>;
3578 clock-names = "ref";
3584 compatible = "qcom,sm8250-qmp-usb3-dp-phy";
3589 #address-cells = <2>;
3590 #size-cells = <2>;
3596 clock-names = "aux", "ref_clk_src", "com_aux";
3600 reset-names = "phy", "common";
3602 usb_1_ssphy: usb3-phy@88e9200 {
3609 #clock-cells = <0>;
3610 #phy-cells = <0>;
3612 clock-names = "pipe0";
3613 clock-output-names = "usb3_phy_pipe_clk_src";
3616 dp_phy: dp-phy@88ea200 {
3622 #phy-cells = <0>;
3623 #clock-cells = <1>;
3628 compatible = "qcom,sm8250-qmp-usb3-uni-phy";
3631 #address-cells = <2>;
3632 #size-cells = <2>;
3639 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3643 reset-names = "phy", "common";
3649 #clock-cells = <0>;
3650 #phy-cells = <0>;
3652 clock-names = "pipe0";
3653 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3658 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
3663 interrupt-names = "hc_irq", "pwr_irq";
3668 clock-names = "iface", "core", "xo";
3670 qcom,dll-config = <0x0007642c>;
3671 qcom,ddr-config = <0x80040868>;
3672 power-domains = <&rpmhpd RPMHPD_CX>;
3673 operating-points-v2 = <&sdhc2_opp_table>;
3677 sdhc2_opp_table: opp-table {
3678 compatible = "operating-points-v2";
3680 opp-19200000 {
3681 opp-hz = /bits/ 64 <19200000>;
3682 required-opps = <&rpmhpd_opp_min_svs>;
3685 opp-50000000 {
3686 opp-hz = /bits/ 64 <50000000>;
3687 required-opps = <&rpmhpd_opp_low_svs>;
3690 opp-100000000 {
3691 opp-hz = /bits/ 64 <100000000>;
3692 required-opps = <&rpmhpd_opp_svs>;
3695 opp-202000000 {
3696 opp-hz = /bits/ 64 <202000000>;
3697 required-opps = <&rpmhpd_opp_svs_l1>;
3703 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3710 operating-points-v2 = <&llcc_bwmon_opp_table>;
3712 llcc_bwmon_opp_table: opp-table {
3713 compatible = "operating-points-v2";
3715 opp-800000 {
3716 opp-peak-kBps = <(200 * 4 * 1000)>;
3719 opp-1200000 {
3720 opp-peak-kBps = <(300 * 4 * 1000)>;
3723 opp-1804000 {
3724 opp-peak-kBps = <(451 * 4 * 1000)>;
3727 opp-2188000 {
3728 opp-peak-kBps = <(547 * 4 * 1000)>;
3731 opp-2724000 {
3732 opp-peak-kBps = <(681 * 4 * 1000)>;
3735 opp-3072000 {
3736 opp-peak-kBps = <(768 * 4 * 1000)>;
3739 opp-4068000 {
3740 opp-peak-kBps = <(1017 * 4 * 1000)>;
3745 opp-6220000 {
3746 opp-peak-kBps = <(1555 * 4 * 1000)>;
3749 opp-7216000 {
3750 opp-peak-kBps = <(1804 * 4 * 1000)>;
3753 opp-8368000 {
3754 opp-peak-kBps = <(2092 * 4 * 1000)>;
3758 opp-10944000 {
3759 opp-peak-kBps = <(2736 * 4 * 1000)>;
3765 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon";
3771 operating-points-v2 = <&cpu_bwmon_opp_table>;
3773 cpu_bwmon_opp_table: opp-table {
3774 compatible = "operating-points-v2";
3776 opp-800000 {
3777 opp-peak-kBps = <(200 * 4 * 1000)>;
3780 opp-1804000 {
3781 opp-peak-kBps = <(451 * 4 * 1000)>;
3784 opp-2188000 {
3785 opp-peak-kBps = <(547 * 4 * 1000)>;
3788 opp-2724000 {
3789 opp-peak-kBps = <(681 * 4 * 1000)>;
3792 opp-3072000 {
3793 opp-peak-kBps = <(768 * 4 * 1000)>;
3798 opp-6220000 {
3799 opp-peak-kBps = <(1555 * 4 * 1000)>;
3802 opp-6832000 {
3803 opp-peak-kBps = <(1708 * 4 * 1000)>;
3806 opp-8368000 {
3807 opp-peak-kBps = <(2092 * 4 * 1000)>;
3813 opp-10944000 {
3814 opp-peak-kBps = <(2736 * 4 * 1000)>;
3818 opp-12784000 {
3819 opp-peak-kBps = <(3196 * 4 * 1000)>;
3825 compatible = "qcom,sm8250-dc-noc";
3827 #interconnect-cells = <2>;
3828 qcom,bcm-voters = <&apps_bcm_voter>;
3832 compatible = "qcom,sm8250-gem-noc";
3834 #interconnect-cells = <2>;
3835 qcom,bcm-voters = <&apps_bcm_voter>;
3839 compatible = "qcom,sm8250-npu-noc";
3841 #interconnect-cells = <2>;
3842 qcom,bcm-voters = <&apps_bcm_voter>;
3846 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3849 #address-cells = <2>;
3850 #size-cells = <2>;
3852 dma-ranges;
3860 clock-names = "cfg_noc",
3867 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3869 assigned-clock-rates = <19200000>, <200000000>;
3871 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3875 interrupt-names = "hs_phy_irq",
3880 power-domains = <&gcc USB30_PRIM_GDSC>;
3886 interconnect-names = "usb-ddr", "apps-usb";
3896 phy-names = "usb2-phy", "usb3-phy";
3900 system-cache-controller@9200000 {
3901 compatible = "qcom,sm8250-llcc";
3905 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3910 compatible = "qcom,sm8250-dwc3", "qcom,dwc3";
3913 #address-cells = <2>;
3914 #size-cells = <2>;
3916 dma-ranges;
3924 clock-names = "cfg_noc",
3931 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3933 assigned-clock-rates = <19200000>, <200000000>;
3935 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3939 interrupt-names = "hs_phy_irq",
3944 power-domains = <&gcc USB30_SEC_GDSC>;
3950 interconnect-names = "usb-ddr", "apps-usb";
3960 phy-names = "usb2-phy", "usb3-phy";
3964 venus: video-codec@aa00000 {
3965 compatible = "qcom,sm8250-venus";
3968 power-domains = <&videocc MVS0C_GDSC>,
3971 power-domain-names = "venus", "vcodec0", "mx";
3972 operating-points-v2 = <&venus_opp_table>;
3977 clock-names = "iface", "core", "vcodec0_core";
3981 interconnect-names = "cpu-cfg", "video-mem";
3984 memory-region = <&video_mem>;
3988 reset-names = "bus", "core";
3992 video-decoder {
3993 compatible = "venus-decoder";
3996 video-encoder {
3997 compatible = "venus-encoder";
4000 venus_opp_table: opp-table {
4001 compatible = "operating-points-v2";
4003 opp-720000000 {
4004 opp-hz = /bits/ 64 <720000000>;
4005 required-opps = <&rpmhpd_opp_low_svs>;
4008 opp-1014000000 {
4009 opp-hz = /bits/ 64 <1014000000>;
4010 required-opps = <&rpmhpd_opp_svs>;
4013 opp-1098000000 {
4014 opp-hz = /bits/ 64 <1098000000>;
4015 required-opps = <&rpmhpd_opp_svs_l1>;
4018 opp-1332000000 {
4019 opp-hz = /bits/ 64 <1332000000>;
4020 required-opps = <&rpmhpd_opp_nom>;
4025 videocc: clock-controller@abf0000 {
4026 compatible = "qcom,sm8250-videocc";
4031 power-domains = <&rpmhpd RPMHPD_MMCX>;
4032 required-opps = <&rpmhpd_opp_low_svs>;
4033 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao";
4034 #clock-cells = <1>;
4035 #reset-cells = <1>;
4036 #power-domain-cells = <1>;
4040 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4041 #address-cells = <1>;
4042 #size-cells = <0>;
4046 power-domains = <&camcc TITAN_TOP_GDSC>;
4053 clock-names = "camnoc_axi",
4059 pinctrl-0 = <&cci0_default>;
4060 pinctrl-1 = <&cci0_sleep>;
4061 pinctrl-names = "default", "sleep";
4065 cci0_i2c0: i2c-bus@0 {
4067 clock-frequency = <1000000>;
4068 #address-cells = <1>;
4069 #size-cells = <0>;
4072 cci0_i2c1: i2c-bus@1 {
4074 clock-frequency = <1000000>;
4075 #address-cells = <1>;
4076 #size-cells = <0>;
4081 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci";
4082 #address-cells = <1>;
4083 #size-cells = <0>;
4087 power-domains = <&camcc TITAN_TOP_GDSC>;
4094 clock-names = "camnoc_axi",
4100 pinctrl-0 = <&cci1_default>;
4101 pinctrl-1 = <&cci1_sleep>;
4102 pinctrl-names = "default", "sleep";
4106 cci1_i2c0: i2c-bus@0 {
4108 clock-frequency = <1000000>;
4109 #address-cells = <1>;
4110 #size-cells = <0>;
4113 cci1_i2c1: i2c-bus@1 {
4115 clock-frequency = <1000000>;
4116 #address-cells = <1>;
4117 #size-cells = <0>;
4122 compatible = "qcom,sm8250-camss";
4135 reg-names = "csiphy0",
4160 interrupt-names = "csiphy0",
4175 power-domains = <&camcc IFE_0_GDSC>,
4217 clock-names = "cam_ahb_clk",
4268 interconnect-names = "cam_ahb",
4274 #address-cells = <1>;
4275 #size-cells = <0>;
4303 camcc: clock-controller@ad00000 {
4304 compatible = "qcom,sm8250-camcc";
4310 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
4311 power-domains = <&rpmhpd RPMHPD_MMCX>;
4312 required-opps = <&rpmhpd_opp_low_svs>;
4314 #clock-cells = <1>;
4315 #reset-cells = <1>;
4316 #power-domain-cells = <1>;
4319 mdss: display-subsystem@ae00000 {
4320 compatible = "qcom,sm8250-mdss";
4322 reg-names = "mdss";
4326 interconnect-names = "mdp0-mem", "mdp1-mem";
4328 power-domains = <&dispcc MDSS_GDSC>;
4334 clock-names = "iface", "bus", "nrt_bus", "core";
4337 interrupt-controller;
4338 #interrupt-cells = <1>;
4344 #address-cells = <2>;
4345 #size-cells = <2>;
4348 mdss_mdp: display-controller@ae01000 {
4349 compatible = "qcom,sm8250-dpu";
4352 reg-names = "mdp", "vbif";
4358 clock-names = "iface", "bus", "core", "vsync";
4360 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4361 assigned-clock-rates = <19200000>;
4363 operating-points-v2 = <&mdp_opp_table>;
4364 power-domains = <&rpmhpd RPMHPD_MMCX>;
4366 interrupt-parent = <&mdss>;
4370 #address-cells = <1>;
4371 #size-cells = <0>;
4376 remote-endpoint = <&mdss_dsi0_in>;
4383 remote-endpoint = <&mdss_dsi1_in>;
4388 mdp_opp_table: opp-table {
4389 compatible = "operating-points-v2";
4391 opp-200000000 {
4392 opp-hz = /bits/ 64 <200000000>;
4393 required-opps = <&rpmhpd_opp_low_svs>;
4396 opp-300000000 {
4397 opp-hz = /bits/ 64 <300000000>;
4398 required-opps = <&rpmhpd_opp_svs>;
4401 opp-345000000 {
4402 opp-hz = /bits/ 64 <345000000>;
4403 required-opps = <&rpmhpd_opp_svs_l1>;
4406 opp-460000000 {
4407 opp-hz = /bits/ 64 <460000000>;
4408 required-opps = <&rpmhpd_opp_nom>;
4414 compatible = "qcom,sm8250-dsi-ctrl",
4415 "qcom,mdss-dsi-ctrl";
4417 reg-names = "dsi_ctrl";
4419 interrupt-parent = <&mdss>;
4428 clock-names = "byte",
4435 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4436 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4438 operating-points-v2 = <&dsi_opp_table>;
4439 power-domains = <&rpmhpd RPMHPD_MMCX>;
4445 #address-cells = <1>;
4446 #size-cells = <0>;
4449 #address-cells = <1>;
4450 #size-cells = <0>;
4455 remote-endpoint = <&dpu_intf1_out>;
4466 dsi_opp_table: opp-table {
4467 compatible = "operating-points-v2";
4469 opp-187500000 {
4470 opp-hz = /bits/ 64 <187500000>;
4471 required-opps = <&rpmhpd_opp_low_svs>;
4474 opp-300000000 {
4475 opp-hz = /bits/ 64 <300000000>;
4476 required-opps = <&rpmhpd_opp_svs>;
4479 opp-358000000 {
4480 opp-hz = /bits/ 64 <358000000>;
4481 required-opps = <&rpmhpd_opp_svs_l1>;
4487 compatible = "qcom,dsi-phy-7nm";
4491 reg-names = "dsi_phy",
4495 #clock-cells = <1>;
4496 #phy-cells = <0>;
4500 clock-names = "iface", "ref";
4506 compatible = "qcom,sm8250-dsi-ctrl",
4507 "qcom,mdss-dsi-ctrl";
4509 reg-names = "dsi_ctrl";
4511 interrupt-parent = <&mdss>;
4520 clock-names = "byte",
4527 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4528 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4530 operating-points-v2 = <&dsi_opp_table>;
4531 power-domains = <&rpmhpd RPMHPD_MMCX>;
4537 #address-cells = <1>;
4538 #size-cells = <0>;
4541 #address-cells = <1>;
4542 #size-cells = <0>;
4547 remote-endpoint = <&dpu_intf2_out>;
4560 compatible = "qcom,dsi-phy-7nm";
4564 reg-names = "dsi_phy",
4568 #clock-cells = <1>;
4569 #phy-cells = <0>;
4573 clock-names = "iface", "ref";
4579 dispcc: clock-controller@af00000 {
4580 compatible = "qcom,sm8250-dispcc";
4582 power-domains = <&rpmhpd RPMHPD_MMCX>;
4583 required-opps = <&rpmhpd_opp_low_svs>;
4591 clock-names = "bi_tcxo",
4598 #clock-cells = <1>;
4599 #reset-cells = <1>;
4600 #power-domain-cells = <1>;
4603 pdc: interrupt-controller@b220000 {
4604 compatible = "qcom,sm8250-pdc", "qcom,pdc";
4606 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
4608 #interrupt-cells = <2>;
4609 interrupt-parent = <&intc>;
4610 interrupt-controller;
4613 tsens0: thermal-sensor@c263000 {
4614 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4620 interrupt-names = "uplow", "critical";
4621 #thermal-sensor-cells = <1>;
4624 tsens1: thermal-sensor@c265000 {
4625 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
4631 interrupt-names = "uplow", "critical";
4632 #thermal-sensor-cells = <1>;
4635 aoss_qmp: power-management@c300000 {
4636 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp";
4638 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4644 #clock-cells = <0>;
4648 compatible = "qcom,rpmh-stats";
4653 compatible = "qcom,spmi-pmic-arb";
4659 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4660 interrupt-names = "periph_irq";
4661 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4664 #address-cells = <2>;
4665 #size-cells = <0>;
4666 interrupt-controller;
4667 #interrupt-cells = <4>;
4671 compatible = "qcom,sm8250-pinctrl";
4675 reg-names = "west", "south", "north";
4677 gpio-controller;
4678 #gpio-cells = <2>;
4679 interrupt-controller;
4680 #interrupt-cells = <2>;
4681 gpio-ranges = <&tlmm 0 0 181>;
4682 wakeup-parent = <&pdc>;
4684 cam2_default: cam2-default-state {
4685 rst-pins {
4688 drive-strength = <2>;
4689 bias-disable;
4692 mclk-pins {
4695 drive-strength = <16>;
4696 bias-disable;
4700 cam2_suspend: cam2-suspend-state {
4701 rst-pins {
4704 drive-strength = <2>;
4705 bias-pull-down;
4706 output-low;
4709 mclk-pins {
4712 drive-strength = <2>;
4713 bias-disable;
4717 cci0_default: cci0-default-state {
4718 cci0_i2c0_default: cci0-i2c0-default-pins {
4723 bias-pull-up;
4724 drive-strength = <2>; /* 2 mA */
4727 cci0_i2c1_default: cci0-i2c1-default-pins {
4732 bias-pull-up;
4733 drive-strength = <2>; /* 2 mA */
4737 cci0_sleep: cci0-sleep-state {
4738 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4743 drive-strength = <2>; /* 2 mA */
4744 bias-pull-down;
4747 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4752 drive-strength = <2>; /* 2 mA */
4753 bias-pull-down;
4757 cci1_default: cci1-default-state {
4758 cci1_i2c0_default: cci1-i2c0-default-pins {
4763 bias-pull-up;
4764 drive-strength = <2>; /* 2 mA */
4767 cci1_i2c1_default: cci1-i2c1-default-pins {
4772 bias-pull-up;
4773 drive-strength = <2>; /* 2 mA */
4777 cci1_sleep: cci1-sleep-state {
4778 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4783 bias-pull-down;
4784 drive-strength = <2>; /* 2 mA */
4787 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4792 bias-pull-down;
4793 drive-strength = <2>; /* 2 mA */
4797 pri_mi2s_active: pri-mi2s-active-state {
4798 sclk-pins {
4801 drive-strength = <8>;
4802 bias-disable;
4805 ws-pins {
4808 drive-strength = <8>;
4809 output-high;
4812 data0-pins {
4815 drive-strength = <8>;
4816 bias-disable;
4817 output-high;
4820 data1-pins {
4823 drive-strength = <8>;
4824 output-high;
4828 qup_i2c0_default: qup-i2c0-default-state {
4831 drive-strength = <2>;
4832 bias-disable;
4835 qup_i2c1_default: qup-i2c1-default-state {
4838 drive-strength = <2>;
4839 bias-disable;
4842 qup_i2c2_default: qup-i2c2-default-state {
4845 drive-strength = <2>;
4846 bias-disable;
4849 qup_i2c3_default: qup-i2c3-default-state {
4852 drive-strength = <2>;
4853 bias-disable;
4856 qup_i2c4_default: qup-i2c4-default-state {
4859 drive-strength = <2>;
4860 bias-disable;
4863 qup_i2c5_default: qup-i2c5-default-state {
4866 drive-strength = <2>;
4867 bias-disable;
4870 qup_i2c6_default: qup-i2c6-default-state {
4873 drive-strength = <2>;
4874 bias-disable;
4877 qup_i2c7_default: qup-i2c7-default-state {
4880 drive-strength = <2>;
4881 bias-disable;
4884 qup_i2c8_default: qup-i2c8-default-state {
4887 drive-strength = <2>;
4888 bias-disable;
4891 qup_i2c9_default: qup-i2c9-default-state {
4894 drive-strength = <2>;
4895 bias-disable;
4898 qup_i2c10_default: qup-i2c10-default-state {
4901 drive-strength = <2>;
4902 bias-disable;
4905 qup_i2c11_default: qup-i2c11-default-state {
4908 drive-strength = <2>;
4909 bias-disable;
4912 qup_i2c12_default: qup-i2c12-default-state {
4915 drive-strength = <2>;
4916 bias-disable;
4919 qup_i2c13_default: qup-i2c13-default-state {
4922 drive-strength = <2>;
4923 bias-disable;
4926 qup_i2c14_default: qup-i2c14-default-state {
4929 drive-strength = <2>;
4930 bias-disable;
4933 qup_i2c15_default: qup-i2c15-default-state {
4936 drive-strength = <2>;
4937 bias-disable;
4940 qup_i2c16_default: qup-i2c16-default-state {
4943 drive-strength = <2>;
4944 bias-disable;
4947 qup_i2c17_default: qup-i2c17-default-state {
4950 drive-strength = <2>;
4951 bias-disable;
4954 qup_i2c18_default: qup-i2c18-default-state {
4957 drive-strength = <2>;
4958 bias-disable;
4961 qup_i2c19_default: qup-i2c19-default-state {
4964 drive-strength = <2>;
4965 bias-disable;
4968 qup_spi0_cs: qup-spi0-cs-state {
4973 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4978 qup_spi0_data_clk: qup-spi0-data-clk-state {
4984 qup_spi1_cs: qup-spi1-cs-state {
4989 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4994 qup_spi1_data_clk: qup-spi1-data-clk-state {
5000 qup_spi2_cs: qup-spi2-cs-state {
5005 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
5010 qup_spi2_data_clk: qup-spi2-data-clk-state {
5016 qup_spi3_cs: qup-spi3-cs-state {
5021 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
5026 qup_spi3_data_clk: qup-spi3-data-clk-state {
5032 qup_spi4_cs: qup-spi4-cs-state {
5037 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
5042 qup_spi4_data_clk: qup-spi4-data-clk-state {
5048 qup_spi5_cs: qup-spi5-cs-state {
5053 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
5058 qup_spi5_data_clk: qup-spi5-data-clk-state {
5064 qup_spi6_cs: qup-spi6-cs-state {
5069 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
5074 qup_spi6_data_clk: qup-spi6-data-clk-state {
5080 qup_spi7_cs: qup-spi7-cs-state {
5085 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
5090 qup_spi7_data_clk: qup-spi7-data-clk-state {
5096 qup_spi8_cs: qup-spi8-cs-state {
5101 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
5106 qup_spi8_data_clk: qup-spi8-data-clk-state {
5112 qup_spi9_cs: qup-spi9-cs-state {
5117 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
5122 qup_spi9_data_clk: qup-spi9-data-clk-state {
5128 qup_spi10_cs: qup-spi10-cs-state {
5133 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
5138 qup_spi10_data_clk: qup-spi10-data-clk-state {
5144 qup_spi11_cs: qup-spi11-cs-state {
5149 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
5154 qup_spi11_data_clk: qup-spi11-data-clk-state {
5160 qup_spi12_cs: qup-spi12-cs-state {
5165 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
5170 qup_spi12_data_clk: qup-spi12-data-clk-state {
5176 qup_spi13_cs: qup-spi13-cs-state {
5181 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
5186 qup_spi13_data_clk: qup-spi13-data-clk-state {
5192 qup_spi14_cs: qup-spi14-cs-state {
5197 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
5202 qup_spi14_data_clk: qup-spi14-data-clk-state {
5208 qup_spi15_cs: qup-spi15-cs-state {
5213 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
5218 qup_spi15_data_clk: qup-spi15-data-clk-state {
5224 qup_spi16_cs: qup-spi16-cs-state {
5229 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state {
5234 qup_spi16_data_clk: qup-spi16-data-clk-state {
5240 qup_spi17_cs: qup-spi17-cs-state {
5245 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state {
5250 qup_spi17_data_clk: qup-spi17-data-clk-state {
5256 qup_spi18_cs: qup-spi18-cs-state {
5261 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state {
5266 qup_spi18_data_clk: qup-spi18-data-clk-state {
5272 qup_spi19_cs: qup-spi19-cs-state {
5277 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state {
5282 qup_spi19_data_clk: qup-spi19-data-clk-state {
5288 qup_uart2_default: qup-uart2-default-state {
5293 qup_uart6_default: qup-uart6-default-state {
5298 qup_uart12_default: qup-uart12-default-state {
5303 qup_uart17_default: qup-uart17-default-state {
5308 qup_uart18_default: qup-uart18-default-state {
5313 tert_mi2s_active: tert-mi2s-active-state {
5314 sck-pins {
5317 drive-strength = <8>;
5318 bias-disable;
5321 data0-pins {
5324 drive-strength = <8>;
5325 bias-disable;
5326 output-high;
5329 ws-pins {
5332 drive-strength = <8>;
5333 output-high;
5337 sdc2_sleep_state: sdc2-sleep-state {
5338 clk-pins {
5340 drive-strength = <2>;
5341 bias-disable;
5344 cmd-pins {
5346 drive-strength = <2>;
5347 bias-pull-up;
5350 data-pins {
5352 drive-strength = <2>;
5353 bias-pull-up;
5357 pcie0_default_state: pcie0-default-state {
5358 perst-pins {
5361 drive-strength = <2>;
5362 bias-pull-down;
5365 clkreq-pins {
5368 drive-strength = <2>;
5369 bias-pull-up;
5372 wake-pins {
5375 drive-strength = <2>;
5376 bias-pull-up;
5380 pcie1_default_state: pcie1-default-state {
5381 perst-pins {
5384 drive-strength = <2>;
5385 bias-pull-down;
5388 clkreq-pins {
5391 drive-strength = <2>;
5392 bias-pull-up;
5395 wake-pins {
5398 drive-strength = <2>;
5399 bias-pull-up;
5403 pcie2_default_state: pcie2-default-state {
5404 perst-pins {
5407 drive-strength = <2>;
5408 bias-pull-down;
5411 clkreq-pins {
5414 drive-strength = <2>;
5415 bias-pull-up;
5418 wake-pins {
5421 drive-strength = <2>;
5422 bias-pull-up;
5428 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500";
5430 #iommu-cells = <2>;
5431 #global-interrupts = <2>;
5530 dma-coherent;
5534 compatible = "qcom,sm8250-adsp-pas";
5537 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
5542 interrupt-names = "wdog", "fatal", "ready",
5543 "handover", "stop-ack";
5546 clock-names = "xo";
5548 power-domains = <&rpmhpd RPMHPD_LCX>,
5550 power-domain-names = "lcx", "lmx";
5552 memory-region = <&adsp_mem>;
5556 qcom,smem-states = <&smp2p_adsp_out 0>;
5557 qcom,smem-state-names = "stop";
5561 glink-edge {
5562 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
5569 qcom,remote-pid = <2>;
5572 compatible = "qcom,apr-v2";
5573 qcom,glink-channels = "apr_audio_svc";
5575 #address-cells = <1>;
5576 #size-cells = <0>;
5581 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5587 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5589 compatible = "qcom,q6afe-dais";
5590 #address-cells = <1>;
5591 #size-cells = <0>;
5592 #sound-dai-cells = <1>;
5595 q6afecc: clock-controller {
5596 compatible = "qcom,q6afe-clocks";
5597 #clock-cells = <2>;
5604 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5606 compatible = "qcom,q6asm-dais";
5607 #address-cells = <1>;
5608 #size-cells = <0>;
5609 #sound-dai-cells = <1>;
5617 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
5619 compatible = "qcom,q6adm-routing";
5620 #sound-dai-cells = <0>;
5627 qcom,glink-channels = "fastrpcglink-apps-dsp";
5629 qcom,non-secure-domain;
5630 #address-cells = <1>;
5631 #size-cells = <0>;
5633 compute-cb@3 {
5634 compatible = "qcom,fastrpc-compute-cb";
5639 compute-cb@4 {
5640 compatible = "qcom,fastrpc-compute-cb";
5645 compute-cb@5 {
5646 compatible = "qcom,fastrpc-compute-cb";
5654 intc: interrupt-controller@17a00000 {
5655 compatible = "arm,gic-v3";
5656 #interrupt-cells = <3>;
5657 interrupt-controller;
5664 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
5671 #address-cells = <1>;
5672 #size-cells = <1>;
5674 compatible = "arm,armv7-timer-mem";
5676 clock-frequency = <19200000>;
5679 frame-number = <0>;
5687 frame-number = <1>;
5694 frame-number = <2>;
5701 frame-number = <3>;
5708 frame-number = <4>;
5715 frame-number = <5>;
5722 frame-number = <6>;
5731 compatible = "qcom,rpmh-rsc";
5735 reg-names = "drv-0", "drv-1", "drv-2";
5739 qcom,tcs-offset = <0xd00>;
5740 qcom,drv-id = <2>;
5741 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
5743 power-domains = <&CLUSTER_PD>;
5745 rpmhcc: clock-controller {
5746 compatible = "qcom,sm8250-rpmh-clk";
5747 #clock-cells = <1>;
5748 clock-names = "xo";
5752 rpmhpd: power-controller {
5753 compatible = "qcom,sm8250-rpmhpd";
5754 #power-domain-cells = <1>;
5755 operating-points-v2 = <&rpmhpd_opp_table>;
5757 rpmhpd_opp_table: opp-table {
5758 compatible = "operating-points-v2";
5761 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5765 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5769 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5773 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5777 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5781 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5785 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5789 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5793 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5797 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5802 apps_bcm_voter: bcm-voter {
5803 compatible = "qcom,bcm-voter";
5808 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3";
5812 clock-names = "xo", "alternate";
5814 #interconnect-cells = <1>;
5818 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
5822 reg-names = "freq-domain0", "freq-domain1",
5823 "freq-domain2";
5826 clock-names = "xo", "alternate";
5830 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
5831 #freq-domain-cells = <1>;
5832 #clock-cells = <1>;
5840 compatible = "arm,armv8-timer";
5851 thermal-zones {
5852 cpu0-thermal {
5853 polling-delay-passive = <250>;
5854 polling-delay = <1000>;
5856 thermal-sensors = <&tsens0 1>;
5859 cpu0_alert0: trip-point0 {
5865 cpu0_alert1: trip-point1 {
5871 cpu0_crit: cpu-crit {
5878 cooling-maps {
5881 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5888 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5896 cpu1-thermal {
5897 polling-delay-passive = <250>;
5898 polling-delay = <1000>;
5900 thermal-sensors = <&tsens0 2>;
5903 cpu1_alert0: trip-point0 {
5909 cpu1_alert1: trip-point1 {
5915 cpu1_crit: cpu-crit {
5922 cooling-maps {
5925 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5932 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5940 cpu2-thermal {
5941 polling-delay-passive = <250>;
5942 polling-delay = <1000>;
5944 thermal-sensors = <&tsens0 3>;
5947 cpu2_alert0: trip-point0 {
5953 cpu2_alert1: trip-point1 {
5959 cpu2_crit: cpu-crit {
5966 cooling-maps {
5969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5976 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5984 cpu3-thermal {
5985 polling-delay-passive = <250>;
5986 polling-delay = <1000>;
5988 thermal-sensors = <&tsens0 4>;
5991 cpu3_alert0: trip-point0 {
5997 cpu3_alert1: trip-point1 {
6003 cpu3_crit: cpu-crit {
6010 cooling-maps {
6013 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6020 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6028 cpu4-top-thermal {
6029 polling-delay-passive = <250>;
6030 polling-delay = <1000>;
6032 thermal-sensors = <&tsens0 7>;
6035 cpu4_top_alert0: trip-point0 {
6041 cpu4_top_alert1: trip-point1 {
6047 cpu4_top_crit: cpu-crit {
6054 cooling-maps {
6057 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6064 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6072 cpu5-top-thermal {
6073 polling-delay-passive = <250>;
6074 polling-delay = <1000>;
6076 thermal-sensors = <&tsens0 8>;
6079 cpu5_top_alert0: trip-point0 {
6085 cpu5_top_alert1: trip-point1 {
6091 cpu5_top_crit: cpu-crit {
6098 cooling-maps {
6101 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6108 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6116 cpu6-top-thermal {
6117 polling-delay-passive = <250>;
6118 polling-delay = <1000>;
6120 thermal-sensors = <&tsens0 9>;
6123 cpu6_top_alert0: trip-point0 {
6129 cpu6_top_alert1: trip-point1 {
6135 cpu6_top_crit: cpu-crit {
6142 cooling-maps {
6145 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6152 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6160 cpu7-top-thermal {
6161 polling-delay-passive = <250>;
6162 polling-delay = <1000>;
6164 thermal-sensors = <&tsens0 10>;
6167 cpu7_top_alert0: trip-point0 {
6173 cpu7_top_alert1: trip-point1 {
6179 cpu7_top_crit: cpu-crit {
6186 cooling-maps {
6189 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6196 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6204 cpu4-bottom-thermal {
6205 polling-delay-passive = <250>;
6206 polling-delay = <1000>;
6208 thermal-sensors = <&tsens0 11>;
6211 cpu4_bottom_alert0: trip-point0 {
6217 cpu4_bottom_alert1: trip-point1 {
6223 cpu4_bottom_crit: cpu-crit {
6230 cooling-maps {
6233 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6240 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6248 cpu5-bottom-thermal {
6249 polling-delay-passive = <250>;
6250 polling-delay = <1000>;
6252 thermal-sensors = <&tsens0 12>;
6255 cpu5_bottom_alert0: trip-point0 {
6261 cpu5_bottom_alert1: trip-point1 {
6267 cpu5_bottom_crit: cpu-crit {
6274 cooling-maps {
6277 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6284 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6292 cpu6-bottom-thermal {
6293 polling-delay-passive = <250>;
6294 polling-delay = <1000>;
6296 thermal-sensors = <&tsens0 13>;
6299 cpu6_bottom_alert0: trip-point0 {
6305 cpu6_bottom_alert1: trip-point1 {
6311 cpu6_bottom_crit: cpu-crit {
6318 cooling-maps {
6321 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6328 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6336 cpu7-bottom-thermal {
6337 polling-delay-passive = <250>;
6338 polling-delay = <1000>;
6340 thermal-sensors = <&tsens0 14>;
6343 cpu7_bottom_alert0: trip-point0 {
6349 cpu7_bottom_alert1: trip-point1 {
6355 cpu7_bottom_crit: cpu-crit {
6362 cooling-maps {
6365 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6372 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
6380 aoss0-thermal {
6381 polling-delay-passive = <250>;
6382 polling-delay = <1000>;
6384 thermal-sensors = <&tsens0 0>;
6387 aoss0_alert0: trip-point0 {
6395 cluster0-thermal {
6396 polling-delay-passive = <250>;
6397 polling-delay = <1000>;
6399 thermal-sensors = <&tsens0 5>;
6402 cluster0_alert0: trip-point0 {
6415 cluster1-thermal {
6416 polling-delay-passive = <250>;
6417 polling-delay = <1000>;
6419 thermal-sensors = <&tsens0 6>;
6422 cluster1_alert0: trip-point0 {
6435 gpu-top-thermal {
6436 polling-delay-passive = <250>;
6437 polling-delay = <1000>;
6439 thermal-sensors = <&tsens0 15>;
6442 gpu1_alert0: trip-point0 {
6450 aoss1-thermal {
6451 polling-delay-passive = <250>;
6452 polling-delay = <1000>;
6454 thermal-sensors = <&tsens1 0>;
6457 aoss1_alert0: trip-point0 {
6465 wlan-thermal {
6466 polling-delay-passive = <250>;
6467 polling-delay = <1000>;
6469 thermal-sensors = <&tsens1 1>;
6472 wlan_alert0: trip-point0 {
6480 video-thermal {
6481 polling-delay-passive = <250>;
6482 polling-delay = <1000>;
6484 thermal-sensors = <&tsens1 2>;
6487 video_alert0: trip-point0 {
6495 mem-thermal {
6496 polling-delay-passive = <250>;
6497 polling-delay = <1000>;
6499 thermal-sensors = <&tsens1 3>;
6502 mem_alert0: trip-point0 {
6510 q6-hvx-thermal {
6511 polling-delay-passive = <250>;
6512 polling-delay = <1000>;
6514 thermal-sensors = <&tsens1 4>;
6517 q6_hvx_alert0: trip-point0 {
6525 camera-thermal {
6526 polling-delay-passive = <250>;
6527 polling-delay = <1000>;
6529 thermal-sensors = <&tsens1 5>;
6532 camera_alert0: trip-point0 {
6540 compute-thermal {
6541 polling-delay-passive = <250>;
6542 polling-delay = <1000>;
6544 thermal-sensors = <&tsens1 6>;
6547 compute_alert0: trip-point0 {
6555 npu-thermal {
6556 polling-delay-passive = <250>;
6557 polling-delay = <1000>;
6559 thermal-sensors = <&tsens1 7>;
6562 npu_alert0: trip-point0 {
6570 gpu-bottom-thermal {
6571 polling-delay-passive = <250>;
6572 polling-delay = <1000>;
6574 thermal-sensors = <&tsens1 8>;
6577 gpu2_alert0: trip-point0 {