Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,dispcc-sm8150.h>
13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8150.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
44 #address-cells = <2>;
45 #size-cells = <0>;
52 enable-method = "psci";
53 capacity-dmips-mhz = <488>;
54 dynamic-power-coefficient = <232>;
55 next-level-cache = <&L2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 operating-points-v2 = <&cpu0_opp_table>;
60 power-domains = <&CPU_PD0>;
61 power-domain-names = "psci";
62 #cooling-cells = <2>;
63 L2_0: l2-cache {
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&L3_0>;
68 L3_0: l3-cache {
70 cache-level = <3>;
71 cache-unified;
81 enable-method = "psci";
82 capacity-dmips-mhz = <488>;
83 dynamic-power-coefficient = <232>;
84 next-level-cache = <&L2_100>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 power-domains = <&CPU_PD1>;
90 power-domain-names = "psci";
91 #cooling-cells = <2>;
92 L2_100: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&L3_0>;
105 enable-method = "psci";
106 capacity-dmips-mhz = <488>;
107 dynamic-power-coefficient = <232>;
108 next-level-cache = <&L2_200>;
109 qcom,freq-domain = <&cpufreq_hw 0>;
110 operating-points-v2 = <&cpu0_opp_table>;
113 power-domains = <&CPU_PD2>;
114 power-domain-names = "psci";
115 #cooling-cells = <2>;
116 L2_200: l2-cache {
118 cache-level = <2>;
119 cache-unified;
120 next-level-cache = <&L3_0>;
129 enable-method = "psci";
130 capacity-dmips-mhz = <488>;
131 dynamic-power-coefficient = <232>;
132 next-level-cache = <&L2_300>;
133 qcom,freq-domain = <&cpufreq_hw 0>;
134 operating-points-v2 = <&cpu0_opp_table>;
137 power-domains = <&CPU_PD3>;
138 power-domain-names = "psci";
139 #cooling-cells = <2>;
140 L2_300: l2-cache {
142 cache-level = <2>;
143 cache-unified;
144 next-level-cache = <&L3_0>;
153 enable-method = "psci";
154 capacity-dmips-mhz = <1024>;
155 dynamic-power-coefficient = <369>;
156 next-level-cache = <&L2_400>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 operating-points-v2 = <&cpu4_opp_table>;
161 power-domains = <&CPU_PD4>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_400: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 capacity-dmips-mhz = <1024>;
179 dynamic-power-coefficient = <369>;
180 next-level-cache = <&L2_500>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
182 operating-points-v2 = <&cpu4_opp_table>;
185 power-domains = <&CPU_PD5>;
186 power-domain-names = "psci";
187 #cooling-cells = <2>;
188 L2_500: l2-cache {
190 cache-level = <2>;
191 cache-unified;
192 next-level-cache = <&L3_0>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 dynamic-power-coefficient = <369>;
204 next-level-cache = <&L2_600>;
205 qcom,freq-domain = <&cpufreq_hw 1>;
206 operating-points-v2 = <&cpu4_opp_table>;
209 power-domains = <&CPU_PD6>;
210 power-domain-names = "psci";
211 #cooling-cells = <2>;
212 L2_600: l2-cache {
214 cache-level = <2>;
215 cache-unified;
216 next-level-cache = <&L3_0>;
225 enable-method = "psci";
226 capacity-dmips-mhz = <1024>;
227 dynamic-power-coefficient = <421>;
228 next-level-cache = <&L2_700>;
229 qcom,freq-domain = <&cpufreq_hw 2>;
230 operating-points-v2 = <&cpu7_opp_table>;
233 power-domains = <&CPU_PD7>;
234 power-domain-names = "psci";
235 #cooling-cells = <2>;
236 L2_700: l2-cache {
238 cache-level = <2>;
239 cache-unified;
240 next-level-cache = <&L3_0>;
244 cpu-map {
280 idle-states {
281 entry-method = "psci";
283 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
284 compatible = "arm,idle-state";
285 idle-state-name = "little-rail-power-collapse";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <355>;
288 exit-latency-us = <909>;
289 min-residency-us = <3934>;
290 local-timer-stop;
293 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
294 compatible = "arm,idle-state";
295 idle-state-name = "big-rail-power-collapse";
296 arm,psci-suspend-param = <0x40000004>;
297 entry-latency-us = <241>;
298 exit-latency-us = <1461>;
299 min-residency-us = <4488>;
300 local-timer-stop;
304 domain-idle-states {
305 CLUSTER_SLEEP_0: cluster-sleep-0 {
306 compatible = "domain-idle-state";
307 arm,psci-suspend-param = <0x4100c244>;
308 entry-latency-us = <3263>;
309 exit-latency-us = <6562>;
310 min-residency-us = <9987>;
315 cpu0_opp_table: opp-table-cpu0 {
316 compatible = "operating-points-v2";
317 opp-shared;
319 cpu0_opp1: opp-300000000 {
320 opp-hz = /bits/ 64 <300000000>;
321 opp-peak-kBps = <800000 9600000>;
324 cpu0_opp2: opp-403200000 {
325 opp-hz = /bits/ 64 <403200000>;
326 opp-peak-kBps = <800000 9600000>;
329 cpu0_opp3: opp-499200000 {
330 opp-hz = /bits/ 64 <499200000>;
331 opp-peak-kBps = <800000 12902400>;
334 cpu0_opp4: opp-576000000 {
335 opp-hz = /bits/ 64 <576000000>;
336 opp-peak-kBps = <800000 12902400>;
339 cpu0_opp5: opp-672000000 {
340 opp-hz = /bits/ 64 <672000000>;
341 opp-peak-kBps = <800000 15974400>;
344 cpu0_opp6: opp-768000000 {
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <1804000 19660800>;
349 cpu0_opp7: opp-844800000 {
350 opp-hz = /bits/ 64 <844800000>;
351 opp-peak-kBps = <1804000 19660800>;
354 cpu0_opp8: opp-940800000 {
355 opp-hz = /bits/ 64 <940800000>;
356 opp-peak-kBps = <1804000 22732800>;
359 cpu0_opp9: opp-1036800000 {
360 opp-hz = /bits/ 64 <1036800000>;
361 opp-peak-kBps = <1804000 22732800>;
364 cpu0_opp10: opp-1113600000 {
365 opp-hz = /bits/ 64 <1113600000>;
366 opp-peak-kBps = <2188000 25804800>;
369 cpu0_opp11: opp-1209600000 {
370 opp-hz = /bits/ 64 <1209600000>;
371 opp-peak-kBps = <2188000 31948800>;
374 cpu0_opp12: opp-1305600000 {
375 opp-hz = /bits/ 64 <1305600000>;
376 opp-peak-kBps = <3072000 31948800>;
379 cpu0_opp13: opp-1382400000 {
380 opp-hz = /bits/ 64 <1382400000>;
381 opp-peak-kBps = <3072000 31948800>;
384 cpu0_opp14: opp-1478400000 {
385 opp-hz = /bits/ 64 <1478400000>;
386 opp-peak-kBps = <3072000 31948800>;
389 cpu0_opp15: opp-1555200000 {
390 opp-hz = /bits/ 64 <1555200000>;
391 opp-peak-kBps = <3072000 40550400>;
394 cpu0_opp16: opp-1632000000 {
395 opp-hz = /bits/ 64 <1632000000>;
396 opp-peak-kBps = <3072000 40550400>;
399 cpu0_opp17: opp-1708800000 {
400 opp-hz = /bits/ 64 <1708800000>;
401 opp-peak-kBps = <3072000 43008000>;
404 cpu0_opp18: opp-1785600000 {
405 opp-hz = /bits/ 64 <1785600000>;
406 opp-peak-kBps = <3072000 43008000>;
410 cpu4_opp_table: opp-table-cpu4 {
411 compatible = "operating-points-v2";
412 opp-shared;
414 cpu4_opp1: opp-710400000 {
415 opp-hz = /bits/ 64 <710400000>;
416 opp-peak-kBps = <1804000 15974400>;
419 cpu4_opp2: opp-825600000 {
420 opp-hz = /bits/ 64 <825600000>;
421 opp-peak-kBps = <2188000 19660800>;
424 cpu4_opp3: opp-940800000 {
425 opp-hz = /bits/ 64 <940800000>;
426 opp-peak-kBps = <2188000 22732800>;
429 cpu4_opp4: opp-1056000000 {
430 opp-hz = /bits/ 64 <1056000000>;
431 opp-peak-kBps = <3072000 25804800>;
434 cpu4_opp5: opp-1171200000 {
435 opp-hz = /bits/ 64 <1171200000>;
436 opp-peak-kBps = <3072000 31948800>;
439 cpu4_opp6: opp-1286400000 {
440 opp-hz = /bits/ 64 <1286400000>;
441 opp-peak-kBps = <4068000 31948800>;
444 cpu4_opp7: opp-1401600000 {
445 opp-hz = /bits/ 64 <1401600000>;
446 opp-peak-kBps = <4068000 31948800>;
449 cpu4_opp8: opp-1497600000 {
450 opp-hz = /bits/ 64 <1497600000>;
451 opp-peak-kBps = <4068000 40550400>;
454 cpu4_opp9: opp-1612800000 {
455 opp-hz = /bits/ 64 <1612800000>;
456 opp-peak-kBps = <4068000 40550400>;
459 cpu4_opp10: opp-1708800000 {
460 opp-hz = /bits/ 64 <1708800000>;
461 opp-peak-kBps = <4068000 43008000>;
464 cpu4_opp11: opp-1804800000 {
465 opp-hz = /bits/ 64 <1804800000>;
466 opp-peak-kBps = <6220000 43008000>;
469 cpu4_opp12: opp-1920000000 {
470 opp-hz = /bits/ 64 <1920000000>;
471 opp-peak-kBps = <6220000 49152000>;
474 cpu4_opp13: opp-2016000000 {
475 opp-hz = /bits/ 64 <2016000000>;
476 opp-peak-kBps = <7216000 49152000>;
479 cpu4_opp14: opp-2131200000 {
480 opp-hz = /bits/ 64 <2131200000>;
481 opp-peak-kBps = <8368000 49152000>;
484 cpu4_opp15: opp-2227200000 {
485 opp-hz = /bits/ 64 <2227200000>;
486 opp-peak-kBps = <8368000 51609600>;
489 cpu4_opp16: opp-2323200000 {
490 opp-hz = /bits/ 64 <2323200000>;
491 opp-peak-kBps = <8368000 51609600>;
494 cpu4_opp17: opp-2419200000 {
495 opp-hz = /bits/ 64 <2419200000>;
496 opp-peak-kBps = <8368000 51609600>;
500 cpu7_opp_table: opp-table-cpu7 {
501 compatible = "operating-points-v2";
502 opp-shared;
504 cpu7_opp1: opp-825600000 {
505 opp-hz = /bits/ 64 <825600000>;
506 opp-peak-kBps = <2188000 19660800>;
509 cpu7_opp2: opp-940800000 {
510 opp-hz = /bits/ 64 <940800000>;
511 opp-peak-kBps = <2188000 22732800>;
514 cpu7_opp3: opp-1056000000 {
515 opp-hz = /bits/ 64 <1056000000>;
516 opp-peak-kBps = <3072000 25804800>;
519 cpu7_opp4: opp-1171200000 {
520 opp-hz = /bits/ 64 <1171200000>;
521 opp-peak-kBps = <3072000 31948800>;
524 cpu7_opp5: opp-1286400000 {
525 opp-hz = /bits/ 64 <1286400000>;
526 opp-peak-kBps = <4068000 31948800>;
529 cpu7_opp6: opp-1401600000 {
530 opp-hz = /bits/ 64 <1401600000>;
531 opp-peak-kBps = <4068000 31948800>;
534 cpu7_opp7: opp-1497600000 {
535 opp-hz = /bits/ 64 <1497600000>;
536 opp-peak-kBps = <4068000 40550400>;
539 cpu7_opp8: opp-1612800000 {
540 opp-hz = /bits/ 64 <1612800000>;
541 opp-peak-kBps = <4068000 40550400>;
544 cpu7_opp9: opp-1708800000 {
545 opp-hz = /bits/ 64 <1708800000>;
546 opp-peak-kBps = <4068000 43008000>;
549 cpu7_opp10: opp-1804800000 {
550 opp-hz = /bits/ 64 <1804800000>;
551 opp-peak-kBps = <6220000 43008000>;
554 cpu7_opp11: opp-1920000000 {
555 opp-hz = /bits/ 64 <1920000000>;
556 opp-peak-kBps = <6220000 49152000>;
559 cpu7_opp12: opp-2016000000 {
560 opp-hz = /bits/ 64 <2016000000>;
561 opp-peak-kBps = <7216000 49152000>;
564 cpu7_opp13: opp-2131200000 {
565 opp-hz = /bits/ 64 <2131200000>;
566 opp-peak-kBps = <8368000 49152000>;
569 cpu7_opp14: opp-2227200000 {
570 opp-hz = /bits/ 64 <2227200000>;
571 opp-peak-kBps = <8368000 51609600>;
574 cpu7_opp15: opp-2323200000 {
575 opp-hz = /bits/ 64 <2323200000>;
576 opp-peak-kBps = <8368000 51609600>;
579 cpu7_opp16: opp-2419200000 {
580 opp-hz = /bits/ 64 <2419200000>;
581 opp-peak-kBps = <8368000 51609600>;
584 cpu7_opp17: opp-2534400000 {
585 opp-hz = /bits/ 64 <2534400000>;
586 opp-peak-kBps = <8368000 51609600>;
589 cpu7_opp18: opp-2649600000 {
590 opp-hz = /bits/ 64 <2649600000>;
591 opp-peak-kBps = <8368000 51609600>;
594 cpu7_opp19: opp-2745600000 {
595 opp-hz = /bits/ 64 <2745600000>;
596 opp-peak-kBps = <8368000 51609600>;
599 cpu7_opp20: opp-2841600000 {
600 opp-hz = /bits/ 64 <2841600000>;
601 opp-peak-kBps = <8368000 51609600>;
607 compatible = "qcom,scm-sm8150", "qcom,scm";
608 #reset-cells = <1>;
619 compatible = "arm,armv8-pmuv3";
624 compatible = "arm,psci-1.0";
627 CPU_PD0: power-domain-cpu0 {
628 #power-domain-cells = <0>;
629 power-domains = <&CLUSTER_PD>;
630 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
633 CPU_PD1: power-domain-cpu1 {
634 #power-domain-cells = <0>;
635 power-domains = <&CLUSTER_PD>;
636 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
639 CPU_PD2: power-domain-cpu2 {
640 #power-domain-cells = <0>;
641 power-domains = <&CLUSTER_PD>;
642 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
645 CPU_PD3: power-domain-cpu3 {
646 #power-domain-cells = <0>;
647 power-domains = <&CLUSTER_PD>;
648 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
651 CPU_PD4: power-domain-cpu4 {
652 #power-domain-cells = <0>;
653 power-domains = <&CLUSTER_PD>;
654 domain-idle-states = <&BIG_CPU_SLEEP_0>;
657 CPU_PD5: power-domain-cpu5 {
658 #power-domain-cells = <0>;
659 power-domains = <&CLUSTER_PD>;
660 domain-idle-states = <&BIG_CPU_SLEEP_0>;
663 CPU_PD6: power-domain-cpu6 {
664 #power-domain-cells = <0>;
665 power-domains = <&CLUSTER_PD>;
666 domain-idle-states = <&BIG_CPU_SLEEP_0>;
669 CPU_PD7: power-domain-cpu7 {
670 #power-domain-cells = <0>;
671 power-domains = <&CLUSTER_PD>;
672 domain-idle-states = <&BIG_CPU_SLEEP_0>;
675 CLUSTER_PD: power-domain-cpu-cluster0 {
676 #power-domain-cells = <0>;
677 domain-idle-states = <&CLUSTER_SLEEP_0>;
681 reserved-memory {
682 #address-cells = <2>;
683 #size-cells = <2>;
688 no-map;
693 no-map;
698 no-map;
702 compatible = "qcom,cmd-db";
704 no-map;
709 no-map;
714 no-map;
718 compatible = "qcom,rmtfs-mem";
720 no-map;
722 qcom,client-id = <1>;
728 no-map;
733 no-map;
738 no-map;
743 no-map;
748 no-map;
753 no-map;
758 no-map;
763 no-map;
768 no-map;
773 no-map;
778 no-map;
783 no-map;
788 no-map;
794 memory-region = <&smem_mem>;
798 smp2p-cdsp {
806 qcom,local-pid = <0>;
807 qcom,remote-pid = <5>;
809 cdsp_smp2p_out: master-kernel {
810 qcom,entry-name = "master-kernel";
811 #qcom,smem-state-cells = <1>;
814 cdsp_smp2p_in: slave-kernel {
815 qcom,entry-name = "slave-kernel";
817 interrupt-controller;
818 #interrupt-cells = <2>;
822 smp2p-lpass {
830 qcom,local-pid = <0>;
831 qcom,remote-pid = <2>;
833 adsp_smp2p_out: master-kernel {
834 qcom,entry-name = "master-kernel";
835 #qcom,smem-state-cells = <1>;
838 adsp_smp2p_in: slave-kernel {
839 qcom,entry-name = "slave-kernel";
841 interrupt-controller;
842 #interrupt-cells = <2>;
846 smp2p-mpss {
854 qcom,local-pid = <0>;
855 qcom,remote-pid = <1>;
857 modem_smp2p_out: master-kernel {
858 qcom,entry-name = "master-kernel";
859 #qcom,smem-state-cells = <1>;
862 modem_smp2p_in: slave-kernel {
863 qcom,entry-name = "slave-kernel";
865 interrupt-controller;
866 #interrupt-cells = <2>;
870 smp2p-slpi {
878 qcom,local-pid = <0>;
879 qcom,remote-pid = <3>;
881 slpi_smp2p_out: master-kernel {
882 qcom,entry-name = "master-kernel";
883 #qcom,smem-state-cells = <1>;
886 slpi_smp2p_in: slave-kernel {
887 qcom,entry-name = "slave-kernel";
889 interrupt-controller;
890 #interrupt-cells = <2>;
895 #address-cells = <2>;
896 #size-cells = <2>;
898 dma-ranges = <0 0 0 0 0x10 0>;
899 compatible = "simple-bus";
901 gcc: clock-controller@100000 {
902 compatible = "qcom,gcc-sm8150";
904 #clock-cells = <1>;
905 #reset-cells = <1>;
906 #power-domain-cells = <1>;
907 clock-names = "bi_tcxo",
913 gpi_dma0: dma-controller@800000 {
914 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
929 dma-channels = <13>;
930 dma-channel-mask = <0xfa>;
932 #dma-cells = <3>;
937 compatible = "qcom,sm8150-ethqos";
940 reg-names = "stmmaceth", "rgmii";
941 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
948 interrupt-names = "macirq", "eth_lpi";
950 power-domains = <&gcc EMAC_GDSC>;
956 rx-fifo-depth = <4096>;
957 tx-fifo-depth = <4096>;
963 compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
965 #address-cells = <1>;
966 #size-cells = <1>;
975 compatible = "qcom,geni-se-qup";
977 clock-names = "m-ahb", "s-ahb";
981 #address-cells = <2>;
982 #size-cells = <2>;
987 compatible = "qcom,geni-i2c";
989 clock-names = "se";
993 dma-names = "tx", "rx";
994 pinctrl-names = "default";
995 pinctrl-0 = <&qup_i2c0_default>;
997 #address-cells = <1>;
998 #size-cells = <0>;
1003 compatible = "qcom,geni-spi";
1005 reg-names = "se";
1006 clock-names = "se";
1010 dma-names = "tx", "rx";
1011 pinctrl-names = "default";
1012 pinctrl-0 = <&qup_spi0_default>;
1014 spi-max-frequency = <50000000>;
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1021 compatible = "qcom,geni-i2c";
1023 clock-names = "se";
1027 dma-names = "tx", "rx";
1028 pinctrl-names = "default";
1029 pinctrl-0 = <&qup_i2c1_default>;
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1037 compatible = "qcom,geni-spi";
1039 reg-names = "se";
1040 clock-names = "se";
1044 dma-names = "tx", "rx";
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&qup_spi1_default>;
1048 spi-max-frequency = <50000000>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1055 compatible = "qcom,geni-i2c";
1057 clock-names = "se";
1061 dma-names = "tx", "rx";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_i2c2_default>;
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 compatible = "qcom,geni-spi";
1073 reg-names = "se";
1074 clock-names = "se";
1078 dma-names = "tx", "rx";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&qup_spi2_default>;
1082 spi-max-frequency = <50000000>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1089 compatible = "qcom,geni-i2c";
1091 clock-names = "se";
1095 dma-names = "tx", "rx";
1096 pinctrl-names = "default";
1097 pinctrl-0 = <&qup_i2c3_default>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1105 compatible = "qcom,geni-spi";
1107 reg-names = "se";
1108 clock-names = "se";
1112 dma-names = "tx", "rx";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&qup_spi3_default>;
1116 spi-max-frequency = <50000000>;
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1123 compatible = "qcom,geni-i2c";
1125 clock-names = "se";
1129 dma-names = "tx", "rx";
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&qup_i2c4_default>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1139 compatible = "qcom,geni-spi";
1141 reg-names = "se";
1142 clock-names = "se";
1146 dma-names = "tx", "rx";
1147 pinctrl-names = "default";
1148 pinctrl-0 = <&qup_spi4_default>;
1150 spi-max-frequency = <50000000>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1157 compatible = "qcom,geni-i2c";
1159 clock-names = "se";
1163 dma-names = "tx", "rx";
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&qup_i2c5_default>;
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1173 compatible = "qcom,geni-spi";
1175 reg-names = "se";
1176 clock-names = "se";
1180 dma-names = "tx", "rx";
1181 pinctrl-names = "default";
1182 pinctrl-0 = <&qup_spi5_default>;
1184 spi-max-frequency = <50000000>;
1185 #address-cells = <1>;
1186 #size-cells = <0>;
1191 compatible = "qcom,geni-i2c";
1193 clock-names = "se";
1197 dma-names = "tx", "rx";
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_i2c6_default>;
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1207 compatible = "qcom,geni-spi";
1209 reg-names = "se";
1210 clock-names = "se";
1214 dma-names = "tx", "rx";
1215 pinctrl-names = "default";
1216 pinctrl-0 = <&qup_spi6_default>;
1218 spi-max-frequency = <50000000>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1225 compatible = "qcom,geni-i2c";
1227 clock-names = "se";
1231 dma-names = "tx", "rx";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_i2c7_default>;
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1241 compatible = "qcom,geni-spi";
1243 reg-names = "se";
1244 clock-names = "se";
1248 dma-names = "tx", "rx";
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_spi7_default>;
1252 spi-max-frequency = <50000000>;
1253 #address-cells = <1>;
1254 #size-cells = <0>;
1259 gpi_dma1: dma-controller@a00000 {
1260 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1275 dma-channels = <13>;
1276 dma-channel-mask = <0xfa>;
1278 #dma-cells = <3>;
1283 compatible = "qcom,geni-se-qup";
1285 clock-names = "m-ahb", "s-ahb";
1289 #address-cells = <2>;
1290 #size-cells = <2>;
1295 compatible = "qcom,geni-i2c";
1297 clock-names = "se";
1301 dma-names = "tx", "rx";
1302 pinctrl-names = "default";
1303 pinctrl-0 = <&qup_i2c8_default>;
1305 #address-cells = <1>;
1306 #size-cells = <0>;
1311 compatible = "qcom,geni-spi";
1313 reg-names = "se";
1314 clock-names = "se";
1318 dma-names = "tx", "rx";
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_spi8_default>;
1322 spi-max-frequency = <50000000>;
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1329 compatible = "qcom,geni-i2c";
1331 clock-names = "se";
1335 dma-names = "tx", "rx";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c9_default>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1345 compatible = "qcom,geni-spi";
1347 reg-names = "se";
1348 clock-names = "se";
1352 dma-names = "tx", "rx";
1353 pinctrl-names = "default";
1354 pinctrl-0 = <&qup_spi9_default>;
1356 spi-max-frequency = <50000000>;
1357 #address-cells = <1>;
1358 #size-cells = <0>;
1363 compatible = "qcom,geni-uart";
1366 clock-names = "se";
1367 pinctrl-0 = <&qup_uart9_default>;
1368 pinctrl-names = "default";
1374 compatible = "qcom,geni-i2c";
1376 clock-names = "se";
1380 dma-names = "tx", "rx";
1381 pinctrl-names = "default";
1382 pinctrl-0 = <&qup_i2c10_default>;
1384 #address-cells = <1>;
1385 #size-cells = <0>;
1390 compatible = "qcom,geni-spi";
1392 reg-names = "se";
1393 clock-names = "se";
1397 dma-names = "tx", "rx";
1398 pinctrl-names = "default";
1399 pinctrl-0 = <&qup_spi10_default>;
1401 spi-max-frequency = <50000000>;
1402 #address-cells = <1>;
1403 #size-cells = <0>;
1408 compatible = "qcom,geni-i2c";
1410 clock-names = "se";
1414 dma-names = "tx", "rx";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_i2c11_default>;
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1424 compatible = "qcom,geni-spi";
1426 reg-names = "se";
1427 clock-names = "se";
1431 dma-names = "tx", "rx";
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&qup_spi11_default>;
1435 spi-max-frequency = <50000000>;
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1442 compatible = "qcom,geni-debug-uart";
1444 clock-names = "se";
1451 compatible = "qcom,geni-i2c";
1453 clock-names = "se";
1457 dma-names = "tx", "rx";
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&qup_i2c12_default>;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1467 compatible = "qcom,geni-spi";
1469 reg-names = "se";
1470 clock-names = "se";
1474 dma-names = "tx", "rx";
1475 pinctrl-names = "default";
1476 pinctrl-0 = <&qup_spi12_default>;
1478 spi-max-frequency = <50000000>;
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1485 compatible = "qcom,geni-i2c";
1487 clock-names = "se";
1491 dma-names = "tx", "rx";
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&qup_i2c16_default>;
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1501 compatible = "qcom,geni-spi";
1503 reg-names = "se";
1504 clock-names = "se";
1508 dma-names = "tx", "rx";
1509 pinctrl-names = "default";
1510 pinctrl-0 = <&qup_spi16_default>;
1512 spi-max-frequency = <50000000>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1519 gpi_dma2: dma-controller@c00000 {
1520 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma";
1535 dma-channels = <13>;
1536 dma-channel-mask = <0xfa>;
1538 #dma-cells = <3>;
1543 compatible = "qcom,geni-se-qup";
1546 clock-names = "m-ahb", "s-ahb";
1550 #address-cells = <2>;
1551 #size-cells = <2>;
1556 compatible = "qcom,geni-i2c";
1558 clock-names = "se";
1562 dma-names = "tx", "rx";
1563 pinctrl-names = "default";
1564 pinctrl-0 = <&qup_i2c17_default>;
1566 #address-cells = <1>;
1567 #size-cells = <0>;
1572 compatible = "qcom,geni-spi";
1574 reg-names = "se";
1575 clock-names = "se";
1579 dma-names = "tx", "rx";
1580 pinctrl-names = "default";
1581 pinctrl-0 = <&qup_spi17_default>;
1583 spi-max-frequency = <50000000>;
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1590 compatible = "qcom,geni-i2c";
1592 clock-names = "se";
1596 dma-names = "tx", "rx";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_i2c18_default>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1606 compatible = "qcom,geni-spi";
1608 reg-names = "se";
1609 clock-names = "se";
1613 dma-names = "tx", "rx";
1614 pinctrl-names = "default";
1615 pinctrl-0 = <&qup_spi18_default>;
1617 spi-max-frequency = <50000000>;
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1624 compatible = "qcom,geni-i2c";
1626 clock-names = "se";
1630 dma-names = "tx", "rx";
1631 pinctrl-names = "default";
1632 pinctrl-0 = <&qup_i2c19_default>;
1634 #address-cells = <1>;
1635 #size-cells = <0>;
1640 compatible = "qcom,geni-spi";
1642 reg-names = "se";
1643 clock-names = "se";
1647 dma-names = "tx", "rx";
1648 pinctrl-names = "default";
1649 pinctrl-0 = <&qup_spi19_default>;
1651 spi-max-frequency = <50000000>;
1652 #address-cells = <1>;
1653 #size-cells = <0>;
1658 compatible = "qcom,geni-i2c";
1660 clock-names = "se";
1664 dma-names = "tx", "rx";
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_i2c13_default>;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1674 compatible = "qcom,geni-spi";
1676 reg-names = "se";
1677 clock-names = "se";
1681 dma-names = "tx", "rx";
1682 pinctrl-names = "default";
1683 pinctrl-0 = <&qup_spi13_default>;
1685 spi-max-frequency = <50000000>;
1686 #address-cells = <1>;
1687 #size-cells = <0>;
1692 compatible = "qcom,geni-i2c";
1694 clock-names = "se";
1698 dma-names = "tx", "rx";
1699 pinctrl-names = "default";
1700 pinctrl-0 = <&qup_i2c14_default>;
1702 #address-cells = <1>;
1703 #size-cells = <0>;
1708 compatible = "qcom,geni-spi";
1710 reg-names = "se";
1711 clock-names = "se";
1715 dma-names = "tx", "rx";
1716 pinctrl-names = "default";
1717 pinctrl-0 = <&qup_spi14_default>;
1719 spi-max-frequency = <50000000>;
1720 #address-cells = <1>;
1721 #size-cells = <0>;
1726 compatible = "qcom,geni-i2c";
1728 clock-names = "se";
1732 dma-names = "tx", "rx";
1733 pinctrl-names = "default";
1734 pinctrl-0 = <&qup_i2c15_default>;
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1742 compatible = "qcom,geni-spi";
1744 reg-names = "se";
1745 clock-names = "se";
1749 dma-names = "tx", "rx";
1750 pinctrl-names = "default";
1751 pinctrl-0 = <&qup_spi15_default>;
1753 spi-max-frequency = <50000000>;
1754 #address-cells = <1>;
1755 #size-cells = <0>;
1761 compatible = "qcom,sm8150-config-noc";
1763 #interconnect-cells = <2>;
1764 qcom,bcm-voters = <&apps_bcm_voter>;
1768 compatible = "qcom,sm8150-system-noc";
1770 #interconnect-cells = <2>;
1771 qcom,bcm-voters = <&apps_bcm_voter>;
1775 compatible = "qcom,sm8150-mc-virt";
1777 #interconnect-cells = <2>;
1778 qcom,bcm-voters = <&apps_bcm_voter>;
1782 compatible = "qcom,sm8150-aggre1-noc";
1784 #interconnect-cells = <2>;
1785 qcom,bcm-voters = <&apps_bcm_voter>;
1789 compatible = "qcom,sm8150-aggre2-noc";
1791 #interconnect-cells = <2>;
1792 qcom,bcm-voters = <&apps_bcm_voter>;
1796 compatible = "qcom,sm8150-compute-noc";
1798 #interconnect-cells = <2>;
1799 qcom,bcm-voters = <&apps_bcm_voter>;
1803 compatible = "qcom,sm8150-mmss-noc";
1805 #interconnect-cells = <2>;
1806 qcom,bcm-voters = <&apps_bcm_voter>;
1809 system-cache-controller@9200000 {
1810 compatible = "qcom,sm8150-llcc";
1814 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
1820 compatible = "qcom,sm8150-dcc", "qcom,dcc";
1826 compatible = "qcom,pcie-sm8150";
1832 reg-names = "parf", "dbi", "elbi", "atu", "config";
1834 linux,pci-domain = <0>;
1835 bus-range = <0x00 0xff>;
1836 num-lanes = <1>;
1838 #address-cells = <3>;
1839 #size-cells = <2>;
1845 interrupt-names = "msi";
1846 #interrupt-cells = <1>;
1847 interrupt-map-mask = <0 0 0 0x7>;
1848 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1860 clock-names = "pipe",
1868 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1872 reset-names = "pci";
1874 power-domains = <&gcc PCIE_0_GDSC>;
1877 phy-names = "pciephy";
1879 perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
1880 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
1882 pinctrl-names = "default";
1883 pinctrl-0 = <&pcie0_default_state>;
1889 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
1891 #address-cells = <2>;
1892 #size-cells = <2>;
1897 clock-names = "aux", "cfg_ahb", "refgen";
1900 reset-names = "phy";
1902 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1903 assigned-clock-rates = <100000000>;
1913 clock-names = "pipe0";
1915 #phy-cells = <0>;
1916 clock-output-names = "pcie_0_pipe_clk";
1921 compatible = "qcom,pcie-sm8150";
1927 reg-names = "parf", "dbi", "elbi", "atu", "config";
1929 linux,pci-domain = <1>;
1930 bus-range = <0x00 0xff>;
1931 num-lanes = <2>;
1933 #address-cells = <3>;
1934 #size-cells = <2>;
1940 interrupt-names = "msi";
1941 #interrupt-cells = <1>;
1942 interrupt-map-mask = <0 0 0 0x7>;
1943 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1955 clock-names = "pipe",
1963 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1964 assigned-clock-rates = <19200000>;
1966 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1970 reset-names = "pci";
1972 power-domains = <&gcc PCIE_1_GDSC>;
1975 phy-names = "pciephy";
1977 perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
1978 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
1980 pinctrl-names = "default";
1981 pinctrl-0 = <&pcie1_default_state>;
1987 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
1989 #address-cells = <2>;
1990 #size-cells = <2>;
1995 clock-names = "aux", "cfg_ahb", "refgen";
1998 reset-names = "phy";
2000 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2001 assigned-clock-rates = <100000000>;
2013 clock-names = "pipe0";
2015 #phy-cells = <0>;
2016 clock-output-names = "pcie_1_pipe_clk";
2021 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
2022 "jedec,ufs-2.0";
2025 reg-names = "std", "ice";
2028 phy-names = "ufsphy";
2029 lanes-per-direction = <2>;
2030 #reset-cells = <1>;
2032 reset-names = "rst";
2036 clock-names =
2056 freq-table-hz =
2071 compatible = "qcom,sm8150-qmp-ufs-phy";
2073 #address-cells = <2>;
2074 #size-cells = <2>;
2076 clock-names = "ref",
2081 power-domains = <&gcc UFS_PHY_GDSC>;
2084 reset-names = "ufsphy";
2093 #phy-cells = <0>;
2097 cryptobam: dma-controller@1dc4000 {
2098 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2101 #dma-cells = <1>;
2103 qcom,controlled-remotely;
2104 num-channels = <8>;
2105 qcom,num-ees = <2>;
2114 compatible = "qcom,sm8150-qce", "qcom,qce";
2117 dma-names = "rx", "tx";
2124 interconnect-names = "memory";
2128 compatible = "qcom,tcsr-mutex";
2130 #hwlock-cells = <1>;
2134 compatible = "qcom,sm8150-tcsr", "syscon";
2139 compatible = "qcom,sm8150-slpi-pas";
2142 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
2147 interrupt-names = "wdog", "fatal", "ready",
2148 "handover", "stop-ack";
2151 clock-names = "xo";
2153 power-domains = <&rpmhpd SM8150_LCX>,
2155 power-domain-names = "lcx", "lmx";
2157 memory-region = <&slpi_mem>;
2161 qcom,smem-states = <&slpi_smp2p_out 0>;
2162 qcom,smem-state-names = "stop";
2166 glink-edge {
2169 qcom,remote-pid = <3>;
2174 qcom,glink-channels = "fastrpcglink-apps-dsp";
2176 qcom,non-secure-domain;
2177 #address-cells = <1>;
2178 #size-cells = <0>;
2180 compute-cb@1 {
2181 compatible = "qcom,fastrpc-compute-cb";
2186 compute-cb@2 {
2187 compatible = "qcom,fastrpc-compute-cb";
2192 compute-cb@3 {
2193 compatible = "qcom,fastrpc-compute-cb";
2196 /* note: shared-cb = <4> in downstream */
2203 compatible = "qcom,adreno-640.1", "qcom,adreno";
2205 reg-names = "kgsl_3d0_reg_memory";
2211 operating-points-v2 = <&gpu_opp_table>;
2215 nvmem-cells = <&gpu_speed_bin>;
2216 nvmem-cell-names = "speed_bin";
2220 zap-shader {
2221 memory-region = <&gpu_mem>;
2224 gpu_opp_table: opp-table {
2225 compatible = "operating-points-v2";
2227 opp-675000000 {
2228 opp-hz = /bits/ 64 <675000000>;
2229 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2230 opp-supported-hw = <0x2>;
2233 opp-585000000 {
2234 opp-hz = /bits/ 64 <585000000>;
2235 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2236 opp-supported-hw = <0x3>;
2239 opp-499200000 {
2240 opp-hz = /bits/ 64 <499200000>;
2241 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2242 opp-supported-hw = <0x3>;
2245 opp-427000000 {
2246 opp-hz = /bits/ 64 <427000000>;
2247 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2248 opp-supported-hw = <0x3>;
2251 opp-345000000 {
2252 opp-hz = /bits/ 64 <345000000>;
2253 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2254 opp-supported-hw = <0x3>;
2257 opp-257000000 {
2258 opp-hz = /bits/ 64 <257000000>;
2259 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2260 opp-supported-hw = <0x3>;
2266 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2271 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2275 interrupt-names = "hfi", "gmu";
2282 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2284 power-domains = <&gpucc GPU_CX_GDSC>,
2286 power-domain-names = "cx", "gx";
2290 operating-points-v2 = <&gmu_opp_table>;
2294 gmu_opp_table: opp-table {
2295 compatible = "operating-points-v2";
2297 opp-200000000 {
2298 opp-hz = /bits/ 64 <200000000>;
2299 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2304 gpucc: clock-controller@2c90000 {
2305 compatible = "qcom,sm8150-gpucc";
2310 clock-names = "bi_tcxo",
2313 #clock-cells = <1>;
2314 #reset-cells = <1>;
2315 #power-domain-cells = <1>;
2319 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu",
2320 "qcom,smmu-500", "arm,mmu-500";
2322 #iommu-cells = <2>;
2323 #global-interrupts = <1>;
2336 clock-names = "ahb", "bus", "iface";
2338 power-domains = <&gpucc GPU_CX_GDSC>;
2342 compatible = "qcom,sm8150-pinctrl";
2347 reg-names = "west", "east", "north", "south";
2349 gpio-ranges = <&tlmm 0 0 176>;
2350 gpio-controller;
2351 #gpio-cells = <2>;
2352 interrupt-controller;
2353 #interrupt-cells = <2>;
2354 wakeup-parent = <&pdc>;
2356 qup_i2c0_default: qup-i2c0-default-state {
2359 drive-strength = <0x02>;
2360 bias-disable;
2363 qup_spi0_default: qup-spi0-default-state {
2366 drive-strength = <6>;
2367 bias-disable;
2370 qup_i2c1_default: qup-i2c1-default-state {
2373 drive-strength = <2>;
2374 bias-disable;
2377 qup_spi1_default: qup-spi1-default-state {
2380 drive-strength = <6>;
2381 bias-disable;
2384 qup_i2c2_default: qup-i2c2-default-state {
2387 drive-strength = <2>;
2388 bias-disable;
2391 qup_spi2_default: qup-spi2-default-state {
2394 drive-strength = <6>;
2395 bias-disable;
2398 qup_i2c3_default: qup-i2c3-default-state {
2401 drive-strength = <2>;
2402 bias-disable;
2405 qup_spi3_default: qup-spi3-default-state {
2408 drive-strength = <6>;
2409 bias-disable;
2412 qup_i2c4_default: qup-i2c4-default-state {
2415 drive-strength = <2>;
2416 bias-disable;
2419 qup_spi4_default: qup-spi4-default-state {
2422 drive-strength = <6>;
2423 bias-disable;
2426 qup_i2c5_default: qup-i2c5-default-state {
2429 drive-strength = <2>;
2430 bias-disable;
2433 qup_spi5_default: qup-spi5-default-state {
2436 drive-strength = <6>;
2437 bias-disable;
2440 qup_i2c6_default: qup-i2c6-default-state {
2443 drive-strength = <2>;
2444 bias-disable;
2447 qup_spi6_default: qup-spi6_default-state {
2450 drive-strength = <6>;
2451 bias-disable;
2454 qup_i2c7_default: qup-i2c7-default-state {
2457 drive-strength = <2>;
2458 bias-disable;
2461 qup_spi7_default: qup-spi7_default-state {
2464 drive-strength = <6>;
2465 bias-disable;
2468 qup_i2c8_default: qup-i2c8-default-state {
2471 drive-strength = <2>;
2472 bias-disable;
2475 qup_spi8_default: qup-spi8-default-state {
2478 drive-strength = <6>;
2479 bias-disable;
2482 qup_i2c9_default: qup-i2c9-default-state {
2485 drive-strength = <2>;
2486 bias-disable;
2489 qup_spi9_default: qup-spi9-default-state {
2492 drive-strength = <6>;
2493 bias-disable;
2496 qup_uart9_default: qup-uart9-default-state {
2499 drive-strength = <2>;
2500 bias-disable;
2503 qup_i2c10_default: qup-i2c10-default-state {
2506 drive-strength = <2>;
2507 bias-disable;
2510 qup_spi10_default: qup-spi10-default-state {
2513 drive-strength = <6>;
2514 bias-disable;
2517 qup_i2c11_default: qup-i2c11-default-state {
2520 drive-strength = <2>;
2521 bias-disable;
2524 qup_spi11_default: qup-spi11-default-state {
2527 drive-strength = <6>;
2528 bias-disable;
2531 qup_i2c12_default: qup-i2c12-default-state {
2534 drive-strength = <2>;
2535 bias-disable;
2538 qup_spi12_default: qup-spi12-default-state {
2541 drive-strength = <6>;
2542 bias-disable;
2545 qup_i2c13_default: qup-i2c13-default-state {
2548 drive-strength = <2>;
2549 bias-disable;
2552 qup_spi13_default: qup-spi13-default-state {
2555 drive-strength = <6>;
2556 bias-disable;
2559 qup_i2c14_default: qup-i2c14-default-state {
2562 drive-strength = <2>;
2563 bias-disable;
2566 qup_spi14_default: qup-spi14-default-state {
2569 drive-strength = <6>;
2570 bias-disable;
2573 qup_i2c15_default: qup-i2c15-default-state {
2576 drive-strength = <2>;
2577 bias-disable;
2580 qup_spi15_default: qup-spi15-default-state {
2583 drive-strength = <6>;
2584 bias-disable;
2587 qup_i2c16_default: qup-i2c16-default-state {
2590 drive-strength = <2>;
2591 bias-disable;
2594 qup_spi16_default: qup-spi16-default-state {
2597 drive-strength = <6>;
2598 bias-disable;
2601 qup_i2c17_default: qup-i2c17-default-state {
2604 drive-strength = <2>;
2605 bias-disable;
2608 qup_spi17_default: qup-spi17-default-state {
2611 drive-strength = <6>;
2612 bias-disable;
2615 qup_i2c18_default: qup-i2c18-default-state {
2618 drive-strength = <2>;
2619 bias-disable;
2622 qup_spi18_default: qup-spi18-default-state {
2625 drive-strength = <6>;
2626 bias-disable;
2629 qup_i2c19_default: qup-i2c19-default-state {
2632 drive-strength = <2>;
2633 bias-disable;
2636 qup_spi19_default: qup-spi19-default-state {
2639 drive-strength = <6>;
2640 bias-disable;
2643 pcie0_default_state: pcie0-default-state {
2644 perst-pins {
2647 drive-strength = <2>;
2648 bias-pull-down;
2651 clkreq-pins {
2654 drive-strength = <2>;
2655 bias-pull-up;
2658 wake-pins {
2661 drive-strength = <2>;
2662 bias-pull-up;
2666 pcie1_default_state: pcie1-default-state {
2667 perst-pins {
2670 drive-strength = <2>;
2671 bias-pull-down;
2674 clkreq-pins {
2677 drive-strength = <2>;
2678 bias-pull-up;
2681 wake-pins {
2684 drive-strength = <2>;
2685 bias-pull-up;
2691 compatible = "qcom,sm8150-mpss-pas";
2694 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2700 interrupt-names = "wdog", "fatal", "ready", "handover",
2701 "stop-ack", "shutdown-ack";
2704 clock-names = "xo";
2706 power-domains = <&rpmhpd SM8150_CX>,
2708 power-domain-names = "cx", "mss";
2710 memory-region = <&mpss_mem>;
2714 qcom,smem-states = <&modem_smp2p_out 0>;
2715 qcom,smem-state-names = "stop";
2719 glink-edge {
2722 qcom,remote-pid = <1>;
2728 compatible = "arm,coresight-stm", "arm,primecell";
2731 reg-names = "stm-base", "stm-stimulus-base";
2734 clock-names = "apb_pclk";
2736 out-ports {
2739 remote-endpoint = <&funnel0_in7>;
2746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2750 clock-names = "apb_pclk";
2752 out-ports {
2755 remote-endpoint = <&merge_funnel_in0>;
2760 in-ports {
2761 #address-cells = <1>;
2762 #size-cells = <0>;
2767 remote-endpoint = <&stm_out>;
2774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2778 clock-names = "apb_pclk";
2780 out-ports {
2783 remote-endpoint = <&merge_funnel_in1>;
2788 in-ports {
2789 #address-cells = <1>;
2790 #size-cells = <0>;
2795 remote-endpoint = <&swao_replicator_out>;
2802 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2806 clock-names = "apb_pclk";
2808 out-ports {
2811 remote-endpoint = <&merge_funnel_in2>;
2816 in-ports {
2817 #address-cells = <1>;
2818 #size-cells = <0>;
2823 remote-endpoint = <&apss_merge_funnel_out>;
2830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2834 clock-names = "apb_pclk";
2836 out-ports {
2839 remote-endpoint = <&etf_in>;
2844 in-ports {
2845 #address-cells = <1>;
2846 #size-cells = <0>;
2851 remote-endpoint = <&funnel0_out>;
2858 remote-endpoint = <&funnel1_out>;
2865 remote-endpoint = <&funnel2_out>;
2872 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2876 clock-names = "apb_pclk";
2878 out-ports {
2879 #address-cells = <1>;
2880 #size-cells = <0>;
2885 remote-endpoint = <&etr_in>;
2892 remote-endpoint = <&replicator1_in>;
2897 in-ports {
2900 remote-endpoint = <&etf_out>;
2907 compatible = "arm,coresight-tmc", "arm,primecell";
2911 clock-names = "apb_pclk";
2913 out-ports {
2916 remote-endpoint = <&replicator_in0>;
2921 in-ports {
2924 remote-endpoint = <&merge_funnel_out>;
2931 compatible = "arm,coresight-tmc", "arm,primecell";
2936 clock-names = "apb_pclk";
2937 arm,scatter-gather;
2939 in-ports {
2942 remote-endpoint = <&replicator_out0>;
2949 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2953 clock-names = "apb_pclk";
2955 out-ports {
2956 #address-cells = <1>;
2957 #size-cells = <0>;
2962 remote-endpoint = <&swao_funnel_in>;
2967 in-ports {
2968 #address-cells = <1>;
2969 #size-cells = <0>;
2974 remote-endpoint = <&replicator_out1>;
2981 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2985 clock-names = "apb_pclk";
2987 out-ports {
2990 remote-endpoint = <&swao_etf_in>;
2995 in-ports {
2996 #address-cells = <1>;
2997 #size-cells = <0>;
3002 remote-endpoint = <&replicator1_out>;
3009 compatible = "arm,coresight-tmc", "arm,primecell";
3013 clock-names = "apb_pclk";
3015 out-ports {
3018 remote-endpoint = <&swao_replicator_in>;
3023 in-ports {
3026 remote-endpoint = <&swao_funnel_out>;
3033 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3037 clock-names = "apb_pclk";
3038 qcom,replicator-loses-context;
3040 out-ports {
3043 remote-endpoint = <&funnel1_in4>;
3048 in-ports {
3051 remote-endpoint = <&swao_etf_out>;
3058 compatible = "arm,coresight-etm4x", "arm,primecell";
3064 clock-names = "apb_pclk";
3065 arm,coresight-loses-context-with-cpu;
3066 qcom,skip-power-up;
3068 out-ports {
3071 remote-endpoint = <&apss_funnel_in0>;
3078 compatible = "arm,coresight-etm4x", "arm,primecell";
3084 clock-names = "apb_pclk";
3085 arm,coresight-loses-context-with-cpu;
3086 qcom,skip-power-up;
3088 out-ports {
3091 remote-endpoint = <&apss_funnel_in1>;
3098 compatible = "arm,coresight-etm4x", "arm,primecell";
3104 clock-names = "apb_pclk";
3105 arm,coresight-loses-context-with-cpu;
3106 qcom,skip-power-up;
3108 out-ports {
3111 remote-endpoint = <&apss_funnel_in2>;
3118 compatible = "arm,coresight-etm4x", "arm,primecell";
3124 clock-names = "apb_pclk";
3125 arm,coresight-loses-context-with-cpu;
3126 qcom,skip-power-up;
3128 out-ports {
3131 remote-endpoint = <&apss_funnel_in3>;
3138 compatible = "arm,coresight-etm4x", "arm,primecell";
3144 clock-names = "apb_pclk";
3145 arm,coresight-loses-context-with-cpu;
3146 qcom,skip-power-up;
3148 out-ports {
3151 remote-endpoint = <&apss_funnel_in4>;
3158 compatible = "arm,coresight-etm4x", "arm,primecell";
3164 clock-names = "apb_pclk";
3165 arm,coresight-loses-context-with-cpu;
3166 qcom,skip-power-up;
3168 out-ports {
3171 remote-endpoint = <&apss_funnel_in5>;
3178 compatible = "arm,coresight-etm4x", "arm,primecell";
3184 clock-names = "apb_pclk";
3185 arm,coresight-loses-context-with-cpu;
3186 qcom,skip-power-up;
3188 out-ports {
3191 remote-endpoint = <&apss_funnel_in6>;
3198 compatible = "arm,coresight-etm4x", "arm,primecell";
3204 clock-names = "apb_pclk";
3205 arm,coresight-loses-context-with-cpu;
3206 qcom,skip-power-up;
3208 out-ports {
3211 remote-endpoint = <&apss_funnel_in7>;
3218 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3222 clock-names = "apb_pclk";
3224 out-ports {
3227 remote-endpoint = <&apss_merge_funnel_in>;
3232 in-ports {
3233 #address-cells = <1>;
3234 #size-cells = <0>;
3239 remote-endpoint = <&etm0_out>;
3246 remote-endpoint = <&etm1_out>;
3253 remote-endpoint = <&etm2_out>;
3260 remote-endpoint = <&etm3_out>;
3267 remote-endpoint = <&etm4_out>;
3274 remote-endpoint = <&etm5_out>;
3281 remote-endpoint = <&etm6_out>;
3288 remote-endpoint = <&etm7_out>;
3295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3299 clock-names = "apb_pclk";
3301 out-ports {
3304 remote-endpoint = <&funnel2_in2>;
3309 in-ports {
3312 remote-endpoint = <&apss_funnel_out>;
3319 compatible = "qcom,sm8150-cdsp-pas";
3322 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3327 interrupt-names = "wdog", "fatal", "ready",
3328 "handover", "stop-ack";
3331 clock-names = "xo";
3333 power-domains = <&rpmhpd SM8150_CX>;
3335 memory-region = <&cdsp_mem>;
3339 qcom,smem-states = <&cdsp_smp2p_out 0>;
3340 qcom,smem-state-names = "stop";
3344 glink-edge {
3347 qcom,remote-pid = <5>;
3352 qcom,glink-channels = "fastrpcglink-apps-dsp";
3354 qcom,non-secure-domain;
3355 #address-cells = <1>;
3356 #size-cells = <0>;
3358 compute-cb@1 {
3359 compatible = "qcom,fastrpc-compute-cb";
3364 compute-cb@2 {
3365 compatible = "qcom,fastrpc-compute-cb";
3370 compute-cb@3 {
3371 compatible = "qcom,fastrpc-compute-cb";
3376 compute-cb@4 {
3377 compatible = "qcom,fastrpc-compute-cb";
3382 compute-cb@5 {
3383 compatible = "qcom,fastrpc-compute-cb";
3388 compute-cb@6 {
3389 compatible = "qcom,fastrpc-compute-cb";
3394 compute-cb@7 {
3395 compatible = "qcom,fastrpc-compute-cb";
3400 compute-cb@8 {
3401 compatible = "qcom,fastrpc-compute-cb";
3412 compatible = "qcom,sm8150-usb-hs-phy",
3413 "qcom,usb-snps-hs-7nm-phy";
3416 #phy-cells = <0>;
3419 clock-names = "ref";
3425 compatible = "qcom,sm8150-usb-hs-phy",
3426 "qcom,usb-snps-hs-7nm-phy";
3429 #phy-cells = <0>;
3432 clock-names = "ref";
3438 compatible = "qcom,sm8150-qmp-usb3-phy";
3442 #address-cells = <2>;
3443 #size-cells = <2>;
3450 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3454 reset-names = "phy", "common";
3463 #clock-cells = <0>;
3464 #phy-cells = <0>;
3466 clock-names = "pipe0";
3467 clock-output-names = "usb3_phy_pipe_clk_src";
3472 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3475 #address-cells = <2>;
3476 #size-cells = <2>;
3483 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3487 reset-names = "phy", "common";
3494 #clock-cells = <0>;
3495 #phy-cells = <0>;
3497 clock-names = "pipe0";
3498 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3503 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
3508 interrupt-names = "hc_irq", "pwr_irq";
3513 clock-names = "iface", "core", "xo";
3515 qcom,dll-config = <0x0007642c>;
3516 qcom,ddr-config = <0x80040868>;
3517 power-domains = <&rpmhpd 0>;
3518 operating-points-v2 = <&sdhc2_opp_table>;
3522 sdhc2_opp_table: opp-table {
3523 compatible = "operating-points-v2";
3525 opp-19200000 {
3526 opp-hz = /bits/ 64 <19200000>;
3527 required-opps = <&rpmhpd_opp_min_svs>;
3530 opp-50000000 {
3531 opp-hz = /bits/ 64 <50000000>;
3532 required-opps = <&rpmhpd_opp_low_svs>;
3535 opp-100000000 {
3536 opp-hz = /bits/ 64 <100000000>;
3537 required-opps = <&rpmhpd_opp_svs>;
3540 opp-202000000 {
3541 opp-hz = /bits/ 64 <202000000>;
3542 required-opps = <&rpmhpd_opp_svs_l1>;
3548 compatible = "qcom,sm8150-dc-noc";
3550 #interconnect-cells = <2>;
3551 qcom,bcm-voters = <&apps_bcm_voter>;
3555 compatible = "qcom,sm8150-gem-noc";
3557 #interconnect-cells = <2>;
3558 qcom,bcm-voters = <&apps_bcm_voter>;
3562 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3565 #address-cells = <2>;
3566 #size-cells = <2>;
3568 dma-ranges;
3576 clock-names = "cfg_noc",
3583 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3585 assigned-clock-rates = <19200000>, <200000000>;
3591 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3594 power-domains = <&gcc USB30_PRIM_GDSC>;
3600 interconnect-names = "usb-ddr", "apps-usb";
3610 phy-names = "usb2-phy", "usb3-phy";
3615 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3618 #address-cells = <2>;
3619 #size-cells = <2>;
3621 dma-ranges;
3629 clock-names = "cfg_noc",
3636 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3638 assigned-clock-rates = <19200000>, <200000000>;
3644 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3647 power-domains = <&gcc USB30_SEC_GDSC>;
3653 interconnect-names = "usb-ddr", "apps-usb";
3663 phy-names = "usb2-phy", "usb3-phy";
3668 compatible = "qcom,sm8150-camnoc-virt";
3670 #interconnect-cells = <2>;
3671 qcom,bcm-voters = <&apps_bcm_voter>;
3674 mdss: display-subsystem@ae00000 {
3675 compatible = "qcom,sm8150-mdss";
3677 reg-names = "mdss";
3681 interconnect-names = "mdp0-mem", "mdp1-mem";
3683 power-domains = <&dispcc MDSS_GDSC>;
3689 clock-names = "iface", "bus", "nrt_bus", "core";
3692 interrupt-controller;
3693 #interrupt-cells = <1>;
3699 #address-cells = <2>;
3700 #size-cells = <2>;
3703 mdss_mdp: display-controller@ae01000 {
3704 compatible = "qcom,sm8150-dpu";
3707 reg-names = "mdp", "vbif";
3713 clock-names = "iface", "bus", "core", "vsync";
3715 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3716 assigned-clock-rates = <19200000>;
3718 operating-points-v2 = <&mdp_opp_table>;
3719 power-domains = <&rpmhpd SM8150_MMCX>;
3721 interrupt-parent = <&mdss>;
3725 #address-cells = <1>;
3726 #size-cells = <0>;
3731 remote-endpoint = <&mdss_dsi0_in>;
3738 remote-endpoint = <&mdss_dsi1_in>;
3743 mdp_opp_table: opp-table {
3744 compatible = "operating-points-v2";
3746 opp-171428571 {
3747 opp-hz = /bits/ 64 <171428571>;
3748 required-opps = <&rpmhpd_opp_low_svs>;
3751 opp-300000000 {
3752 opp-hz = /bits/ 64 <300000000>;
3753 required-opps = <&rpmhpd_opp_svs>;
3756 opp-345000000 {
3757 opp-hz = /bits/ 64 <345000000>;
3758 required-opps = <&rpmhpd_opp_svs_l1>;
3761 opp-460000000 {
3762 opp-hz = /bits/ 64 <460000000>;
3763 required-opps = <&rpmhpd_opp_nom>;
3769 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3771 reg-names = "dsi_ctrl";
3773 interrupt-parent = <&mdss>;
3782 clock-names = "byte",
3789 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
3791 assigned-clock-parents = <&mdss_dsi0_phy 0>,
3794 operating-points-v2 = <&dsi_opp_table>;
3795 power-domains = <&rpmhpd SM8150_MMCX>;
3801 #address-cells = <1>;
3802 #size-cells = <0>;
3805 #address-cells = <1>;
3806 #size-cells = <0>;
3811 remote-endpoint = <&dpu_intf1_out>;
3822 dsi_opp_table: opp-table {
3823 compatible = "operating-points-v2";
3825 opp-187500000 {
3826 opp-hz = /bits/ 64 <187500000>;
3827 required-opps = <&rpmhpd_opp_low_svs>;
3830 opp-300000000 {
3831 opp-hz = /bits/ 64 <300000000>;
3832 required-opps = <&rpmhpd_opp_svs>;
3835 opp-358000000 {
3836 opp-hz = /bits/ 64 <358000000>;
3837 required-opps = <&rpmhpd_opp_svs_l1>;
3843 compatible = "qcom,dsi-phy-7nm-8150";
3847 reg-names = "dsi_phy",
3851 #clock-cells = <1>;
3852 #phy-cells = <0>;
3856 clock-names = "iface", "ref";
3862 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3864 reg-names = "dsi_ctrl";
3866 interrupt-parent = <&mdss>;
3875 clock-names = "byte",
3882 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
3884 assigned-clock-parents = <&mdss_dsi1_phy 0>,
3887 operating-points-v2 = <&dsi_opp_table>;
3888 power-domains = <&rpmhpd SM8150_MMCX>;
3894 #address-cells = <1>;
3895 #size-cells = <0>;
3898 #address-cells = <1>;
3899 #size-cells = <0>;
3904 remote-endpoint = <&dpu_intf2_out>;
3917 compatible = "qcom,dsi-phy-7nm-8150";
3921 reg-names = "dsi_phy",
3925 #clock-cells = <1>;
3926 #phy-cells = <0>;
3930 clock-names = "iface", "ref";
3936 dispcc: clock-controller@af00000 {
3937 compatible = "qcom,sm8150-dispcc";
3946 clock-names = "bi_tcxo",
3953 power-domains = <&rpmhpd SM8150_MMCX>;
3954 #clock-cells = <1>;
3955 #reset-cells = <1>;
3956 #power-domain-cells = <1>;
3959 pdc: interrupt-controller@b220000 {
3960 compatible = "qcom,sm8150-pdc", "qcom,pdc";
3962 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3964 #interrupt-cells = <2>;
3965 interrupt-parent = <&intc>;
3966 interrupt-controller;
3969 aoss_qmp: power-management@c300000 {
3970 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp";
3975 #clock-cells = <0>;
3979 compatible = "qcom,rpmh-stats";
3983 tsens0: thermal-sensor@c263000 {
3984 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3990 interrupt-names = "uplow", "critical";
3991 #thermal-sensor-cells = <1>;
3994 tsens1: thermal-sensor@c265000 {
3995 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
4001 interrupt-names = "uplow", "critical";
4002 #thermal-sensor-cells = <1>;
4006 compatible = "qcom,spmi-pmic-arb";
4012 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4013 interrupt-names = "periph_irq";
4017 #address-cells = <2>;
4018 #size-cells = <0>;
4019 interrupt-controller;
4020 #interrupt-cells = <4>;
4024 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500";
4026 #iommu-cells = <2>;
4027 #global-interrupts = <1>;
4112 compatible = "qcom,sm8150-adsp-pas";
4115 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
4120 interrupt-names = "wdog", "fatal", "ready",
4121 "handover", "stop-ack";
4124 clock-names = "xo";
4126 power-domains = <&rpmhpd SM8150_CX>;
4128 memory-region = <&adsp_mem>;
4132 qcom,smem-states = <&adsp_smp2p_out 0>;
4133 qcom,smem-state-names = "stop";
4137 glink-edge {
4140 qcom,remote-pid = <2>;
4145 qcom,glink-channels = "fastrpcglink-apps-dsp";
4147 qcom,non-secure-domain;
4148 #address-cells = <1>;
4149 #size-cells = <0>;
4151 compute-cb@3 {
4152 compatible = "qcom,fastrpc-compute-cb";
4157 compute-cb@4 {
4158 compatible = "qcom,fastrpc-compute-cb";
4163 compute-cb@5 {
4164 compatible = "qcom,fastrpc-compute-cb";
4172 intc: interrupt-controller@17a00000 {
4173 compatible = "arm,gic-v3";
4174 interrupt-controller;
4175 #interrupt-cells = <3>;
4182 compatible = "qcom,sm8150-apss-shared",
4183 "qcom,sdm845-apss-shared";
4185 #mbox-cells = <1>;
4189 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
4196 #address-cells = <1>;
4197 #size-cells = <1>;
4199 compatible = "arm,armv7-timer-mem";
4201 clock-frequency = <19200000>;
4204 frame-number = <0>;
4212 frame-number = <1>;
4219 frame-number = <2>;
4226 frame-number = <3>;
4233 frame-number = <4>;
4240 frame-number = <5>;
4247 frame-number = <6>;
4256 compatible = "qcom,rpmh-rsc";
4260 reg-names = "drv-0", "drv-1", "drv-2";
4264 qcom,tcs-offset = <0xd00>;
4265 qcom,drv-id = <2>;
4266 qcom,tcs-config = <ACTIVE_TCS 2>,
4270 power-domains = <&CLUSTER_PD>;
4272 rpmhcc: clock-controller {
4273 compatible = "qcom,sm8150-rpmh-clk";
4274 #clock-cells = <1>;
4275 clock-names = "xo";
4279 rpmhpd: power-controller {
4280 compatible = "qcom,sm8150-rpmhpd";
4281 #power-domain-cells = <1>;
4282 operating-points-v2 = <&rpmhpd_opp_table>;
4284 rpmhpd_opp_table: opp-table {
4285 compatible = "operating-points-v2";
4288 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4292 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4300 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4304 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4308 opp-level = <224>;
4312 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4316 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4320 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4324 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4328 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4333 apps_bcm_voter: bcm-voter {
4334 compatible = "qcom,bcm-voter";
4339 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3";
4343 clock-names = "xo", "alternate";
4345 #interconnect-cells = <1>;
4349 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
4352 reg-names = "freq-domain0", "freq-domain1",
4353 "freq-domain2";
4356 clock-names = "xo", "alternate";
4358 #freq-domain-cells = <1>;
4359 #clock-cells = <1>;
4363 compatible = "qcom,sm8150-lmh";
4367 qcom,lmh-temp-arm-millicelsius = <60000>;
4368 qcom,lmh-temp-low-millicelsius = <84500>;
4369 qcom,lmh-temp-high-millicelsius = <85000>;
4370 interrupt-controller;
4371 #interrupt-cells = <1>;
4375 compatible = "qcom,sm8150-lmh";
4379 qcom,lmh-temp-arm-millicelsius = <60000>;
4380 qcom,lmh-temp-low-millicelsius = <84500>;
4381 qcom,lmh-temp-high-millicelsius = <85000>;
4382 interrupt-controller;
4383 #interrupt-cells = <1>;
4387 compatible = "qcom,wcn3990-wifi";
4389 reg-names = "membase";
4390 memory-region = <&wlan_mem>;
4391 clock-names = "cxo_ref_clk_pin", "qdss";
4411 compatible = "arm,armv8-timer";
4418 thermal-zones {
4419 cpu0-thermal {
4420 polling-delay-passive = <250>;
4421 polling-delay = <1000>;
4423 thermal-sensors = <&tsens0 1>;
4426 cpu0_alert0: trip-point0 {
4432 cpu0_alert1: trip-point1 {
4438 cpu0_crit: cpu-crit {
4445 cooling-maps {
4448 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4455 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4463 cpu1-thermal {
4464 polling-delay-passive = <250>;
4465 polling-delay = <1000>;
4467 thermal-sensors = <&tsens0 2>;
4470 cpu1_alert0: trip-point0 {
4476 cpu1_alert1: trip-point1 {
4482 cpu1_crit: cpu-crit {
4489 cooling-maps {
4492 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4499 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4507 cpu2-thermal {
4508 polling-delay-passive = <250>;
4509 polling-delay = <1000>;
4511 thermal-sensors = <&tsens0 3>;
4514 cpu2_alert0: trip-point0 {
4520 cpu2_alert1: trip-point1 {
4526 cpu2_crit: cpu-crit {
4533 cooling-maps {
4536 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4543 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4551 cpu3-thermal {
4552 polling-delay-passive = <250>;
4553 polling-delay = <1000>;
4555 thermal-sensors = <&tsens0 4>;
4558 cpu3_alert0: trip-point0 {
4564 cpu3_alert1: trip-point1 {
4570 cpu3_crit: cpu-crit {
4577 cooling-maps {
4580 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4587 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4595 cpu4-top-thermal {
4596 polling-delay-passive = <250>;
4597 polling-delay = <1000>;
4599 thermal-sensors = <&tsens0 7>;
4602 cpu4_top_alert0: trip-point0 {
4608 cpu4_top_alert1: trip-point1 {
4614 cpu4_top_crit: cpu-crit {
4621 cooling-maps {
4624 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4631 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4639 cpu5-top-thermal {
4640 polling-delay-passive = <250>;
4641 polling-delay = <1000>;
4643 thermal-sensors = <&tsens0 8>;
4646 cpu5_top_alert0: trip-point0 {
4652 cpu5_top_alert1: trip-point1 {
4658 cpu5_top_crit: cpu-crit {
4665 cooling-maps {
4668 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4675 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4683 cpu6-top-thermal {
4684 polling-delay-passive = <250>;
4685 polling-delay = <1000>;
4687 thermal-sensors = <&tsens0 9>;
4690 cpu6_top_alert0: trip-point0 {
4696 cpu6_top_alert1: trip-point1 {
4702 cpu6_top_crit: cpu-crit {
4709 cooling-maps {
4712 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4719 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4727 cpu7-top-thermal {
4728 polling-delay-passive = <250>;
4729 polling-delay = <1000>;
4731 thermal-sensors = <&tsens0 10>;
4734 cpu7_top_alert0: trip-point0 {
4740 cpu7_top_alert1: trip-point1 {
4746 cpu7_top_crit: cpu-crit {
4753 cooling-maps {
4756 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4771 cpu4-bottom-thermal {
4772 polling-delay-passive = <250>;
4773 polling-delay = <1000>;
4775 thermal-sensors = <&tsens0 11>;
4778 cpu4_bottom_alert0: trip-point0 {
4784 cpu4_bottom_alert1: trip-point1 {
4790 cpu4_bottom_crit: cpu-crit {
4797 cooling-maps {
4800 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4815 cpu5-bottom-thermal {
4816 polling-delay-passive = <250>;
4817 polling-delay = <1000>;
4819 thermal-sensors = <&tsens0 12>;
4822 cpu5_bottom_alert0: trip-point0 {
4828 cpu5_bottom_alert1: trip-point1 {
4834 cpu5_bottom_crit: cpu-crit {
4841 cooling-maps {
4844 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4859 cpu6-bottom-thermal {
4860 polling-delay-passive = <250>;
4861 polling-delay = <1000>;
4863 thermal-sensors = <&tsens0 13>;
4866 cpu6_bottom_alert0: trip-point0 {
4872 cpu6_bottom_alert1: trip-point1 {
4878 cpu6_bottom_crit: cpu-crit {
4885 cooling-maps {
4888 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4903 cpu7-bottom-thermal {
4904 polling-delay-passive = <250>;
4905 polling-delay = <1000>;
4907 thermal-sensors = <&tsens0 14>;
4910 cpu7_bottom_alert0: trip-point0 {
4916 cpu7_bottom_alert1: trip-point1 {
4922 cpu7_bottom_crit: cpu-crit {
4929 cooling-maps {
4932 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4939 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4947 aoss0-thermal {
4948 polling-delay-passive = <250>;
4949 polling-delay = <1000>;
4951 thermal-sensors = <&tsens0 0>;
4954 aoss0_alert0: trip-point0 {
4962 cluster0-thermal {
4963 polling-delay-passive = <250>;
4964 polling-delay = <1000>;
4966 thermal-sensors = <&tsens0 5>;
4969 cluster0_alert0: trip-point0 {
4982 cluster1-thermal {
4983 polling-delay-passive = <250>;
4984 polling-delay = <1000>;
4986 thermal-sensors = <&tsens0 6>;
4989 cluster1_alert0: trip-point0 {
5002 gpu-top-thermal {
5003 polling-delay-passive = <250>;
5004 polling-delay = <1000>;
5006 thermal-sensors = <&tsens0 15>;
5009 gpu1_alert0: trip-point0 {
5017 aoss1-thermal {
5018 polling-delay-passive = <250>;
5019 polling-delay = <1000>;
5021 thermal-sensors = <&tsens1 0>;
5024 aoss1_alert0: trip-point0 {
5032 wlan-thermal {
5033 polling-delay-passive = <250>;
5034 polling-delay = <1000>;
5036 thermal-sensors = <&tsens1 1>;
5039 wlan_alert0: trip-point0 {
5047 video-thermal {
5048 polling-delay-passive = <250>;
5049 polling-delay = <1000>;
5051 thermal-sensors = <&tsens1 2>;
5054 video_alert0: trip-point0 {
5062 mem-thermal {
5063 polling-delay-passive = <250>;
5064 polling-delay = <1000>;
5066 thermal-sensors = <&tsens1 3>;
5069 mem_alert0: trip-point0 {
5077 q6-hvx-thermal {
5078 polling-delay-passive = <250>;
5079 polling-delay = <1000>;
5081 thermal-sensors = <&tsens1 4>;
5084 q6_hvx_alert0: trip-point0 {
5092 camera-thermal {
5093 polling-delay-passive = <250>;
5094 polling-delay = <1000>;
5096 thermal-sensors = <&tsens1 5>;
5099 camera_alert0: trip-point0 {
5107 compute-thermal {
5108 polling-delay-passive = <250>;
5109 polling-delay = <1000>;
5111 thermal-sensors = <&tsens1 6>;
5114 compute_alert0: trip-point0 {
5122 modem-thermal {
5123 polling-delay-passive = <250>;
5124 polling-delay = <1000>;
5126 thermal-sensors = <&tsens1 7>;
5129 modem_alert0: trip-point0 {
5137 npu-thermal {
5138 polling-delay-passive = <250>;
5139 polling-delay = <1000>;
5141 thermal-sensors = <&tsens1 8>;
5144 npu_alert0: trip-point0 {
5152 modem-vec-thermal {
5153 polling-delay-passive = <250>;
5154 polling-delay = <1000>;
5156 thermal-sensors = <&tsens1 9>;
5159 modem_vec_alert0: trip-point0 {
5167 modem-scl-thermal {
5168 polling-delay-passive = <250>;
5169 polling-delay = <1000>;
5171 thermal-sensors = <&tsens1 10>;
5174 modem_scl_alert0: trip-point0 {
5182 gpu-bottom-thermal {
5183 polling-delay-passive = <250>;
5184 polling-delay = <1000>;
5186 thermal-sensors = <&tsens1 11>;
5189 gpu2_alert0: trip-point0 {