Lines Matching +full:thermal +full:- +full:sensors
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
8 #include <dt-bindings/clock/qcom,sm6375-gpucc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/firmware/qcom,scm.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mailbox/qcom-ipcc.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board_clk: xo-board-clk {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 clock-frequency = <32000>;
33 #clock-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <0>;
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
49 operating-points-v2 = <&cpu0_opp_table>;
51 power-domains = <&CPU_PD0>;
52 power-domain-names = "psci";
53 #cooling-cells = <2>;
54 L2_0: l2-cache {
56 cache-level = <2>;
57 cache-unified;
58 next-level-cache = <&L3_0>;
59 L3_0: l3-cache {
61 cache-level = <3>;
62 cache-unified;
72 enable-method = "psci";
73 next-level-cache = <&L2_100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
75 operating-points-v2 = <&cpu0_opp_table>;
77 power-domains = <&CPU_PD1>;
78 power-domain-names = "psci";
79 #cooling-cells = <2>;
80 L2_100: l2-cache {
82 cache-level = <2>;
83 cache-unified;
84 next-level-cache = <&L3_0>;
93 enable-method = "psci";
94 next-level-cache = <&L2_200>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
96 operating-points-v2 = <&cpu0_opp_table>;
98 power-domains = <&CPU_PD2>;
99 power-domain-names = "psci";
100 #cooling-cells = <2>;
101 L2_200: l2-cache {
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&L3_0>;
114 enable-method = "psci";
115 next-level-cache = <&L2_300>;
116 qcom,freq-domain = <&cpufreq_hw 0>;
117 operating-points-v2 = <&cpu0_opp_table>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 #cooling-cells = <2>;
122 L2_300: l2-cache {
124 cache-level = <2>;
125 cache-unified;
126 next-level-cache = <&L3_0>;
135 enable-method = "psci";
136 next-level-cache = <&L2_400>;
137 qcom,freq-domain = <&cpufreq_hw 0>;
138 operating-points-v2 = <&cpu0_opp_table>;
140 power-domains = <&CPU_PD4>;
141 power-domain-names = "psci";
142 #cooling-cells = <2>;
143 L2_400: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
156 enable-method = "psci";
157 next-level-cache = <&L2_500>;
158 qcom,freq-domain = <&cpufreq_hw 0>;
159 operating-points-v2 = <&cpu0_opp_table>;
161 power-domains = <&CPU_PD5>;
162 power-domain-names = "psci";
163 #cooling-cells = <2>;
164 L2_500: l2-cache {
166 cache-level = <2>;
167 cache-unified;
168 next-level-cache = <&L3_0>;
177 enable-method = "psci";
178 next-level-cache = <&L2_600>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu6_opp_table>;
182 power-domains = <&CPU_PD6>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
185 L2_600: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 next-level-cache = <&L2_700>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu6_opp_table>;
203 power-domains = <&CPU_PD7>;
204 power-domain-names = "psci";
205 #cooling-cells = <2>;
206 L2_700: l2-cache {
208 cache-level = <2>;
209 cache-unified;
210 next-level-cache = <&L3_0>;
214 cpu-map {
250 idle-states {
251 entry-method = "psci";
253 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
254 compatible = "arm,idle-state";
255 idle-state-name = "silver-power-collapse";
256 arm,psci-suspend-param = <0x40000003>;
257 entry-latency-us = <549>;
258 exit-latency-us = <901>;
259 min-residency-us = <1774>;
260 local-timer-stop;
263 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
264 compatible = "arm,idle-state";
265 idle-state-name = "silver-rail-power-collapse";
266 arm,psci-suspend-param = <0x40000004>;
267 entry-latency-us = <702>;
268 exit-latency-us = <915>;
269 min-residency-us = <4001>;
270 local-timer-stop;
273 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
274 compatible = "arm,idle-state";
275 idle-state-name = "gold-power-collapse";
276 arm,psci-suspend-param = <0x40000003>;
277 entry-latency-us = <523>;
278 exit-latency-us = <1244>;
279 min-residency-us = <2207>;
280 local-timer-stop;
283 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
284 compatible = "arm,idle-state";
285 idle-state-name = "gold-rail-power-collapse";
286 arm,psci-suspend-param = <0x40000004>;
287 entry-latency-us = <526>;
288 exit-latency-us = <1854>;
289 min-residency-us = <5555>;
290 local-timer-stop;
294 domain-idle-states {
295 CLUSTER_SLEEP_0: cluster-sleep-0 {
296 compatible = "domain-idle-state";
297 arm,psci-suspend-param = <0x41000044>;
298 entry-latency-us = <2752>;
299 exit-latency-us = <3048>;
300 min-residency-us = <6118>;
307 compatible = "qcom,scm-sm6375", "qcom,scm";
309 clock-names = "core";
310 #reset-cells = <1>;
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
322 opp-shared;
324 opp-300000000 {
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <(300000 * 32)>;
329 opp-576000000 {
330 opp-hz = /bits/ 64 <576000000>;
331 opp-peak-kBps = <(556800 * 32)>;
334 opp-691200000 {
335 opp-hz = /bits/ 64 <691200000>;
336 opp-peak-kBps = <(652800 * 32)>;
339 opp-940800000 {
340 opp-hz = /bits/ 64 <940800000>;
341 opp-peak-kBps = <(921600 * 32)>;
344 opp-1113600000 {
345 opp-hz = /bits/ 64 <1113600000>;
346 opp-peak-kBps = <(921600 * 32)>;
349 opp-1324800000 {
350 opp-hz = /bits/ 64 <1324800000>;
351 opp-peak-kBps = <(1171200 * 32)>;
354 opp-1516800000 {
355 opp-hz = /bits/ 64 <1516800000>;
356 opp-peak-kBps = <(1497600 * 32)>;
359 opp-1651200000 {
360 opp-hz = /bits/ 64 <1651200000>;
361 opp-peak-kBps = <(1497600 * 32)>;
364 opp-1708800000 {
365 opp-hz = /bits/ 64 <1708800000>;
366 opp-peak-kBps = <(1497600 * 32)>;
369 opp-1804800000 {
370 opp-hz = /bits/ 64 <1804800000>;
371 opp-peak-kBps = <(1497600 * 32)>;
375 cpu6_opp_table: opp-table-cpu6 {
376 compatible = "operating-points-v2";
377 opp-shared;
379 opp-691200000 {
380 opp-hz = /bits/ 64 <691200000>;
381 opp-peak-kBps = <(556800 * 32)>;
384 opp-940800000 {
385 opp-hz = /bits/ 64 <940800000>;
386 opp-peak-kBps = <(921600 * 32)>;
389 opp-1228800000 {
390 opp-hz = /bits/ 64 <1228800000>;
391 opp-peak-kBps = <(1171200 * 32)>;
394 opp-1401600000 {
395 opp-hz = /bits/ 64 <1401600000>;
396 opp-peak-kBps = <(1382400 * 32)>;
399 opp-1516800000 {
400 opp-hz = /bits/ 64 <1516800000>;
401 opp-peak-kBps = <(1497600 * 32)>;
404 opp-1651200000 {
405 opp-hz = /bits/ 64 <1651200000>;
406 opp-peak-kBps = <(1497600 * 32)>;
409 opp-1804800000 {
410 opp-hz = /bits/ 64 <1804800000>;
411 opp-peak-kBps = <(1497600 * 32)>;
414 opp-1900800000 {
415 opp-hz = /bits/ 64 <1900800000>;
416 opp-peak-kBps = <(1497600 * 32)>;
419 opp-2054400000 {
420 opp-hz = /bits/ 64 <2054400000>;
421 opp-peak-kBps = <(1497600 * 32)>;
424 opp-2208000000 {
425 opp-hz = /bits/ 64 <2208000000>;
426 opp-peak-kBps = <(1497600 * 32)>;
431 compatible = "arm,armv8-pmuv3";
436 compatible = "arm,psci-1.0";
439 CPU_PD0: power-domain-cpu0 {
440 #power-domain-cells = <0>;
441 power-domains = <&CLUSTER_PD>;
442 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
445 CPU_PD1: power-domain-cpu1 {
446 #power-domain-cells = <0>;
447 power-domains = <&CLUSTER_PD>;
448 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
451 CPU_PD2: power-domain-cpu2 {
452 #power-domain-cells = <0>;
453 power-domains = <&CLUSTER_PD>;
454 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
457 CPU_PD3: power-domain-cpu3 {
458 #power-domain-cells = <0>;
459 power-domains = <&CLUSTER_PD>;
460 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
463 CPU_PD4: power-domain-cpu4 {
464 #power-domain-cells = <0>;
465 power-domains = <&CLUSTER_PD>;
466 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
469 CPU_PD5: power-domain-cpu5 {
470 #power-domain-cells = <0>;
471 power-domains = <&CLUSTER_PD>;
472 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
475 CPU_PD6: power-domain-cpu6 {
476 #power-domain-cells = <0>;
477 power-domains = <&CLUSTER_PD>;
478 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
481 CPU_PD7: power-domain-cpu7 {
482 #power-domain-cells = <0>;
483 power-domains = <&CLUSTER_PD>;
484 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
487 CLUSTER_PD: power-domain-cpu-cluster0 {
488 #power-domain-cells = <0>;
489 domain-idle-states = <&CLUSTER_SLEEP_0>;
493 qup_opp_table: opp-table-qup {
494 compatible = "operating-points-v2";
496 opp-75000000 {
497 opp-hz = /bits/ 64 <75000000>;
498 required-opps = <&rpmpd_opp_low_svs>;
501 opp-100000000 {
502 opp-hz = /bits/ 64 <100000000>;
503 required-opps = <&rpmpd_opp_svs>;
506 opp-128000000 {
507 opp-hz = /bits/ 64 <128000000>;
508 required-opps = <&rpmpd_opp_nom>;
512 reserved_memory: reserved-memory {
513 #address-cells = <2>;
514 #size-cells = <2>;
519 no-map;
522 xbl_aop_mem: xbl-aop@80700000 {
524 no-map;
527 reserved_xbl_uefi: xbl-uefi-res@80880000 {
529 no-map;
536 no-map;
541 no-map;
544 cdsp_secure_heap_mem: cdsp-sec-heap@80c00000 {
546 no-map;
549 dfps_data_mem: dpfs-data@85e00000 {
551 no-map;
554 pil_wlan_mem: pil-wlan@86500000 {
556 no-map;
559 pil_adsp_mem: pil-adsp@86700000 {
561 no-map;
564 pil_cdsp_mem: pil-cdsp@88700000 {
566 no-map;
569 pil_video_mem: pil-video@8a500000 {
571 no-map;
574 pil_ipa_fw_mem: pil-ipa-fw@8aa00000 {
576 no-map;
579 pil_ipa_gsi_mem: pil-ipa-gsi@8aa10000 {
581 no-map;
584 pil_gpu_micro_code_mem: pil-gpu-ucode@8aa1a000 {
586 no-map;
589 pil_mpss_wlan_mem: pil-mpss-wlan@8b800000 {
591 no-map;
596 no-map;
600 compatible = "qcom,rmtfs-mem";
602 no-map;
604 qcom,client-id = <1>;
610 no-map;
615 no-map;
620 no-map;
625 compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc";
627 glink-edge {
628 compatible = "qcom,glink-rpm";
629 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
632 qcom,rpm-msg-ram = <&rpm_msg_ram>;
635 rpm_requests: rpm-requests {
636 compatible = "qcom,rpm-sm6375";
637 qcom,glink-channels = "rpm_requests";
639 rpmcc: clock-controller {
640 compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc";
642 clock-names = "xo";
643 #clock-cells = <1>;
646 rpmpd: power-controller {
647 compatible = "qcom,sm6375-rpmpd";
648 #power-domain-cells = <1>;
649 operating-points-v2 = <&rpmpd_opp_table>;
651 rpmpd_opp_table: opp-table {
652 compatible = "operating-points-v2";
655 opp-level = <RPM_SMD_LEVEL_RETENTION>;
659 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
663 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
667 opp-level = <RPM_SMD_LEVEL_SVS>;
671 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
675 opp-level = <RPM_SMD_LEVEL_NOM>;
679 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
683 opp-level = <RPM_SMD_LEVEL_TURBO>;
687 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
695 smp2p-adsp {
698 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
704 qcom,local-pid = <0>;
705 qcom,remote-pid = <2>;
707 smp2p_adsp_out: master-kernel {
708 qcom,entry-name = "master-kernel";
709 #qcom,smem-state-cells = <1>;
712 smp2p_adsp_in: slave-kernel {
713 qcom,entry-name = "slave-kernel";
714 interrupt-controller;
715 #interrupt-cells = <2>;
719 smp2p-cdsp {
722 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
728 qcom,local-pid = <0>;
729 qcom,remote-pid = <5>;
731 smp2p_cdsp_out: master-kernel {
732 qcom,entry-name = "master-kernel";
733 #qcom,smem-state-cells = <1>;
736 smp2p_cdsp_in: slave-kernel {
737 qcom,entry-name = "slave-kernel";
738 interrupt-controller;
739 #interrupt-cells = <2>;
743 smp2p-modem {
746 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
752 qcom,local-pid = <0>;
753 qcom,remote-pid = <1>;
755 smp2p_modem_out: master-kernel {
756 qcom,entry-name = "master-kernel";
757 #qcom,smem-state-cells = <1>;
760 smp2p_modem_in: slave-kernel {
761 qcom,entry-name = "slave-kernel";
762 interrupt-controller;
763 #interrupt-cells = <2>;
766 ipa_smp2p_out: ipa-ap-to-modem {
767 qcom,entry-name = "ipa";
768 #qcom,smem-state-cells = <1>;
771 ipa_smp2p_in: ipa-modem-to-ap {
772 qcom,entry-name = "ipa";
773 interrupt-controller;
774 #interrupt-cells = <2>;
777 wlan_smp2p_in: wlan-wpss-to-ap {
778 qcom,entry-name = "wlan";
779 interrupt-controller;
780 #interrupt-cells = <2>;
785 #address-cells = <2>;
786 #size-cells = <2>;
788 dma-ranges = <0 0 0 0 0x10 0>;
789 compatible = "simple-bus";
792 compatible = "qcom,sm6375-ipcc", "qcom,ipcc";
795 interrupt-controller;
796 #interrupt-cells = <3>;
797 #mbox-cells = <2>;
801 compatible = "qcom,tcsr-mutex";
803 #hwlock-cells = <1>;
807 compatible = "qcom,sm6375-tlmm";
810 gpio-ranges = <&tlmm 0 0 157>;
811 /* TODO: Hook up MPM as wakeup-parent when it's there */
812 interrupt-controller;
813 gpio-controller;
814 #interrupt-cells = <2>;
815 #gpio-cells = <2>;
817 sdc2_off_state: sdc2-off-state {
818 clk-pins {
820 drive-strength = <2>;
821 bias-disable;
824 cmd-pins {
826 drive-strength = <2>;
827 bias-pull-up;
830 data-pins {
832 drive-strength = <2>;
833 bias-pull-up;
837 sdc2_on_state: sdc2-on-state {
838 clk-pins {
840 drive-strength = <16>;
841 bias-disable;
844 cmd-pins {
846 drive-strength = <10>;
847 bias-pull-up;
850 data-pins {
852 drive-strength = <10>;
853 bias-pull-up;
857 qup_i2c0_default: qup-i2c0-default-state {
860 drive-strength = <2>;
861 bias-pull-up;
864 qup_i2c1_default: qup-i2c1-default-state {
867 drive-strength = <2>;
868 bias-pull-up;
871 qup_i2c2_default: qup-i2c2-default-state {
874 drive-strength = <2>;
875 bias-pull-up;
878 qup_i2c8_default: qup-i2c8-default-state {
882 drive-strength = <2>;
883 bias-pull-up;
886 qup_i2c10_default: qup-i2c10-default-state {
889 drive-strength = <2>;
890 bias-pull-up;
893 qup_spi0_default: qup-spi0-default-state {
896 drive-strength = <6>;
897 bias-disable;
901 gcc: clock-controller@1400000 {
902 compatible = "qcom,sm6375-gcc";
907 #power-domain-cells = <1>;
908 #clock-cells = <1>;
909 #reset-cells = <1>;
913 compatible = "qcom,sm6375-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy";
917 clock-names = "ref";
919 #phy-cells = <0>;
925 compatible = "qcom,spmi-pmic-arb";
931 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
932 interrupt-names = "periph_irq";
936 #address-cells = <2>;
937 #size-cells = <0>;
938 interrupt-controller;
939 #interrupt-cells = <4>;
942 tsens0: thermal-sensor@4411000 {
943 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
948 interrupt-names = "uplow", "critical";
949 #thermal-sensor-cells = <1>;
950 #qcom,sensors = <15>;
953 tsens1: thermal-sensor@4413000 {
954 compatible = "qcom,sm6375-tsens", "qcom,tsens-v2";
959 interrupt-names = "uplow", "critical";
960 #thermal-sensor-cells = <1>;
961 #qcom,sensors = <11>;
965 compatible = "qcom,rpm-msg-ram";
970 compatible = "qcom,rpm-stats";
975 compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5";
980 interrupt-names = "hc_irq", "pwr_irq";
985 clock-names = "iface", "core", "xo";
989 pinctrl-0 = <&sdc2_on_state>;
990 pinctrl-1 = <&sdc2_off_state>;
991 pinctrl-names = "default", "sleep";
993 qcom,dll-config = <0x0007642c>;
994 qcom,ddr-config = <0x80040868>;
995 power-domains = <&rpmpd SM6375_VDDCX>;
996 operating-points-v2 = <&sdhc2_opp_table>;
997 bus-width = <4>;
1001 sdhc2_opp_table: opp-table {
1002 compatible = "operating-points-v2";
1004 opp-100000000 {
1005 opp-hz = /bits/ 64 <100000000>;
1006 required-opps = <&rpmpd_opp_low_svs>;
1009 opp-202000000 {
1010 opp-hz = /bits/ 64 <202000000>;
1011 required-opps = <&rpmpd_opp_svs_plus>;
1016 gpi_dma0: dma-controller@4a00000 {
1017 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1029 dma-channels = <10>;
1030 dma-channel-mask = <0x1f>;
1032 #dma-cells = <3>;
1037 compatible = "qcom,geni-se-qup";
1039 clock-names = "m-ahb", "s-ahb";
1043 #address-cells = <2>;
1044 #size-cells = <2>;
1049 compatible = "qcom,geni-i2c";
1051 clock-names = "se";
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&qup_i2c0_default>;
1058 dma-names = "tx", "rx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1065 compatible = "qcom,geni-spi";
1067 clock-names = "se";
1070 pinctrl-names = "default";
1071 pinctrl-0 = <&qup_spi0_default>;
1072 power-domains = <&rpmpd SM6375_VDDCX>;
1073 operating-points-v2 = <&qup_opp_table>;
1076 dma-names = "tx", "rx";
1077 #address-cells = <1>;
1078 #size-cells = <0>;
1083 compatible = "qcom,geni-i2c";
1085 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c1_default>;
1092 dma-names = "tx", "rx";
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1099 compatible = "qcom,geni-spi";
1101 clock-names = "se";
1104 power-domains = <&rpmpd SM6375_VDDCX>;
1105 operating-points-v2 = <&qup_opp_table>;
1108 dma-names = "tx", "rx";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1115 compatible = "qcom,geni-i2c";
1117 clock-names = "se";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&qup_i2c2_default>;
1124 dma-names = "tx", "rx";
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1131 compatible = "qcom,geni-spi";
1133 clock-names = "se";
1136 power-domains = <&rpmpd SM6375_VDDCX>;
1137 operating-points-v2 = <&qup_opp_table>;
1140 dma-names = "tx", "rx";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1155 gpi_dma1: dma-controller@4c00000 {
1156 compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma";
1168 dma-channels = <10>;
1169 dma-channel-mask = <0x1f>;
1171 #dma-cells = <3>;
1176 compatible = "qcom,geni-se-qup";
1178 clock-names = "m-ahb", "s-ahb";
1182 #address-cells = <2>;
1183 #size-cells = <2>;
1188 compatible = "qcom,geni-i2c";
1190 clock-names = "se";
1195 dma-names = "tx", "rx";
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1202 compatible = "qcom,geni-spi";
1204 clock-names = "se";
1207 power-domains = <&rpmpd SM6375_VDDCX>;
1208 operating-points-v2 = <&qup_opp_table>;
1211 dma-names = "tx", "rx";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1218 compatible = "qcom,geni-i2c";
1220 clock-names = "se";
1225 dma-names = "tx", "rx";
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1232 compatible = "qcom,geni-spi";
1234 clock-names = "se";
1237 power-domains = <&rpmpd SM6375_VDDCX>;
1238 operating-points-v2 = <&qup_opp_table>;
1241 dma-names = "tx", "rx";
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1248 compatible = "qcom,geni-i2c";
1250 clock-names = "se";
1253 pinctrl-names = "default";
1254 pinctrl-0 = <&qup_i2c8_default>;
1257 dma-names = "tx", "rx";
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 compatible = "qcom,geni-spi";
1266 clock-names = "se";
1269 power-domains = <&rpmpd SM6375_VDDCX>;
1270 operating-points-v2 = <&qup_opp_table>;
1273 dma-names = "tx", "rx";
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1280 compatible = "qcom,geni-i2c";
1282 clock-names = "se";
1287 dma-names = "tx", "rx";
1288 #address-cells = <1>;
1289 #size-cells = <0>;
1294 compatible = "qcom,geni-spi";
1296 clock-names = "se";
1299 power-domains = <&rpmpd SM6375_VDDCX>;
1300 operating-points-v2 = <&qup_opp_table>;
1303 dma-names = "tx", "rx";
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1310 compatible = "qcom,geni-i2c";
1312 clock-names = "se";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&qup_i2c10_default>;
1319 dma-names = "tx", "rx";
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1326 compatible = "qcom,geni-spi";
1328 clock-names = "se";
1331 power-domains = <&rpmpd SM6375_VDDCX>;
1332 operating-points-v2 = <&qup_opp_table>;
1335 dma-names = "tx", "rx";
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1343 compatible = "qcom,sm6375-dwc3", "qcom,dwc3";
1352 clock-names = "cfg_noc",
1359 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1361 assigned-clock-rates = <19200000>, <133333333>;
1367 interrupt-names = "hs_phy_irq",
1372 power-domains = <&gcc USB30_PRIM_GDSC>;
1378 * USB3 is not implemented yet - (re)move it when
1381 qcom,select-utmi-as-pipe-clk;
1383 #address-cells = <2>;
1384 #size-cells = <2>;
1393 maximum-speed = "high-speed";
1395 phy-names = "usb2-phy";
1399 snps,hird-threshold = /bits/ 8 <0x10>;
1400 snps,usb2-gadget-lpm-disable;
1402 snps,is-utmi-l1-suspend;
1403 snps,dis-u1-entry-quirk;
1404 snps,dis-u2-entry-quirk;
1406 snps,has-lpm-erratum;
1407 tx-fifo-resize;
1412 compatible = "qcom,sm6375-smmu-v2", "qcom,smmu-v2";
1414 #iommu-cells = <1>;
1415 #global-interrupts = <2>;
1428 clock-names = "bus";
1430 power-domains = <&gpucc GPU_CX_GDSC>;
1433 gpucc: clock-controller@5990000 {
1434 compatible = "qcom,sm6375-gpucc";
1440 power-domains = <&rpmpd SM6375_VDDGX>;
1441 required-opps = <&rpmpd_opp_low_svs>;
1442 #clock-cells = <1>;
1443 #reset-cells = <1>;
1444 #power-domain-cells = <1>;
1448 compatible = "qcom,sm6375-mpss-pas";
1451 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1457 interrupt-names = "wdog",
1461 "stop-ack",
1462 "shutdown-ack";
1465 clock-names = "xo";
1467 power-domains = <&rpmpd SM6375_VDDCX>;
1468 power-domain-names = "cx";
1470 memory-region = <&pil_mpss_wlan_mem>;
1472 qcom,smem-states = <&smp2p_modem_out 0>;
1473 qcom,smem-state-names = "stop";
1477 glink-edge {
1478 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1484 qcom,remote-pid = <1>;
1489 compatible = "qcom,sm6375-adsp-pas";
1492 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1497 interrupt-names = "wdog", "fatal", "ready",
1498 "handover", "stop-ack";
1501 clock-names = "xo";
1503 power-domains = <&rpmpd SM6375_VDD_LPI_CX>,
1505 power-domain-names = "lcx", "lmx";
1507 memory-region = <&pil_adsp_mem>;
1509 qcom,smem-states = <&smp2p_adsp_out 0>;
1510 qcom,smem-state-names = "stop";
1514 glink-edge {
1515 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1522 qcom,remote-pid = <2>;
1527 compatible = "qcom,sm6375-cdsp-pas";
1530 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
1535 interrupt-names = "wdog", "fatal", "ready",
1536 "handover", "stop-ack";
1539 clock-names = "xo";
1541 power-domains = <&rpmpd SM6375_VDDCX>;
1542 power-domain-names = "cx";
1544 memory-region = <&pil_cdsp_mem>;
1546 qcom,smem-states = <&smp2p_cdsp_out 0>;
1547 qcom,smem-state-names = "stop";
1551 glink-edge {
1552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1558 qcom,remote-pid = <5>;
1563 compatible = "qcom,sm6375-imem", "syscon", "simple-mfd";
1567 #address-cells = <1>;
1568 #size-cells = <1>;
1570 pil-reloc@94c {
1571 compatible = "qcom,pil-reloc-info";
1577 compatible = "qcom,sm6375-smmu-500", "arm,mmu-500";
1645 power-domains = <&gcc HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC>,
1648 #global-interrupts = <1>;
1649 #iommu-cells = <2>;
1653 compatible = "qcom,wcn3990-wifi";
1655 reg-names = "membase";
1656 memory-region = <&pil_wlan_mem>;
1670 qcom,msa-fixed-perm;
1674 intc: interrupt-controller@f200000 {
1675 compatible = "arm,gic-v3";
1679 #redistributor-regions = <1>;
1680 #interrupt-cells = <3>;
1681 redistributor-stride = <0 0x20000>;
1682 interrupt-controller;
1686 compatible = "arm,armv7-timer-mem";
1689 #address-cells = <1>;
1690 #size-cells = <1>;
1696 frame-number = <0>;
1702 frame-number = <1>;
1709 frame-number = <2>;
1716 frame-number = <3>;
1723 frame-number = <4>;
1730 frame-number = <5>;
1737 frame-number = <6>;
1743 compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3";
1747 clock-names = "xo", "alternate";
1748 #interconnect-cells = <1>;
1752 compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss";
1754 reg-names = "freq-domain0", "freq-domain1";
1757 clock-names = "xo", "alternate";
1760 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
1761 #freq-domain-cells = <1>;
1762 #clock-cells = <1>;
1766 thermal-zones {
1767 mapss0-thermal {
1768 polling-delay-passive = <0>;
1769 polling-delay = <0>;
1771 thermal-sensors = <&tsens0 0>;
1774 mapss0_alert0: trip-point0 {
1780 mapss0_alert1: trip-point1 {
1786 mapss0_crit: mapss-crit {
1794 cpu0-thermal {
1795 polling-delay-passive = <0>;
1796 polling-delay = <0>;
1798 thermal-sensors = <&tsens0 1>;
1801 cpu0_alert0: trip-point0 {
1807 cpu0_alert1: trip-point1 {
1813 cpu0_crit: cpu-crit {
1821 cpu1-thermal {
1822 polling-delay-passive = <0>;
1823 polling-delay = <0>;
1825 thermal-sensors = <&tsens0 2>;
1828 cpu1_alert0: trip-point0 {
1834 cpu1_alert1: trip-point1 {
1840 cpu1_crit: cpu-crit {
1848 cpu2-thermal {
1849 polling-delay-passive = <0>;
1850 polling-delay = <0>;
1852 thermal-sensors = <&tsens0 3>;
1855 cpu2_alert0: trip-point0 {
1861 cpu2_alert1: trip-point1 {
1867 cpu2_crit: cpu-crit {
1875 cpu3-thermal {
1876 polling-delay-passive = <0>;
1877 polling-delay = <0>;
1879 thermal-sensors = <&tsens0 4>;
1882 cpu3_alert0: trip-point0 {
1888 cpu3_alert1: trip-point1 {
1894 cpu3_crit: cpu-crit {
1902 cpu4-thermal {
1903 polling-delay-passive = <0>;
1904 polling-delay = <0>;
1906 thermal-sensors = <&tsens0 5>;
1909 cpu4_alert0: trip-point0 {
1915 cpu4_alert1: trip-point1 {
1921 cpu4_crit: cpu-crit {
1929 cpu5-thermal {
1930 polling-delay-passive = <0>;
1931 polling-delay = <0>;
1933 thermal-sensors = <&tsens0 6>;
1936 cpu5_alert0: trip-point0 {
1942 cpu5_alert1: trip-point1 {
1948 cpu5_crit: cpu-crit {
1956 cluster0-thermal {
1957 polling-delay-passive = <0>;
1958 polling-delay = <0>;
1960 thermal-sensors = <&tsens0 7>;
1963 cluster0_alert0: trip-point0 {
1969 cluster0_alert1: trip-point1 {
1975 cluster0_crit: cpu-crit {
1983 cluster1-thermal {
1984 polling-delay-passive = <0>;
1985 polling-delay = <0>;
1987 thermal-sensors = <&tsens0 8>;
1990 cluster1_alert0: trip-point0 {
1996 cluster1_alert1: trip-point1 {
2002 cluster1_crit: cpu-crit {
2010 cpu6-thermal {
2011 polling-delay-passive = <0>;
2012 polling-delay = <0>;
2014 thermal-sensors = <&tsens0 9>;
2017 cpu6_alert0: trip-point0 {
2023 cpu6_alert1: trip-point1 {
2029 cpu6_crit: cpu-crit {
2037 cpu7-thermal {
2038 polling-delay-passive = <0>;
2039 polling-delay = <0>;
2041 thermal-sensors = <&tsens0 10>;
2044 cpu7_alert0: trip-point0 {
2050 cpu7_alert1: trip-point1 {
2056 cpu7_crit: cpu-crit {
2064 cpu-unk0-thermal {
2065 polling-delay-passive = <0>;
2066 polling-delay = <0>;
2068 thermal-sensors = <&tsens0 11>;
2071 cpu_unk0_alert0: trip-point0 {
2077 cpu_unk0_alert1: trip-point1 {
2083 cpu_unk0_crit: cpu-crit {
2091 cpu-unk1-thermal {
2092 polling-delay-passive = <0>;
2093 polling-delay = <0>;
2095 thermal-sensors = <&tsens0 12>;
2098 cpu_unk1_alert0: trip-point0 {
2104 cpu_unk1_alert1: trip-point1 {
2110 cpu_unk1_crit: cpu-crit {
2118 gpuss0-thermal {
2119 polling-delay-passive = <0>;
2120 polling-delay = <0>;
2122 thermal-sensors = <&tsens0 13>;
2125 gpuss0_alert0: trip-point0 {
2131 gpuss0_alert1: trip-point1 {
2137 gpuss0_crit: gpu-crit {
2145 gpuss1-thermal {
2146 polling-delay-passive = <0>;
2147 polling-delay = <0>;
2149 thermal-sensors = <&tsens0 14>;
2152 gpuss1_alert0: trip-point0 {
2158 gpuss1_alert1: trip-point1 {
2164 gpuss1_crit: gpu-crit {
2172 mapss1-thermal {
2173 polling-delay-passive = <0>;
2174 polling-delay = <0>;
2176 thermal-sensors = <&tsens1 0>;
2179 mapss1_alert0: trip-point0 {
2185 mapss1_alert1: trip-point1 {
2191 mapss1_crit: mapss-crit {
2199 cwlan-thermal {
2200 polling-delay-passive = <0>;
2201 polling-delay = <0>;
2203 thermal-sensors = <&tsens1 1>;
2206 cwlan_alert0: trip-point0 {
2212 cwlan_alert1: trip-point1 {
2218 cwlan_crit: cwlan-crit {
2226 audio-thermal {
2227 polling-delay-passive = <0>;
2228 polling-delay = <0>;
2230 thermal-sensors = <&tsens1 2>;
2233 audio_alert0: trip-point0 {
2239 audio_alert1: trip-point1 {
2245 audio_crit: audio-crit {
2253 ddr-thermal {
2254 polling-delay-passive = <0>;
2255 polling-delay = <0>;
2257 thermal-sensors = <&tsens1 3>;
2260 ddr_alert0: trip-point0 {
2266 ddr_alert1: trip-point1 {
2272 ddr_crit: ddr-crit {
2280 q6hvx-thermal {
2281 polling-delay-passive = <0>;
2282 polling-delay = <0>;
2284 thermal-sensors = <&tsens1 4>;
2287 q6hvx_alert0: trip-point0 {
2293 q6hvx_alert1: trip-point1 {
2299 q6hvx_crit: q6hvx-crit {
2307 camera-thermal {
2308 polling-delay-passive = <0>;
2309 polling-delay = <0>;
2311 thermal-sensors = <&tsens1 5>;
2314 camera_alert0: trip-point0 {
2320 camera_alert1: trip-point1 {
2326 camera_crit: camera-crit {
2334 mdm-core0-thermal {
2335 polling-delay-passive = <0>;
2336 polling-delay = <0>;
2338 thermal-sensors = <&tsens1 6>;
2341 mdm_core0_alert0: trip-point0 {
2347 mdm_core0_alert1: trip-point1 {
2353 mdm_core0_crit: mdm-core0-crit {
2361 mdm-core1-thermal {
2362 polling-delay-passive = <0>;
2363 polling-delay = <0>;
2365 thermal-sensors = <&tsens1 7>;
2368 mdm_core1_alert0: trip-point0 {
2374 mdm_core1_alert1: trip-point1 {
2380 mdm_core1_crit: mdm-core1-crit {
2388 mdm-vec-thermal {
2389 polling-delay-passive = <0>;
2390 polling-delay = <0>;
2392 thermal-sensors = <&tsens1 8>;
2395 mdm_vec_alert0: trip-point0 {
2401 mdm_vec_alert1: trip-point1 {
2407 mdm_vec_crit: mdm-vec-crit {
2415 msm-scl-thermal {
2416 polling-delay-passive = <0>;
2417 polling-delay = <0>;
2419 thermal-sensors = <&tsens1 9>;
2422 msm_scl_alert0: trip-point0 {
2428 msm_scl_alert1: trip-point1 {
2434 msm_scl_crit: msm-scl-crit {
2442 video-thermal {
2443 polling-delay-passive = <0>;
2444 polling-delay = <0>;
2446 thermal-sensors = <&tsens1 10>;
2449 video_alert0: trip-point0 {
2455 video_alert1: trip-point1 {
2461 video_crit: video-crit {
2471 compatible = "arm,armv8-timer";