Lines Matching +full:min +full:- +full:residency +full:- +full:us
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm6350.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sm6350-camcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm6350.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/mailbox/qcom-ipcc.h>
19 #include <dt-bindings/phy/phy-qcom-qmp.h>
20 #include <dt-bindings/power/qcom-rpmpd.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
24 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <76800000>;
33 clock-output-names = "xo_board";
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 clock-frequency = <32764>;
39 #clock-cells = <0>;
44 #address-cells = <2>;
45 #size-cells = <0>;
52 enable-method = "psci";
53 capacity-dmips-mhz = <1024>;
54 dynamic-power-coefficient = <100>;
55 next-level-cache = <&L2_0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 operating-points-v2 = <&cpu0_opp_table>;
61 power-domains = <&CPU_PD0>;
62 power-domain-names = "psci";
63 #cooling-cells = <2>;
64 L2_0: l2-cache {
66 cache-level = <2>;
67 cache-unified;
68 next-level-cache = <&L3_0>;
69 L3_0: l3-cache {
71 cache-level = <3>;
72 cache-unified;
82 enable-method = "psci";
83 capacity-dmips-mhz = <1024>;
84 dynamic-power-coefficient = <100>;
85 next-level-cache = <&L2_100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
91 power-domains = <&CPU_PD1>;
92 power-domain-names = "psci";
93 #cooling-cells = <2>;
94 L2_100: l2-cache {
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&L3_0>;
107 enable-method = "psci";
108 capacity-dmips-mhz = <1024>;
109 dynamic-power-coefficient = <100>;
110 next-level-cache = <&L2_200>;
111 qcom,freq-domain = <&cpufreq_hw 0>;
112 operating-points-v2 = <&cpu0_opp_table>;
116 power-domains = <&CPU_PD2>;
117 power-domain-names = "psci";
118 #cooling-cells = <2>;
119 L2_200: l2-cache {
121 cache-level = <2>;
122 cache-unified;
123 next-level-cache = <&L3_0>;
132 enable-method = "psci";
133 capacity-dmips-mhz = <1024>;
134 dynamic-power-coefficient = <100>;
135 next-level-cache = <&L2_300>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
137 operating-points-v2 = <&cpu0_opp_table>;
141 power-domains = <&CPU_PD3>;
142 power-domain-names = "psci";
143 #cooling-cells = <2>;
144 L2_300: l2-cache {
146 cache-level = <2>;
147 cache-unified;
148 next-level-cache = <&L3_0>;
157 enable-method = "psci";
158 capacity-dmips-mhz = <1024>;
159 dynamic-power-coefficient = <100>;
160 next-level-cache = <&L2_400>;
161 qcom,freq-domain = <&cpufreq_hw 0>;
162 operating-points-v2 = <&cpu0_opp_table>;
166 power-domains = <&CPU_PD4>;
167 power-domain-names = "psci";
168 #cooling-cells = <2>;
169 L2_400: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&L3_0>;
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
184 dynamic-power-coefficient = <100>;
185 next-level-cache = <&L2_500>;
186 qcom,freq-domain = <&cpufreq_hw 0>;
187 operating-points-v2 = <&cpu0_opp_table>;
191 power-domains = <&CPU_PD5>;
192 power-domain-names = "psci";
193 #cooling-cells = <2>;
194 L2_500: l2-cache {
196 cache-level = <2>;
197 cache-unified;
198 next-level-cache = <&L3_0>;
207 enable-method = "psci";
208 capacity-dmips-mhz = <1894>;
209 dynamic-power-coefficient = <703>;
210 next-level-cache = <&L2_600>;
211 qcom,freq-domain = <&cpufreq_hw 1>;
212 operating-points-v2 = <&cpu6_opp_table>;
216 power-domains = <&CPU_PD6>;
217 power-domain-names = "psci";
218 #cooling-cells = <2>;
219 L2_600: l2-cache {
221 cache-level = <2>;
222 cache-unified;
223 next-level-cache = <&L3_0>;
232 enable-method = "psci";
233 capacity-dmips-mhz = <1894>;
234 dynamic-power-coefficient = <703>;
235 next-level-cache = <&L2_700>;
236 qcom,freq-domain = <&cpufreq_hw 1>;
237 operating-points-v2 = <&cpu6_opp_table>;
241 power-domains = <&CPU_PD7>;
242 power-domain-names = "psci";
243 #cooling-cells = <2>;
244 L2_700: l2-cache {
246 cache-level = <2>;
247 cache-unified;
248 next-level-cache = <&L3_0>;
252 cpu-map {
288 domain-idle-states {
289 CLUSTER_SLEEP_PC: cluster-sleep-0 {
290 compatible = "domain-idle-state";
291 arm,psci-suspend-param = <0x41000044>;
292 entry-latency-us = <2752>;
293 exit-latency-us = <3048>;
294 min-residency-us = <6118>;
297 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
298 compatible = "domain-idle-state";
299 arm,psci-suspend-param = <0x41001244>;
300 entry-latency-us = <3638>;
301 exit-latency-us = <4562>;
302 min-residency-us = <8467>;
305 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
306 compatible = "domain-idle-state";
307 arm,psci-suspend-param = <0x4100b244>;
308 entry-latency-us = <3263>;
309 exit-latency-us = <6562>;
310 min-residency-us = <9987>;
314 cpu_idle_states: idle-states {
315 entry-method = "psci";
317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
318 compatible = "arm,idle-state";
319 idle-state-name = "little-power-collapse";
320 arm,psci-suspend-param = <0x40000003>;
321 entry-latency-us = <549>;
322 exit-latency-us = <901>;
323 min-residency-us = <1774>;
324 local-timer-stop;
327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
328 compatible = "arm,idle-state";
329 idle-state-name = "little-rail-power-collapse";
330 arm,psci-suspend-param = <0x40000004>;
331 entry-latency-us = <702>;
332 exit-latency-us = <915>;
333 min-residency-us = <4001>;
334 local-timer-stop;
337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
338 compatible = "arm,idle-state";
339 idle-state-name = "big-power-collapse";
340 arm,psci-suspend-param = <0x40000003>;
341 entry-latency-us = <523>;
342 exit-latency-us = <1244>;
343 min-residency-us = <2207>;
344 local-timer-stop;
347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
348 compatible = "arm,idle-state";
349 idle-state-name = "big-rail-power-collapse";
350 arm,psci-suspend-param = <0x40000004>;
351 entry-latency-us = <526>;
352 exit-latency-us = <1854>;
353 min-residency-us = <5555>;
354 local-timer-stop;
361 compatible = "qcom,scm-sm6350", "qcom,scm";
362 #reset-cells = <1>;
372 cpu0_opp_table: opp-table-cpu0 {
373 compatible = "operating-points-v2";
374 opp-shared;
376 opp-300000000 {
377 opp-hz = /bits/ 64 <300000000>;
378 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
379 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
382 opp-576000000 {
383 opp-hz = /bits/ 64 <576000000>;
384 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
387 opp-768000000 {
388 opp-hz = /bits/ 64 <768000000>;
389 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
392 opp-1017600000 {
393 opp-hz = /bits/ 64 <1017600000>;
394 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
397 opp-1248000000 {
398 opp-hz = /bits/ 64 <1248000000>;
399 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
402 opp-1324800000 {
403 opp-hz = /bits/ 64 <1324800000>;
404 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
407 opp-1516800000 {
408 opp-hz = /bits/ 64 <1516800000>;
409 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
412 opp-1612800000 {
413 opp-hz = /bits/ 64 <1612800000>;
414 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
417 opp-1708800000 {
418 opp-hz = /bits/ 64 <1708800000>;
419 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
423 cpu6_opp_table: opp-table-cpu6 {
424 compatible = "operating-points-v2";
425 opp-shared;
427 opp-300000000 {
428 opp-hz = /bits/ 64 <300000000>;
429 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
432 opp-787200000 {
433 opp-hz = /bits/ 64 <787200000>;
434 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
437 opp-979200000 {
438 opp-hz = /bits/ 64 <979200000>;
439 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
442 opp-1036800000 {
443 opp-hz = /bits/ 64 <1036800000>;
444 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
447 opp-1248000000 {
448 opp-hz = /bits/ 64 <1248000000>;
449 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
452 opp-1401600000 {
453 opp-hz = /bits/ 64 <1401600000>;
454 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
457 opp-1555200000 {
458 opp-hz = /bits/ 64 <1555200000>;
459 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
462 opp-1766400000 {
463 opp-hz = /bits/ 64 <1766400000>;
464 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
467 opp-1900800000 {
468 opp-hz = /bits/ 64 <1900800000>;
469 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
472 opp-2073600000 {
473 opp-hz = /bits/ 64 <2073600000>;
474 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
478 qup_opp_table: opp-table-qup {
479 compatible = "operating-points-v2";
481 opp-75000000 {
482 opp-hz = /bits/ 64 <75000000>;
483 required-opps = <&rpmhpd_opp_low_svs>;
486 opp-100000000 {
487 opp-hz = /bits/ 64 <100000000>;
488 required-opps = <&rpmhpd_opp_svs>;
491 opp-128000000 {
492 opp-hz = /bits/ 64 <128000000>;
493 required-opps = <&rpmhpd_opp_nom>;
498 compatible = "arm,armv8-pmuv3";
503 compatible = "arm,psci-1.0";
506 CPU_PD0: power-domain-cpu0 {
507 #power-domain-cells = <0>;
508 power-domains = <&CLUSTER_PD>;
509 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
512 CPU_PD1: power-domain-cpu1 {
513 #power-domain-cells = <0>;
514 power-domains = <&CLUSTER_PD>;
515 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
518 CPU_PD2: power-domain-cpu2 {
519 #power-domain-cells = <0>;
520 power-domains = <&CLUSTER_PD>;
521 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
524 CPU_PD3: power-domain-cpu3 {
525 #power-domain-cells = <0>;
526 power-domains = <&CLUSTER_PD>;
527 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
530 CPU_PD4: power-domain-cpu4 {
531 #power-domain-cells = <0>;
532 power-domains = <&CLUSTER_PD>;
533 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
536 CPU_PD5: power-domain-cpu5 {
537 #power-domain-cells = <0>;
538 power-domains = <&CLUSTER_PD>;
539 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
542 CPU_PD6: power-domain-cpu6 {
543 #power-domain-cells = <0>;
544 power-domains = <&CLUSTER_PD>;
545 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
548 CPU_PD7: power-domain-cpu7 {
549 #power-domain-cells = <0>;
550 power-domains = <&CLUSTER_PD>;
551 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
554 CLUSTER_PD: power-domain-cpu-cluster0 {
555 #power-domain-cells = <0>;
556 domain-idle-states = <&CLUSTER_SLEEP_PC
562 reserved_memory: reserved-memory {
563 #address-cells = <2>;
564 #size-cells = <2>;
569 no-map;
574 no-map;
578 compatible = "qcom,cmd-db";
580 no-map;
585 no-map;
590 no-map;
595 no-map;
600 no-map;
605 no-map;
610 no-map;
615 no-map;
620 no-map;
625 no-map;
630 no-map;
635 no-map;
640 no-map;
645 no-map;
650 no-map;
655 no-map;
660 no-map;
665 no-map;
670 no-map;
676 record-size = <0x1000>;
677 console-size = <0x40000>;
678 pmsg-size = <0x20000>;
679 ecc-size = <16>;
680 no-map;
685 no-map;
691 memory-region = <&smem_mem>;
695 smp2p-adsp {
698 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
704 qcom,local-pid = <0>;
705 qcom,remote-pid = <2>;
707 smp2p_adsp_out: master-kernel {
708 qcom,entry-name = "master-kernel";
709 #qcom,smem-state-cells = <1>;
712 smp2p_adsp_in: slave-kernel {
713 qcom,entry-name = "slave-kernel";
714 interrupt-controller;
715 #interrupt-cells = <2>;
719 smp2p-cdsp {
722 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
728 qcom,local-pid = <0>;
729 qcom,remote-pid = <5>;
731 smp2p_cdsp_out: master-kernel {
732 qcom,entry-name = "master-kernel";
733 #qcom,smem-state-cells = <1>;
736 smp2p_cdsp_in: slave-kernel {
737 qcom,entry-name = "slave-kernel";
738 interrupt-controller;
739 #interrupt-cells = <2>;
743 smp2p-mpss {
747 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
753 qcom,local-pid = <0>;
754 qcom,remote-pid = <1>;
756 modem_smp2p_out: master-kernel {
757 qcom,entry-name = "master-kernel";
758 #qcom,smem-state-cells = <1>;
761 modem_smp2p_in: slave-kernel {
762 qcom,entry-name = "slave-kernel";
763 interrupt-controller;
764 #interrupt-cells = <2>;
767 ipa_smp2p_out: ipa-ap-to-modem {
768 qcom,entry-name = "ipa";
769 #qcom,smem-state-cells = <1>;
772 ipa_smp2p_in: ipa-modem-to-ap {
773 qcom,entry-name = "ipa";
774 interrupt-controller;
775 #interrupt-cells = <2>;
780 #address-cells = <2>;
781 #size-cells = <2>;
783 dma-ranges = <0 0 0 0 0x10 0>;
784 compatible = "simple-bus";
786 gcc: clock-controller@100000 {
787 compatible = "qcom,gcc-sm6350";
789 #clock-cells = <1>;
790 #reset-cells = <1>;
791 #power-domain-cells = <1>;
792 clock-names = "bi_tcxo",
801 compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
804 interrupt-controller;
805 #interrupt-cells = <3>;
806 #mbox-cells = <2>;
810 compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
812 #address-cells = <1>;
813 #size-cells = <1>;
815 gpu_speed_bin: gpu-speed-bin@2015 {
822 compatible = "qcom,prng-ee";
825 clock-names = "core";
829 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
833 reg-names = "hc", "cqhci", "ice";
837 interrupt-names = "hc_irq", "pwr_irq";
843 clock-names = "iface", "core", "xo";
845 qcom,dll-config = <0x000f642c>;
846 qcom,ddr-config = <0x80040868>;
847 power-domains = <&rpmhpd SM6350_CX>;
848 operating-points-v2 = <&sdhc1_opp_table>;
849 bus-width = <8>;
850 non-removable;
851 supports-cqe;
855 sdhc1_opp_table: opp-table {
856 compatible = "operating-points-v2";
858 opp-19200000 {
859 opp-hz = /bits/ 64 <19200000>;
860 required-opps = <&rpmhpd_opp_min_svs>;
863 opp-100000000 {
864 opp-hz = /bits/ 64 <100000000>;
865 required-opps = <&rpmhpd_opp_low_svs>;
868 opp-384000000 {
869 opp-hz = /bits/ 64 <384000000>;
870 required-opps = <&rpmhpd_opp_svs_l1>;
875 gpi_dma0: dma-controller@800000 {
876 compatible = "qcom,sm6350-gpi-dma";
888 dma-channels = <10>;
889 dma-channel-mask = <0x1f>;
891 #dma-cells = <3>;
896 compatible = "qcom,geni-se-qup";
898 clock-names = "m-ahb", "s-ahb";
901 #address-cells = <2>;
902 #size-cells = <2>;
908 compatible = "qcom,geni-i2c";
910 clock-names = "se";
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_i2c0_default>;
917 dma-names = "tx", "rx";
918 #address-cells = <1>;
919 #size-cells = <0>;
923 interconnect-names = "qup-core", "qup-config", "qup-memory";
928 compatible = "qcom,geni-uart";
930 clock-names = "se";
932 pinctrl-names = "default";
933 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
935 power-domains = <&rpmhpd SM6350_CX>;
936 operating-points-v2 = <&qup_opp_table>;
939 interconnect-names = "qup-core", "qup-config";
944 compatible = "qcom,geni-i2c";
946 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_i2c2_default>;
953 dma-names = "tx", "rx";
954 #address-cells = <1>;
955 #size-cells = <0>;
959 interconnect-names = "qup-core", "qup-config", "qup-memory";
964 gpi_dma1: dma-controller@900000 {
965 compatible = "qcom,sm6350-gpi-dma";
977 dma-channels = <10>;
978 dma-channel-mask = <0x3f>;
980 #dma-cells = <3>;
985 compatible = "qcom,geni-se-qup";
987 clock-names = "m-ahb", "s-ahb";
990 #address-cells = <2>;
991 #size-cells = <2>;
997 compatible = "qcom,geni-i2c";
999 clock-names = "se";
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&qup_i2c6_default>;
1006 dma-names = "tx", "rx";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 compatible = "qcom,geni-i2c";
1019 clock-names = "se";
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&qup_i2c7_default>;
1026 dma-names = "tx", "rx";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1037 compatible = "qcom,geni-i2c";
1039 clock-names = "se";
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&qup_i2c8_default>;
1046 dma-names = "tx", "rx";
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1052 interconnect-names = "qup-core", "qup-config", "qup-memory";
1057 compatible = "qcom,geni-debug-uart";
1059 clock-names = "se";
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&qup_uart9_default>;
1066 interconnect-names = "qup-core", "qup-config";
1071 compatible = "qcom,geni-i2c";
1073 clock-names = "se";
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&qup_i2c10_default>;
1080 dma-names = "tx", "rx";
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1086 interconnect-names = "qup-core", "qup-config", "qup-memory";
1092 compatible = "qcom,sm6350-config-noc";
1094 #interconnect-cells = <2>;
1095 qcom,bcm-voters = <&apps_bcm_voter>;
1099 compatible = "qcom,sm6350-system-noc";
1101 #interconnect-cells = <2>;
1102 qcom,bcm-voters = <&apps_bcm_voter>;
1104 clk_virt: interconnect-clk-virt {
1105 compatible = "qcom,sm6350-clk-virt";
1106 #interconnect-cells = <2>;
1107 qcom,bcm-voters = <&apps_bcm_voter>;
1112 compatible = "qcom,sm6350-aggre1-noc";
1114 #interconnect-cells = <2>;
1115 qcom,bcm-voters = <&apps_bcm_voter>;
1119 compatible = "qcom,sm6350-aggre2-noc";
1121 #interconnect-cells = <2>;
1122 qcom,bcm-voters = <&apps_bcm_voter>;
1124 compute_noc: interconnect-compute-noc {
1125 compatible = "qcom,sm6350-compute-noc";
1126 #interconnect-cells = <2>;
1127 qcom,bcm-voters = <&apps_bcm_voter>;
1132 compatible = "qcom,sm6350-mmss-noc";
1134 #interconnect-cells = <2>;
1135 qcom,bcm-voters = <&apps_bcm_voter>;
1139 compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
1140 "jedec,ufs-2.0";
1143 reg-names = "std", "ice";
1146 phy-names = "ufsphy";
1147 lanes-per-direction = <2>;
1148 #reset-cells = <1>;
1150 reset-names = "rst";
1152 power-domains = <&gcc UFS_PHY_GDSC>;
1156 clock-names = "core_clk",
1174 freq-table-hz =
1189 compatible = "qcom,sm6350-qmp-ufs-phy";
1191 #address-cells = <2>;
1192 #size-cells = <2>;
1195 clock-names = "ref",
1201 reset-names = "ufsphy";
1211 #phy-cells = <0>;
1216 compatible = "qcom,sm6350-ipa";
1223 reg-names = "ipa-reg",
1224 "ipa-shared",
1227 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1231 interrupt-names = "ipa",
1233 "ipa-clock-query",
1234 "ipa-setup-ready";
1237 clock-names = "core";
1242 interconnect-names = "memory", "imem", "config";
1244 qcom,smem-states = <&ipa_smp2p_out 0>,
1246 qcom,smem-state-names = "ipa-clock-enabled-valid",
1247 "ipa-clock-enabled";
1253 compatible = "qcom,tcsr-mutex";
1255 #hwlock-cells = <1>;
1259 compatible = "qcom,sm6350-adsp-pas";
1262 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
1267 interrupt-names = "wdog", "fatal", "ready",
1268 "handover", "stop-ack";
1271 clock-names = "xo";
1273 power-domains = <&rpmhpd SM6350_LCX>,
1275 power-domain-names = "lcx", "lmx";
1277 memory-region = <&pil_adsp_mem>;
1281 qcom,smem-states = <&smp2p_adsp_out 0>;
1282 qcom,smem-state-names = "stop";
1286 glink-edge {
1287 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
1294 qcom,remote-pid = <2>;
1298 qcom,glink-channels = "fastrpcglink-apps-dsp";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1303 compute-cb@3 {
1304 compatible = "qcom,fastrpc-compute-cb";
1309 compute-cb@4 {
1310 compatible = "qcom,fastrpc-compute-cb";
1315 compute-cb@5 {
1316 compatible = "qcom,fastrpc-compute-cb";
1326 compatible = "qcom,adreno-619.0", "qcom,adreno";
1329 reg-names = "kgsl_3d0_reg_memory",
1334 operating-points-v2 = <&gpu_opp_table>;
1336 nvmem-cells = <&gpu_speed_bin>;
1337 nvmem-cell-names = "speed_bin";
1341 zap-shader {
1342 memory-region = <&pil_gpu_mem>;
1345 gpu_opp_table: opp-table {
1346 compatible = "operating-points-v2";
1348 opp-850000000 {
1349 opp-hz = /bits/ 64 <850000000>;
1350 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1351 opp-supported-hw = <0x02>;
1354 opp-800000000 {
1355 opp-hz = /bits/ 64 <800000000>;
1356 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1357 opp-supported-hw = <0x04>;
1360 opp-650000000 {
1361 opp-hz = /bits/ 64 <650000000>;
1362 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1363 opp-supported-hw = <0x08>;
1366 opp-565000000 {
1367 opp-hz = /bits/ 64 <565000000>;
1368 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1369 opp-supported-hw = <0x10>;
1372 opp-430000000 {
1373 opp-hz = /bits/ 64 <430000000>;
1374 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1375 opp-supported-hw = <0xff>;
1378 opp-355000000 {
1379 opp-hz = /bits/ 64 <355000000>;
1380 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1381 opp-supported-hw = <0xff>;
1384 opp-253000000 {
1385 opp-hz = /bits/ 64 <253000000>;
1386 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1387 opp-supported-hw = <0xff>;
1393 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1395 #iommu-cells = <1>;
1396 #global-interrupts = <2>;
1411 clock-names = "ahb",
1415 power-domains = <&gpucc GPU_CX_GDSC>;
1419 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1423 reg-names = "gmu",
1429 interrupt-names = "hfi",
1437 clock-names = "ahb",
1443 power-domains = <&gpucc GPU_CX_GDSC>,
1445 power-domain-names = "cx",
1450 operating-points-v2 = <&gmu_opp_table>;
1454 gmu_opp_table: opp-table {
1455 compatible = "operating-points-v2";
1457 opp-200000000 {
1458 opp-hz = /bits/ 64 <200000000>;
1459 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1464 gpucc: clock-controller@3d90000 {
1465 compatible = "qcom,sm6350-gpucc";
1470 clock-names = "bi_tcxo",
1473 #clock-cells = <1>;
1474 #reset-cells = <1>;
1475 #power-domain-cells = <1>;
1479 compatible = "qcom,sm6350-mpss-pas";
1482 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1488 interrupt-names = "wdog", "fatal", "ready", "handover",
1489 "stop-ack", "shutdown-ack";
1492 clock-names = "xo";
1494 power-domains = <&rpmhpd SM6350_CX>,
1496 power-domain-names = "cx", "mss";
1498 memory-region = <&pil_modem_mem>;
1502 qcom,smem-states = <&modem_smp2p_out 0>;
1503 qcom,smem-state-names = "stop";
1507 glink-edge {
1508 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1514 qcom,remote-pid = <1>;
1519 compatible = "qcom,sm6350-cdsp-pas";
1522 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1527 interrupt-names = "wdog", "fatal", "ready",
1528 "handover", "stop-ack";
1531 clock-names = "xo";
1533 power-domains = <&rpmhpd SM6350_CX>,
1535 power-domain-names = "cx", "mx";
1537 memory-region = <&pil_cdsp_mem>;
1541 qcom,smem-states = <&smp2p_cdsp_out 0>;
1542 qcom,smem-state-names = "stop";
1546 glink-edge {
1547 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1554 qcom,remote-pid = <5>;
1558 qcom,glink-channels = "fastrpcglink-apps-dsp";
1560 #address-cells = <1>;
1561 #size-cells = <0>;
1563 compute-cb@1 {
1564 compatible = "qcom,fastrpc-compute-cb";
1569 compute-cb@2 {
1570 compatible = "qcom,fastrpc-compute-cb";
1575 compute-cb@3 {
1576 compatible = "qcom,fastrpc-compute-cb";
1581 compute-cb@4 {
1582 compatible = "qcom,fastrpc-compute-cb";
1587 compute-cb@5 {
1588 compatible = "qcom,fastrpc-compute-cb";
1593 compute-cb@6 {
1594 compatible = "qcom,fastrpc-compute-cb";
1599 compute-cb@7 {
1600 compatible = "qcom,fastrpc-compute-cb";
1605 compute-cb@8 {
1606 compatible = "qcom,fastrpc-compute-cb";
1617 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
1622 interrupt-names = "hc_irq", "pwr_irq";
1628 clock-names = "iface", "core", "xo";
1632 interconnect-names = "sdhc-ddr", "cpu-sdhc";
1634 pinctrl-0 = <&sdc2_on_state>;
1635 pinctrl-1 = <&sdc2_off_state>;
1636 pinctrl-names = "default", "sleep";
1638 qcom,dll-config = <0x0007642c>;
1639 qcom,ddr-config = <0x80040868>;
1640 power-domains = <&rpmhpd SM6350_CX>;
1641 operating-points-v2 = <&sdhc2_opp_table>;
1642 bus-width = <4>;
1646 sdhc2_opp_table: opp-table {
1647 compatible = "operating-points-v2";
1649 opp-100000000 {
1650 opp-hz = /bits/ 64 <100000000>;
1651 required-opps = <&rpmhpd_opp_svs_l1>;
1652 opp-peak-kBps = <790000 131000>;
1653 opp-avg-kBps = <50000 50000>;
1656 opp-202000000 {
1657 opp-hz = /bits/ 64 <202000000>;
1658 required-opps = <&rpmhpd_opp_nom>;
1659 opp-peak-kBps = <3190000 294000>;
1660 opp-avg-kBps = <261438 300000>;
1666 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
1669 #phy-cells = <0>;
1672 clock-names = "cfg_ahb", "ref";
1678 compatible = "qcom,sm6350-qmp-usb3-dp-phy";
1685 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
1687 power-domains = <&gcc USB30_PRIM_GDSC>;
1691 reset-names = "phy", "common";
1693 #clock-cells = <1>;
1694 #phy-cells = <1>;
1700 compatible = "qcom,sm6350-dc-noc";
1702 #interconnect-cells = <2>;
1703 qcom,bcm-voters = <&apps_bcm_voter>;
1706 system-cache-controller@9200000 {
1707 compatible = "qcom,sm6350-llcc";
1709 reg-names = "llcc0_base", "llcc_broadcast_base";
1713 compatible = "qcom,sm6350-gem-noc";
1715 #interconnect-cells = <2>;
1716 qcom,bcm-voters = <&apps_bcm_voter>;
1720 compatible = "qcom,sm6350-npu-noc";
1722 #interconnect-cells = <2>;
1723 qcom,bcm-voters = <&apps_bcm_voter>;
1727 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
1731 operating-points-v2 = <&llcc_bwmon_opp_table>;
1735 llcc_bwmon_opp_table: opp-table {
1736 compatible = "operating-points-v2";
1738 opp-0 {
1739 opp-peak-kBps = <2288000>;
1742 opp-1 {
1743 opp-peak-kBps = <4577000>;
1746 opp-2 {
1747 opp-peak-kBps = <7110000>;
1750 opp-3 {
1751 opp-peak-kBps = <9155000>;
1754 opp-4 {
1755 opp-peak-kBps = <12298000>;
1758 opp-5 {
1759 opp-peak-kBps = <14236000>;
1766 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
1770 operating-points-v2 = <&cpu_bwmon_opp_table>;
1774 cpu_bwmon_opp_table: opp-table {
1775 compatible = "operating-points-v2";
1777 opp-0 {
1778 opp-peak-kBps = <762000>;
1781 opp-1 {
1782 opp-peak-kBps = <1144000>;
1785 opp-2 {
1786 opp-peak-kBps = <1720000>;
1789 opp-3 {
1790 opp-peak-kBps = <2086000>;
1793 opp-4 {
1794 opp-peak-kBps = <2597000>;
1797 opp-5 {
1798 opp-peak-kBps = <2929000>;
1801 opp-6 {
1802 opp-peak-kBps = <3879000>;
1805 opp-7 {
1806 opp-peak-kBps = <5161000>;
1809 opp-8 {
1810 opp-peak-kBps = <5931000>;
1813 opp-9 {
1814 opp-peak-kBps = <6881000>;
1817 opp-10 {
1818 opp-peak-kBps = <7980000>;
1824 compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
1827 #address-cells = <2>;
1828 #size-cells = <2>;
1836 clock-names = "cfg_noc",
1842 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1847 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1850 power-domains = <&gcc USB30_PRIM_GDSC>;
1856 interconnect-names = "usb-ddr", "apps-usb";
1865 snps,has-lpm-erratum;
1866 snps,hird-threshold = /bits/ 8 <0x10>;
1868 phy-names = "usb2-phy", "usb3-phy";
1873 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1876 power-domains = <&camcc TITAN_TOP_GDSC>;
1884 clock-names = "camnoc_axi",
1891 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1893 assigned-clock-rates = <80000000>, <37500000>;
1895 pinctrl-0 = <&cci0_default &cci1_default>;
1896 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1897 pinctrl-names = "default", "sleep";
1899 #address-cells = <1>;
1900 #size-cells = <0>;
1904 cci0_i2c0: i2c-bus@0 {
1906 clock-frequency = <1000000>;
1907 #address-cells = <1>;
1908 #size-cells = <0>;
1911 cci0_i2c1: i2c-bus@1 {
1913 clock-frequency = <1000000>;
1914 #address-cells = <1>;
1915 #size-cells = <0>;
1920 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
1923 power-domains = <&camcc TITAN_TOP_GDSC>;
1931 clock-names = "camnoc_axi",
1938 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
1940 assigned-clock-rates = <80000000>, <37500000>;
1942 pinctrl-0 = <&cci2_default>;
1943 pinctrl-1 = <&cci2_sleep>;
1944 pinctrl-names = "default", "sleep";
1946 #address-cells = <1>;
1947 #size-cells = <0>;
1951 cci1_i2c0: i2c-bus@0 {
1953 clock-frequency = <1000000>;
1954 #address-cells = <1>;
1955 #size-cells = <0>;
1961 camcc: clock-controller@ad00000 {
1962 compatible = "qcom,sm6350-camcc";
1965 #clock-cells = <1>;
1966 #reset-cells = <1>;
1967 #power-domain-cells = <1>;
1970 mdss: display-subsystem@ae00000 {
1971 compatible = "qcom,sm6350-mdss";
1973 reg-names = "mdss";
1976 interrupt-controller;
1977 #interrupt-cells = <1>;
1982 clock-names = "iface",
1986 power-domains = <&dispcc MDSS_GDSC>;
1989 #address-cells = <2>;
1990 #size-cells = <2>;
1995 mdss_mdp: display-controller@ae01000 {
1996 compatible = "qcom,sm6350-dpu";
1999 reg-names = "mdp", "vbif";
2001 interrupt-parent = <&mdss>;
2010 clock-names = "bus",
2017 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2018 assigned-clock-rates = <19200000>;
2020 operating-points-v2 = <&mdp_opp_table>;
2021 power-domains = <&rpmhpd SM6350_CX>;
2024 #address-cells = <1>;
2025 #size-cells = <0>;
2031 remote-endpoint = <&mdss_dsi0_in>;
2036 mdp_opp_table: opp-table {
2037 compatible = "operating-points-v2";
2039 opp-19200000 {
2040 opp-hz = /bits/ 64 <19200000>;
2041 required-opps = <&rpmhpd_opp_min_svs>;
2044 opp-200000000 {
2045 opp-hz = /bits/ 64 <200000000>;
2046 required-opps = <&rpmhpd_opp_low_svs>;
2049 opp-300000000 {
2050 opp-hz = /bits/ 64 <300000000>;
2051 required-opps = <&rpmhpd_opp_svs>;
2054 opp-373333333 {
2055 opp-hz = /bits/ 64 <373333333>;
2056 required-opps = <&rpmhpd_opp_svs_l1>;
2059 opp-448000000 {
2060 opp-hz = /bits/ 64 <448000000>;
2061 required-opps = <&rpmhpd_opp_nom>;
2064 opp-560000000 {
2065 opp-hz = /bits/ 64 <560000000>;
2066 required-opps = <&rpmhpd_opp_turbo>;
2072 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2074 reg-names = "dsi_ctrl";
2076 interrupt-parent = <&mdss>;
2085 clock-names = "byte",
2092 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2094 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2096 operating-points-v2 = <&mdss_dsi_opp_table>;
2097 power-domains = <&rpmhpd SM6350_MX>;
2100 phy-names = "dsi";
2102 #address-cells = <1>;
2103 #size-cells = <0>;
2108 #address-cells = <1>;
2109 #size-cells = <0>;
2115 remote-endpoint = <&dpu_intf1_out>;
2127 mdss_dsi_opp_table: opp-table {
2128 compatible = "operating-points-v2";
2130 opp-187500000 {
2131 opp-hz = /bits/ 64 <187500000>;
2132 required-opps = <&rpmhpd_opp_low_svs>;
2135 opp-300000000 {
2136 opp-hz = /bits/ 64 <300000000>;
2137 required-opps = <&rpmhpd_opp_svs>;
2140 opp-358000000 {
2141 opp-hz = /bits/ 64 <358000000>;
2142 required-opps = <&rpmhpd_opp_svs_l1>;
2148 compatible = "qcom,dsi-phy-10nm";
2152 reg-names = "dsi_phy",
2156 #clock-cells = <1>;
2157 #phy-cells = <0>;
2161 clock-names = "iface", "ref";
2167 dispcc: clock-controller@af00000 {
2168 compatible = "qcom,sm6350-dispcc";
2176 clock-names = "bi_tcxo",
2182 #clock-cells = <1>;
2183 #reset-cells = <1>;
2184 #power-domain-cells = <1>;
2187 pdc: interrupt-controller@b220000 {
2188 compatible = "qcom,sm6350-pdc", "qcom,pdc";
2190 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
2192 #interrupt-cells = <2>;
2193 interrupt-parent = <&intc>;
2194 interrupt-controller;
2197 tsens0: thermal-sensor@c263000 {
2198 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2202 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2204 interrupt-names = "uplow", "critical";
2205 #thermal-sensor-cells = <1>;
2208 tsens1: thermal-sensor@c265000 {
2209 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
2213 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2215 interrupt-names = "uplow", "critical";
2216 #thermal-sensor-cells = <1>;
2219 aoss_qmp: power-management@c300000 {
2220 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
2222 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
2226 #clock-cells = <0>;
2230 compatible = "qcom,spmi-pmic-arb";
2236 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2237 interrupt-names = "periph_irq";
2238 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2241 #address-cells = <2>;
2242 #size-cells = <0>;
2243 interrupt-controller;
2244 #interrupt-cells = <4>;
2248 compatible = "qcom,sm6350-tlmm";
2259 gpio-controller;
2260 #gpio-cells = <2>;
2261 interrupt-controller;
2262 #interrupt-cells = <2>;
2263 gpio-ranges = <&tlmm 0 0 157>;
2264 wakeup-parent = <&pdc>;
2266 cci0_default: cci0-default-state {
2269 drive-strength = <2>;
2270 bias-pull-up;
2273 cci0_sleep: cci0-sleep-state {
2276 drive-strength = <2>;
2277 bias-pull-down;
2280 cci1_default: cci1-default-state {
2283 drive-strength = <2>;
2284 bias-pull-up;
2287 cci1_sleep: cci1-sleep-state {
2290 drive-strength = <2>;
2291 bias-pull-down;
2294 cci2_default: cci2-default-state {
2297 drive-strength = <2>;
2298 bias-pull-up;
2301 cci2_sleep: cci2-sleep-state {
2304 drive-strength = <2>;
2305 bias-pull-down;
2308 sdc2_off_state: sdc2-off-state {
2309 clk-pins {
2311 drive-strength = <2>;
2312 bias-disable;
2315 cmd-pins {
2317 drive-strength = <2>;
2318 bias-pull-up;
2321 data-pins {
2323 drive-strength = <2>;
2324 bias-pull-up;
2328 sdc2_on_state: sdc2-on-state {
2329 clk-pins {
2331 drive-strength = <16>;
2332 bias-disable;
2335 cmd-pins {
2337 drive-strength = <10>;
2338 bias-pull-up;
2341 data-pins {
2343 drive-strength = <10>;
2344 bias-pull-up;
2348 qup_uart9_default: qup-uart9-default-state {
2351 drive-strength = <2>;
2352 bias-disable;
2355 qup_i2c0_default: qup-i2c0-default-state {
2358 drive-strength = <2>;
2359 bias-pull-up;
2362 qup_i2c2_default: qup-i2c2-default-state {
2365 drive-strength = <2>;
2366 bias-pull-up;
2369 qup_i2c6_default: qup-i2c6-default-state {
2372 drive-strength = <2>;
2373 bias-pull-up;
2376 qup_i2c7_default: qup-i2c7-default-state {
2379 drive-strength = <2>;
2380 bias-pull-up;
2383 qup_i2c8_default: qup-i2c8-default-state {
2386 drive-strength = <2>;
2387 bias-pull-up;
2390 qup_i2c10_default: qup-i2c10-default-state {
2393 drive-strength = <2>;
2394 bias-pull-up;
2397 qup_uart1_cts: qup-uart1-cts-default-state {
2400 drive-strength = <2>;
2401 bias-disable;
2404 qup_uart1_rts: qup-uart1-rts-default-state {
2407 drive-strength = <2>;
2408 bias-pull-down;
2411 qup_uart1_rx: qup-uart1-rx-default-state {
2414 drive-strength = <2>;
2415 bias-disable;
2418 qup_uart1_tx: qup-uart1-tx-default-state {
2421 drive-strength = <2>;
2422 bias-pull-up;
2427 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
2429 #iommu-cells = <2>;
2430 #global-interrupts = <1>;
2514 intc: interrupt-controller@17a00000 {
2515 compatible = "arm,gic-v3";
2516 #interrupt-cells = <3>;
2517 interrupt-controller;
2524 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
2531 compatible = "arm,armv7-timer-mem";
2533 clock-frequency = <19200000>;
2534 #address-cells = <1>;
2535 #size-cells = <1>;
2539 frame-number = <0>;
2547 frame-number = <1>;
2554 frame-number = <2>;
2561 frame-number = <3>;
2568 frame-number = <4>;
2575 frame-number = <5>;
2582 frame-number = <6>;
2590 compatible = "qcom,rpmh-rsc";
2595 reg-names = "drv-0", "drv-1", "drv-2";
2599 qcom,tcs-offset = <0xd00>;
2600 qcom,drv-id = <2>;
2601 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
2603 power-domains = <&CLUSTER_PD>;
2605 rpmhcc: clock-controller {
2606 compatible = "qcom,sm6350-rpmh-clk";
2607 #clock-cells = <1>;
2608 clock-names = "xo";
2612 rpmhpd: power-controller {
2613 compatible = "qcom,sm6350-rpmhpd";
2614 #power-domain-cells = <1>;
2615 operating-points-v2 = <&rpmhpd_opp_table>;
2617 rpmhpd_opp_table: opp-table {
2618 compatible = "operating-points-v2";
2621 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2625 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2629 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2633 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2637 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2641 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2645 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2649 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2653 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2657 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2662 apps_bcm_voter: bcm-voter {
2663 compatible = "qcom,bcm-voter";
2668 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
2672 clock-names = "xo", "alternate";
2674 #interconnect-cells = <1>;
2678 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
2680 reg-names = "freq-domain0", "freq-domain1";
2682 clock-names = "xo", "alternate";
2684 #freq-domain-cells = <1>;
2685 #clock-cells = <1>;
2689 compatible = "qcom,wcn3990-wifi";
2691 reg-names = "membase";
2692 memory-region = <&wlan_fw_mem>;
2706 qcom,msa-fixed-perm;
2712 compatible = "arm,armv8-timer";
2713 clock-frequency = <19200000>;