Lines Matching +full:msm8996 +full:- +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
21 xo_board: xo-board {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <19200000>;
25 clock-output-names = "xo_board";
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <32000>;
32 clock-output-names = "sleep_clk";
37 #address-cells = <2>;
38 #size-cells = <0>;
44 enable-method = "psci";
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
47 L2_0: l2-cache {
49 cache-level = <2>;
50 cache-unified;
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
67 enable-method = "psci";
68 capacity-dmips-mhz = <1024>;
69 next-level-cache = <&L2_0>;
76 enable-method = "psci";
77 capacity-dmips-mhz = <1024>;
78 next-level-cache = <&L2_0>;
85 enable-method = "psci";
86 capacity-dmips-mhz = <1638>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
90 cache-level = <2>;
91 cache-unified;
99 enable-method = "psci";
100 capacity-dmips-mhz = <1638>;
101 next-level-cache = <&L2_1>;
108 enable-method = "psci";
109 capacity-dmips-mhz = <1638>;
110 next-level-cache = <&L2_1>;
117 enable-method = "psci";
118 capacity-dmips-mhz = <1638>;
119 next-level-cache = <&L2_1>;
122 cpu-map {
163 compatible = "qcom,scm-sm6125", "qcom,scm";
164 #reset-cells = <1>;
175 compatible = "arm,armv8-pmuv3";
180 compatible = "arm,psci-1.0";
185 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc";
187 glink-edge {
188 compatible = "qcom,glink-rpm";
191 qcom,rpm-msg-ram = <&rpm_msg_ram>;
194 rpm_requests: rpm-requests {
195 compatible = "qcom,rpm-sm6125";
196 qcom,glink-channels = "rpm_requests";
198 rpmcc: clock-controller {
199 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
200 #clock-cells = <1>;
203 rpmpd: power-controller {
204 compatible = "qcom,sm6125-rpmpd";
205 #power-domain-cells = <1>;
206 operating-points-v2 = <&rpmpd_opp_table>;
208 rpmpd_opp_table: opp-table {
209 compatible = "operating-points-v2";
212 opp-level = <RPM_SMD_LEVEL_RETENTION>;
216 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
220 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
224 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
228 opp-level = <RPM_SMD_LEVEL_SVS>;
232 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
236 opp-level = <RPM_SMD_LEVEL_NOM>;
240 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
244 opp-level = <RPM_SMD_LEVEL_TURBO>;
248 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
256 reserved_memory: reserved-memory {
257 #address-cells = <2>;
258 #size-cells = <2>;
263 no-map;
268 no-map;
273 no-map;
278 no-map;
283 no-map;
288 no-map;
293 no-map;
298 no-map;
303 no-map;
308 no-map;
313 no-map;
318 no-map;
323 no-map;
328 no-map;
333 no-map;
338 no-map;
343 no-map;
348 no-map;
353 no-map;
358 no-map;
363 no-map;
369 memory-region = <&smem_mem>;
374 #address-cells = <1>;
375 #size-cells = <1>;
377 compatible = "simple-bus";
380 compatible = "qcom,tcsr-mutex";
382 #hwlock-cells = <1>;
386 compatible = "qcom,sm6125-tlmm";
390 reg-names = "west", "south", "east";
392 gpio-controller;
393 gpio-ranges = <&tlmm 0 0 134>;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
398 sdc2_off_state: sdc2-off-state {
399 clk-pins {
401 drive-strength = <2>;
402 bias-disable;
405 cmd-pins {
407 drive-strength = <2>;
408 bias-pull-up;
411 data-pins {
413 drive-strength = <2>;
414 bias-pull-up;
418 sdc2_on_state: sdc2-on-state {
419 clk-pins {
421 drive-strength = <16>;
422 bias-disable;
425 cmd-pins {
427 drive-strength = <10>;
428 bias-pull-up;
431 data-pins {
433 drive-strength = <10>;
434 bias-pull-up;
438 qup_i2c0_default: qup-i2c0-default-state {
441 drive-strength = <2>;
442 bias-disable;
445 qup_i2c0_sleep: qup-i2c0-sleep-state {
448 drive-strength = <2>;
449 bias-pull-up;
452 qup_i2c1_default: qup-i2c1-default-state {
455 drive-strength = <2>;
456 bias-disable;
459 qup_i2c1_sleep: qup-i2c1-sleep-state {
462 drive-strength = <2>;
463 bias-pull-up;
466 qup_i2c2_default: qup-i2c2-default-state {
469 drive-strength = <2>;
470 bias-disable;
473 qup_i2c2_sleep: qup-i2c2-sleep-state {
476 drive-strength = <2>;
477 bias-pull-up;
480 qup_i2c3_default: qup-i2c3-default-state {
483 drive-strength = <2>;
484 bias-disable;
487 qup_i2c3_sleep: qup-i2c3-sleep-state {
490 drive-strength = <2>;
491 bias-pull-up;
494 qup_i2c4_default: qup-i2c4-default-state {
497 drive-strength = <2>;
498 bias-disable;
501 qup_i2c4_sleep: qup-i2c4-sleep-state {
504 drive-strength = <2>;
505 bias-pull-up;
508 qup_i2c5_default: qup-i2c5-default-state {
511 drive-strength = <2>;
512 bias-disable;
515 qup_i2c5_sleep: qup-i2c5-sleep-state {
518 drive-strength = <2>;
519 bias-pull-up;
522 qup_i2c6_default: qup-i2c6-default-state {
525 drive-strength = <2>;
526 bias-disable;
529 qup_i2c6_sleep: qup-i2c6-sleep-state {
532 drive-strength = <2>;
533 bias-pull-up;
536 qup_i2c7_default: qup-i2c7-default-state {
539 drive-strength = <2>;
540 bias-disable;
543 qup_i2c7_sleep: qup-i2c7-sleep-state {
546 drive-strength = <2>;
547 bias-pull-up;
550 qup_i2c8_default: qup-i2c8-default-state {
553 drive-strength = <2>;
554 bias-disable;
557 qup_i2c8_sleep: qup-i2c8-sleep-state {
560 drive-strength = <2>;
561 bias-pull-up;
564 qup_i2c9_default: qup-i2c9-default-state {
567 drive-strength = <2>;
568 bias-disable;
571 qup_i2c9_sleep: qup-i2c9-sleep-state {
574 drive-strength = <2>;
575 bias-pull-up;
578 qup_spi0_default: qup-spi0-default-state {
581 drive-strength = <6>;
582 bias-disable;
585 qup_spi0_sleep: qup-spi0-sleep-state {
588 drive-strength = <6>;
589 bias-disable;
592 qup_spi2_default: qup-spi2-default-state {
595 drive-strength = <6>;
596 bias-disable;
599 qup_spi2_sleep: qup-spi2-sleep-state {
602 drive-strength = <6>;
603 bias-disable;
606 qup_spi5_default: qup-spi5-default-state {
609 drive-strength = <6>;
610 bias-disable;
613 qup_spi5_sleep: qup-spi5-sleep-state {
616 drive-strength = <6>;
617 bias-disable;
620 qup_spi6_default: qup-spi6-default-state {
623 drive-strength = <6>;
624 bias-disable;
627 qup_spi6_sleep: qup-spi6-sleep-state {
630 drive-strength = <6>;
631 bias-disable;
634 qup_spi8_default: qup-spi8-default-state {
637 drive-strength = <6>;
638 bias-disable;
641 qup_spi8_sleep: qup-spi8-sleep-state {
644 drive-strength = <6>;
645 bias-disable;
648 qup_spi9_default: qup-spi9-default-state {
651 drive-strength = <6>;
652 bias-disable;
655 qup_spi9_sleep: qup-spi9-sleep-state {
658 drive-strength = <6>;
659 bias-disable;
663 gcc: clock-controller@1400000 {
664 compatible = "qcom,gcc-sm6125";
666 #clock-cells = <1>;
667 #reset-cells = <1>;
668 #power-domain-cells = <1>;
669 clock-names = "bi_tcxo", "sleep_clk";
674 compatible = "qcom,msm8996-qusb2-phy";
676 #phy-cells = <0>;
680 clock-names = "cfg_ahb", "ref";
687 compatible = "qcom,rpm-msg-ram";
692 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
694 reg-names = "hc", "cqhci";
698 interrupt-names = "hc_irq", "pwr_irq";
703 clock-names = "iface", "core", "xo";
706 power-domains = <&rpmpd SM6125_VDDCX>;
708 qcom,dll-config = <0x000f642c>;
709 qcom,ddr-config = <0x80040873>;
711 bus-width = <8>;
712 non-removable;
713 supports-cqe;
719 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
721 reg-names = "hc";
725 interrupt-names = "hc_irq", "pwr_irq";
730 clock-names = "iface", "core", "xo";
733 pinctrl-0 = <&sdc2_on_state>;
734 pinctrl-1 = <&sdc2_off_state>;
735 pinctrl-names = "default", "sleep";
737 power-domains = <&rpmpd SM6125_VDDCX>;
739 qcom,dll-config = <0x0007642c>;
740 qcom,ddr-config = <0x80040873>;
742 bus-width = <4>;
747 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
749 reg-names = "std", "ice";
760 clock-names = "core_clk",
768 freq-table-hz = <50000000 240000000>,
778 reset-names = "rst";
779 #reset-cells = <1>;
782 phy-names = "ufsphy";
784 lanes-per-direction = <1>;
792 compatible = "qcom,sm6125-qmp-ufs-phy";
797 clock-names = "ref",
801 reset-names = "ufsphy";
803 power-domains = <&gcc UFS_PHY_GDSC>;
805 #phy-cells = <0>;
810 gpi_dma0: dma-controller@4a00000 {
811 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
821 dma-channels = <8>;
822 dma-channel-mask = <0x1f>;
824 #dma-cells = <3>;
829 compatible = "qcom,geni-se-qup";
833 clock-names = "m-ahb", "s-ahb";
835 #address-cells = <1>;
836 #size-cells = <1>;
841 compatible = "qcom,geni-i2c";
844 clock-names = "se";
846 pinctrl-0 = <&qup_i2c0_default>;
847 pinctrl-1 = <&qup_i2c0_sleep>;
848 pinctrl-names = "default", "sleep";
851 dma-names = "tx", "rx";
852 #address-cells = <1>;
853 #size-cells = <0>;
858 compatible = "qcom,geni-spi";
861 clock-names = "se";
863 pinctrl-0 = <&qup_spi0_default>;
864 pinctrl-1 = <&qup_spi0_sleep>;
865 pinctrl-names = "default", "sleep";
868 dma-names = "tx", "rx";
869 #address-cells = <1>;
870 #size-cells = <0>;
875 compatible = "qcom,geni-i2c";
878 clock-names = "se";
880 pinctrl-0 = <&qup_i2c1_default>;
881 pinctrl-1 = <&qup_i2c1_sleep>;
882 pinctrl-names = "default", "sleep";
885 dma-names = "tx", "rx";
886 #address-cells = <1>;
887 #size-cells = <0>;
892 compatible = "qcom,geni-i2c";
895 clock-names = "se";
897 pinctrl-0 = <&qup_i2c2_default>;
898 pinctrl-1 = <&qup_i2c2_sleep>;
899 pinctrl-names = "default", "sleep";
902 dma-names = "tx", "rx";
903 #address-cells = <1>;
904 #size-cells = <0>;
909 compatible = "qcom,geni-spi";
912 clock-names = "se";
914 pinctrl-0 = <&qup_spi2_default>;
915 pinctrl-1 = <&qup_spi2_sleep>;
916 pinctrl-names = "default", "sleep";
919 dma-names = "tx", "rx";
920 #address-cells = <1>;
921 #size-cells = <0>;
926 compatible = "qcom,geni-i2c";
929 clock-names = "se";
931 pinctrl-0 = <&qup_i2c3_default>;
932 pinctrl-1 = <&qup_i2c3_sleep>;
933 pinctrl-names = "default", "sleep";
936 dma-names = "tx", "rx";
937 #address-cells = <1>;
938 #size-cells = <0>;
943 compatible = "qcom,geni-i2c";
946 clock-names = "se";
948 pinctrl-0 = <&qup_i2c4_default>;
949 pinctrl-1 = <&qup_i2c4_sleep>;
950 pinctrl-names = "default", "sleep";
953 dma-names = "tx", "rx";
954 #address-cells = <1>;
955 #size-cells = <0>;
960 gpi_dma1: dma-controller@4c00000 {
961 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
971 dma-channels = <8>;
972 dma-channel-mask = <0x0f>;
974 #dma-cells = <3>;
979 compatible = "qcom,geni-se-qup";
983 clock-names = "m-ahb", "s-ahb";
985 #address-cells = <1>;
986 #size-cells = <1>;
991 compatible = "qcom,geni-i2c";
994 clock-names = "se";
996 pinctrl-0 = <&qup_i2c5_default>;
997 pinctrl-1 = <&qup_i2c5_sleep>;
998 pinctrl-names = "default", "sleep";
1001 dma-names = "tx", "rx";
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1008 compatible = "qcom,geni-spi";
1011 clock-names = "se";
1013 pinctrl-0 = <&qup_spi5_default>;
1014 pinctrl-1 = <&qup_spi5_sleep>;
1015 pinctrl-names = "default", "sleep";
1018 dma-names = "tx", "rx";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1025 compatible = "qcom,geni-i2c";
1028 clock-names = "se";
1030 pinctrl-0 = <&qup_i2c6_default>;
1031 pinctrl-1 = <&qup_i2c6_sleep>;
1032 pinctrl-names = "default", "sleep";
1035 dma-names = "tx", "rx";
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1042 compatible = "qcom,geni-spi";
1045 clock-names = "se";
1047 pinctrl-0 = <&qup_spi6_default>;
1048 pinctrl-1 = <&qup_spi6_sleep>;
1049 pinctrl-names = "default", "sleep";
1052 dma-names = "tx", "rx";
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1059 compatible = "qcom,geni-i2c";
1062 clock-names = "se";
1064 pinctrl-0 = <&qup_i2c7_default>;
1065 pinctrl-1 = <&qup_i2c7_sleep>;
1066 pinctrl-names = "default", "sleep";
1069 dma-names = "tx", "rx";
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1076 compatible = "qcom,geni-i2c";
1079 clock-names = "se";
1081 pinctrl-0 = <&qup_i2c8_default>;
1082 pinctrl-1 = <&qup_i2c8_sleep>;
1083 pinctrl-names = "default", "sleep";
1086 dma-names = "tx", "rx";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 compatible = "qcom,geni-spi";
1096 clock-names = "se";
1098 pinctrl-0 = <&qup_spi8_default>;
1099 pinctrl-1 = <&qup_spi8_sleep>;
1100 pinctrl-names = "default", "sleep";
1103 dma-names = "tx", "rx";
1104 #address-cells = <1>;
1105 #size-cells = <0>;
1110 compatible = "qcom,geni-i2c";
1113 clock-names = "se";
1115 pinctrl-0 = <&qup_i2c9_default>;
1116 pinctrl-1 = <&qup_i2c9_sleep>;
1117 pinctrl-names = "default", "sleep";
1120 dma-names = "tx", "rx";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1127 compatible = "qcom,geni-spi";
1130 clock-names = "se";
1132 pinctrl-0 = <&qup_spi9_default>;
1133 pinctrl-1 = <&qup_spi9_sleep>;
1134 pinctrl-names = "default", "sleep";
1137 dma-names = "tx", "rx";
1138 #address-cells = <1>;
1139 #size-cells = <0>;
1145 compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
1147 #address-cells = <1>;
1148 #size-cells = <1>;
1157 clock-names = "cfg_noc",
1164 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1166 assigned-clock-rates = <19200000>, <66666667>;
1168 power-domains = <&gcc USB30_PRIM_GDSC>;
1169 qcom,select-utmi-as-pipe-clk;
1178 phy-names = "usb2-phy";
1181 maximum-speed = "high-speed";
1187 compatible = "qcom,rpm-stats";
1192 compatible = "qcom,spmi-pmic-arb";
1198 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1199 interrupt-names = "periph_irq";
1203 #address-cells = <2>;
1204 #size-cells = <0>;
1205 interrupt-controller;
1206 #interrupt-cells = <4>;
1210 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1278 #global-interrupts = <1>;
1279 #iommu-cells = <2>;
1283 compatible = "qcom,sm6125-apcs-hmss-global",
1284 "qcom,msm8994-apcs-kpss-global";
1287 #mbox-cells = <1>;
1291 compatible = "arm,armv7-timer-mem";
1292 #address-cells = <1>;
1293 #size-cells = <1>;
1296 clock-frequency = <19200000>;
1299 frame-number = <0>;
1307 frame-number = <1>;
1314 frame-number = <2>;
1321 frame-number = <3>;
1328 frame-number = <4>;
1335 frame-number = <5>;
1342 frame-number = <6>;
1349 intc: interrupt-controller@f200000 {
1350 compatible = "arm,gic-v3";
1353 #interrupt-cells = <3>;
1354 interrupt-controller;
1360 compatible = "arm,armv8-timer";
1365 clock-frequency = <19200000>;