Lines Matching +full:adreno +full:- +full:gmu +full:- +full:wrapper
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
19 #address-cells = <2>;
20 #size-cells = <2>;
25 xo_board: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
37 #address-cells = <2>;
38 #size-cells = <0>;
45 capacity-dmips-mhz = <1024>;
46 dynamic-power-coefficient = <100>;
47 enable-method = "psci";
48 next-level-cache = <&L2_0>;
49 qcom,freq-domain = <&cpufreq_hw 0>;
50 power-domains = <&CPU_PD0>;
51 power-domain-names = "psci";
52 L2_0: l2-cache {
54 cache-level = <2>;
55 cache-unified;
64 capacity-dmips-mhz = <1024>;
65 dynamic-power-coefficient = <100>;
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
69 power-domains = <&CPU_PD1>;
70 power-domain-names = "psci";
78 capacity-dmips-mhz = <1024>;
79 dynamic-power-coefficient = <100>;
80 enable-method = "psci";
81 next-level-cache = <&L2_0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 power-domains = <&CPU_PD2>;
84 power-domain-names = "psci";
92 capacity-dmips-mhz = <1024>;
93 dynamic-power-coefficient = <100>;
94 enable-method = "psci";
95 next-level-cache = <&L2_0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
97 power-domains = <&CPU_PD3>;
98 power-domain-names = "psci";
106 enable-method = "psci";
107 capacity-dmips-mhz = <1638>;
108 dynamic-power-coefficient = <282>;
109 next-level-cache = <&L2_1>;
110 qcom,freq-domain = <&cpufreq_hw 1>;
111 power-domains = <&CPU_PD4>;
112 power-domain-names = "psci";
113 L2_1: l2-cache {
115 cache-level = <2>;
116 cache-unified;
125 capacity-dmips-mhz = <1638>;
126 dynamic-power-coefficient = <282>;
127 enable-method = "psci";
128 next-level-cache = <&L2_1>;
129 qcom,freq-domain = <&cpufreq_hw 1>;
130 power-domains = <&CPU_PD5>;
131 power-domain-names = "psci";
139 capacity-dmips-mhz = <1638>;
140 dynamic-power-coefficient = <282>;
141 enable-method = "psci";
142 next-level-cache = <&L2_1>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 power-domains = <&CPU_PD6>;
145 power-domain-names = "psci";
153 capacity-dmips-mhz = <1638>;
154 dynamic-power-coefficient = <282>;
155 enable-method = "psci";
156 next-level-cache = <&L2_1>;
157 qcom,freq-domain = <&cpufreq_hw 1>;
158 power-domains = <&CPU_PD7>;
159 power-domain-names = "psci";
162 cpu-map {
200 idle-states {
201 entry-method = "psci";
203 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
204 compatible = "arm,idle-state";
205 idle-state-name = "silver-rail-power-collapse";
206 arm,psci-suspend-param = <0x40000003>;
207 entry-latency-us = <290>;
208 exit-latency-us = <376>;
209 min-residency-us = <1182>;
210 local-timer-stop;
213 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
214 compatible = "arm,idle-state";
215 idle-state-name = "gold-rail-power-collapse";
216 arm,psci-suspend-param = <0x40000003>;
217 entry-latency-us = <297>;
218 exit-latency-us = <324>;
219 min-residency-us = <1110>;
220 local-timer-stop;
224 domain-idle-states {
225 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x40000022>;
229 entry-latency-us = <360>;
230 exit-latency-us = <421>;
231 min-residency-us = <782>;
234 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 {
236 compatible = "domain-idle-state";
237 arm,psci-suspend-param = <0x41000044>;
238 entry-latency-us = <800>;
239 exit-latency-us = <2118>;
240 min-residency-us = <7376>;
243 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 {
245 compatible = "domain-idle-state";
246 arm,psci-suspend-param = <0x40000042>;
247 entry-latency-us = <314>;
248 exit-latency-us = <345>;
249 min-residency-us = <660>;
252 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 {
254 compatible = "domain-idle-state";
255 arm,psci-suspend-param = <0x41000044>;
256 entry-latency-us = <640>;
257 exit-latency-us = <1654>;
258 min-residency-us = <8094>;
265 compatible = "qcom,scm-sm6115", "qcom,scm";
266 #reset-cells = <1>;
277 compatible = "arm,armv8-pmuv3";
282 compatible = "arm,psci-1.0";
285 CPU_PD0: power-domain-cpu0 {
286 #power-domain-cells = <0>;
287 power-domains = <&CLUSTER_0_PD>;
288 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
291 CPU_PD1: power-domain-cpu1 {
292 #power-domain-cells = <0>;
293 power-domains = <&CLUSTER_0_PD>;
294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
297 CPU_PD2: power-domain-cpu2 {
298 #power-domain-cells = <0>;
299 power-domains = <&CLUSTER_0_PD>;
300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
303 CPU_PD3: power-domain-cpu3 {
304 #power-domain-cells = <0>;
305 power-domains = <&CLUSTER_0_PD>;
306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
309 CPU_PD4: power-domain-cpu4 {
310 #power-domain-cells = <0>;
311 power-domains = <&CLUSTER_1_PD>;
312 domain-idle-states = <&BIG_CPU_SLEEP_0>;
315 CPU_PD5: power-domain-cpu5 {
316 #power-domain-cells = <0>;
317 power-domains = <&CLUSTER_1_PD>;
318 domain-idle-states = <&BIG_CPU_SLEEP_0>;
321 CPU_PD6: power-domain-cpu6 {
322 #power-domain-cells = <0>;
323 power-domains = <&CLUSTER_1_PD>;
324 domain-idle-states = <&BIG_CPU_SLEEP_0>;
327 CPU_PD7: power-domain-cpu7 {
328 #power-domain-cells = <0>;
329 power-domains = <&CLUSTER_1_PD>;
330 domain-idle-states = <&BIG_CPU_SLEEP_0>;
333 CLUSTER_0_PD: power-domain-cpu-cluster0 {
334 #power-domain-cells = <0>;
335 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>;
338 CLUSTER_1_PD: power-domain-cpu-cluster1 {
339 #power-domain-cells = <0>;
340 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>;
345 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
347 glink-edge {
348 compatible = "qcom,glink-rpm";
351 qcom,rpm-msg-ram = <&rpm_msg_ram>;
354 rpm_requests: rpm-requests {
355 compatible = "qcom,rpm-sm6115";
356 qcom,glink-channels = "rpm_requests";
358 rpmcc: clock-controller {
359 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
361 clock-names = "xo";
362 #clock-cells = <1>;
365 rpmpd: power-controller {
366 compatible = "qcom,sm6115-rpmpd";
367 #power-domain-cells = <1>;
368 operating-points-v2 = <&rpmpd_opp_table>;
370 rpmpd_opp_table: opp-table {
371 compatible = "operating-points-v2";
374 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
378 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
382 opp-level = <RPM_SMD_LEVEL_SVS>;
386 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
390 opp-level = <RPM_SMD_LEVEL_NOM>;
394 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
398 opp-level = <RPM_SMD_LEVEL_TURBO>;
402 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
410 reserved_memory: reserved-memory {
411 #address-cells = <2>;
412 #size-cells = <2>;
417 no-map;
422 no-map;
427 no-map;
433 no-map;
436 qcom,rpm-msg-ram = <&rpm_msg_ram>;
441 no-map;
446 no-map;
451 no-map;
456 no-map;
461 no-map;
466 no-map;
471 no-map;
476 no-map;
481 no-map;
486 no-map;
491 no-map;
496 no-map;
500 compatible = "qcom,rmtfs-mem";
502 no-map;
504 qcom,client-id = <1>;
509 smp2p-adsp {
517 qcom,local-pid = <0>;
518 qcom,remote-pid = <2>;
520 adsp_smp2p_out: master-kernel {
521 qcom,entry-name = "master-kernel";
522 #qcom,smem-state-cells = <1>;
525 adsp_smp2p_in: slave-kernel {
526 qcom,entry-name = "slave-kernel";
528 interrupt-controller;
529 #interrupt-cells = <2>;
533 smp2p-cdsp {
541 qcom,local-pid = <0>;
542 qcom,remote-pid = <5>;
544 cdsp_smp2p_out: master-kernel {
545 qcom,entry-name = "master-kernel";
546 #qcom,smem-state-cells = <1>;
549 cdsp_smp2p_in: slave-kernel {
550 qcom,entry-name = "slave-kernel";
552 interrupt-controller;
553 #interrupt-cells = <2>;
557 smp2p-mpss {
565 qcom,local-pid = <0>;
566 qcom,remote-pid = <1>;
568 modem_smp2p_out: master-kernel {
569 qcom,entry-name = "master-kernel";
570 #qcom,smem-state-cells = <1>;
573 modem_smp2p_in: slave-kernel {
574 qcom,entry-name = "slave-kernel";
576 interrupt-controller;
577 #interrupt-cells = <2>;
582 compatible = "simple-bus";
583 #address-cells = <2>;
584 #size-cells = <2>;
586 dma-ranges = <0 0 0 0 0x10 0>;
589 compatible = "qcom,tcsr-mutex";
591 #hwlock-cells = <1>;
595 compatible = "qcom,sm6115-tlmm";
599 reg-names = "west", "south", "east";
601 gpio-controller;
602 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
603 #gpio-cells = <2>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
607 qup_i2c0_default: qup-i2c0-default-state {
610 drive-strength = <2>;
611 bias-pull-up;
614 qup_i2c1_default: qup-i2c1-default-state {
617 drive-strength = <2>;
618 bias-pull-up;
621 qup_i2c2_default: qup-i2c2-default-state {
624 drive-strength = <2>;
625 bias-pull-up;
628 qup_i2c3_default: qup-i2c3-default-state {
631 drive-strength = <2>;
632 bias-pull-up;
635 qup_i2c4_default: qup-i2c4-default-state {
638 drive-strength = <2>;
639 bias-pull-up;
642 qup_i2c5_default: qup-i2c5-default-state {
645 drive-strength = <2>;
646 bias-pull-up;
649 qup_spi0_default: qup-spi0-default-state {
652 drive-strength = <2>;
653 bias-pull-up;
656 qup_spi1_default: qup-spi1-default-state {
659 drive-strength = <2>;
660 bias-pull-up;
663 qup_spi2_default: qup-spi2-default-state {
666 drive-strength = <2>;
667 bias-pull-up;
670 qup_spi3_default: qup-spi3-default-state {
673 drive-strength = <2>;
674 bias-pull-up;
677 qup_spi4_default: qup-spi4-default-state {
680 drive-strength = <2>;
681 bias-pull-up;
684 qup_spi5_default: qup-spi5-default-state {
687 drive-strength = <2>;
688 bias-pull-up;
691 sdc1_state_on: sdc1-on-state {
692 clk-pins {
694 bias-disable;
695 drive-strength = <16>;
698 cmd-pins {
700 bias-pull-up;
701 drive-strength = <10>;
704 data-pins {
706 bias-pull-up;
707 drive-strength = <10>;
710 rclk-pins {
712 bias-pull-down;
716 sdc1_state_off: sdc1-off-state {
717 clk-pins {
719 bias-disable;
720 drive-strength = <2>;
723 cmd-pins {
725 bias-pull-up;
726 drive-strength = <2>;
729 data-pins {
731 bias-pull-up;
732 drive-strength = <2>;
735 rclk-pins {
737 bias-pull-down;
741 sdc2_state_on: sdc2-on-state {
742 clk-pins {
744 bias-disable;
745 drive-strength = <16>;
748 cmd-pins {
750 bias-pull-up;
751 drive-strength = <10>;
754 data-pins {
756 bias-pull-up;
757 drive-strength = <10>;
761 sdc2_state_off: sdc2-off-state {
762 clk-pins {
764 bias-disable;
765 drive-strength = <2>;
768 cmd-pins {
770 bias-pull-up;
771 drive-strength = <2>;
774 data-pins {
776 bias-pull-up;
777 drive-strength = <2>;
782 gcc: clock-controller@1400000 {
783 compatible = "qcom,gcc-sm6115";
786 clock-names = "bi_tcxo", "sleep_clk";
787 #clock-cells = <1>;
788 #reset-cells = <1>;
789 #power-domain-cells = <1>;
793 compatible = "qcom,sm6115-qusb2-phy";
795 #phy-cells = <0>;
798 clock-names = "cfg_ahb", "ref";
801 nvmem-cells = <&qusb2_hstx_trim>;
806 cryptobam: dma-controller@1b04000 {
807 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
811 clock-names = "bam_clk";
812 #dma-cells = <1>;
814 qcom,controlled-remotely;
823 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
826 clock-names = "core";
829 dma-names = "rx", "tx";
838 compatible = "qcom,sm6115-qmp-usb3-phy";
845 clock-names = "cfg_ahb",
852 reset-names = "phy", "phy_phy";
854 #clock-cells = <0>;
855 clock-output-names = "usb3_phy_pipe_clk_src";
857 #phy-cells = <0>;
863 compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
865 #address-cells = <1>;
866 #size-cells = <1>;
868 qusb2_hstx_trim: hstx-trim@25b {
873 gpu_speed_bin: gpu-speed-bin@6006 {
880 compatible = "qcom,prng-ee";
883 clock-names = "core";
887 compatible = "qcom,spmi-pmic-arb";
893 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
894 interrupt-names = "periph_irq";
898 #address-cells = <2>;
899 #size-cells = <0>;
900 interrupt-controller;
901 #interrupt-cells = <4>;
904 tsens0: thermal-sensor@4411000 {
905 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
911 interrupt-names = "uplow", "critical";
912 #thermal-sensor-cells = <1>;
916 compatible = "qcom,rpm-msg-ram";
921 compatible = "qcom,rpm-stats";
926 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
930 reg-names = "hc", "cqhci", "ice";
934 interrupt-names = "hc_irq", "pwr_irq";
940 clock-names = "iface", "core", "xo", "ice";
942 bus-width = <8>;
947 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
949 reg-names = "hc";
953 interrupt-names = "hc_irq", "pwr_irq";
958 clock-names = "iface", "core", "xo";
960 power-domains = <&rpmpd SM6115_VDDCX>;
961 operating-points-v2 = <&sdhc2_opp_table>;
965 bus-width = <4>;
966 qcom,dll-config = <0x0007642c>;
967 qcom,ddr-config = <0x80040868>;
970 sdhc2_opp_table: opp-table {
971 compatible = "operating-points-v2";
973 opp-100000000 {
974 opp-hz = /bits/ 64 <100000000>;
975 required-opps = <&rpmpd_opp_low_svs>;
978 opp-202000000 {
979 opp-hz = /bits/ 64 <202000000>;
980 required-opps = <&rpmpd_opp_nom>;
986 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
988 reg-names = "std", "ice";
991 phy-names = "ufsphy";
992 lanes-per-direction = <1>;
993 #reset-cells = <1>;
995 reset-names = "rst";
997 power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1008 clock-names = "core_clk",
1017 freq-table-hz = <50000000 200000000>,
1030 compatible = "qcom,sm6115-qmp-ufs-phy";
1032 #address-cells = <2>;
1033 #size-cells = <2>;
1037 clock-names = "ref", "ref_aux";
1040 reset-names = "ufsphy";
1047 #phy-cells = <0>;
1051 gpi_dma0: dma-controller@4a00000 {
1052 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1064 dma-channels = <10>;
1065 dma-channel-mask = <0xf>;
1067 #dma-cells = <3>;
1072 compatible = "qcom,geni-se-qup";
1074 clock-names = "m-ahb", "s-ahb";
1077 #address-cells = <2>;
1078 #size-cells = <2>;
1084 compatible = "qcom,geni-i2c";
1086 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c0_default>;
1093 dma-names = "tx", "rx";
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1100 compatible = "qcom,geni-spi";
1102 clock-names = "se";
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&qup_spi0_default>;
1109 dma-names = "tx", "rx";
1110 #address-cells = <1>;
1111 #size-cells = <0>;
1116 compatible = "qcom,geni-i2c";
1118 clock-names = "se";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&qup_i2c1_default>;
1125 dma-names = "tx", "rx";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1132 compatible = "qcom,geni-spi";
1134 clock-names = "se";
1136 pinctrl-names = "default";
1137 pinctrl-0 = <&qup_spi1_default>;
1141 dma-names = "tx", "rx";
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1148 compatible = "qcom,geni-i2c";
1150 clock-names = "se";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_i2c2_default>;
1157 dma-names = "tx", "rx";
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1164 compatible = "qcom,geni-spi";
1166 clock-names = "se";
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&qup_spi2_default>;
1173 dma-names = "tx", "rx";
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1180 compatible = "qcom,geni-i2c";
1182 clock-names = "se";
1184 pinctrl-names = "default";
1185 pinctrl-0 = <&qup_i2c3_default>;
1189 dma-names = "tx", "rx";
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 compatible = "qcom,geni-spi";
1198 clock-names = "se";
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&qup_spi3_default>;
1205 dma-names = "tx", "rx";
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1212 compatible = "qcom,geni-i2c";
1214 clock-names = "se";
1216 pinctrl-names = "default";
1217 pinctrl-0 = <&qup_i2c4_default>;
1221 dma-names = "tx", "rx";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1228 compatible = "qcom,geni-spi";
1230 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_spi4_default>;
1237 dma-names = "tx", "rx";
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1244 compatible = "qcom,geni-debug-uart";
1246 clock-names = "se";
1253 compatible = "qcom,geni-i2c";
1255 clock-names = "se";
1257 pinctrl-names = "default";
1258 pinctrl-0 = <&qup_i2c5_default>;
1262 dma-names = "tx", "rx";
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1269 compatible = "qcom,geni-spi";
1271 clock-names = "se";
1273 pinctrl-names = "default";
1274 pinctrl-0 = <&qup_spi5_default>;
1278 dma-names = "tx", "rx";
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1286 compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1288 #address-cells = <2>;
1289 #size-cells = <2>;
1298 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1300 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1302 assigned-clock-rates = <19200000>, <66666667>;
1306 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1309 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1310 qcom,select-utmi-as-pipe-clk;
1318 phy-names = "usb2-phy", "usb3-phy";
1322 snps,has-lpm-erratum;
1323 snps,hird-threshold = /bits/ 8 <0x10>;
1329 compatible = "qcom,adreno-610.0", "qcom,adreno";
1331 reg-names = "kgsl_3d0_reg_memory";
1333 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1340 clock-names = "core",
1344 "gmu",
1350 operating-points-v2 = <&gpu_opp_table>;
1351 power-domains = <&rpmpd SM6115_VDDCX>;
1352 qcom,gmu = <&gmu_wrapper>;
1354 nvmem-cells = <&gpu_speed_bin>;
1355 nvmem-cell-names = "speed_bin";
1359 zap-shader {
1360 memory-region = <&pil_gpu_mem>;
1363 gpu_opp_table: opp-table {
1364 compatible = "operating-points-v2";
1366 opp-320000000 {
1367 opp-hz = /bits/ 64 <320000000>;
1368 required-opps = <&rpmpd_opp_low_svs>;
1369 opp-supported-hw = <0x1f>;
1372 opp-465000000 {
1373 opp-hz = /bits/ 64 <465000000>;
1374 required-opps = <&rpmpd_opp_svs>;
1375 opp-supported-hw = <0x1f>;
1378 opp-600000000 {
1379 opp-hz = /bits/ 64 <600000000>;
1380 required-opps = <&rpmpd_opp_svs_plus>;
1381 opp-supported-hw = <0x1f>;
1384 opp-745000000 {
1385 opp-hz = /bits/ 64 <745000000>;
1386 required-opps = <&rpmpd_opp_nom>;
1387 opp-supported-hw = <0xf>;
1390 opp-820000000 {
1391 opp-hz = /bits/ 64 <820000000>;
1392 required-opps = <&rpmpd_opp_nom_plus>;
1393 opp-supported-hw = <0x7>;
1396 opp-900000000 {
1397 opp-hz = /bits/ 64 <900000000>;
1398 required-opps = <&rpmpd_opp_turbo>;
1399 opp-supported-hw = <0x7>;
1403 opp-950000000 {
1404 opp-hz = /bits/ 64 <950000000>;
1405 required-opps = <&rpmpd_opp_turbo_plus>;
1406 opp-supported-hw = <0x4>;
1409 opp-980000000 {
1410 opp-hz = /bits/ 64 <980000000>;
1411 required-opps = <&rpmpd_opp_turbo_plus>;
1412 opp-supported-hw = <0x3>;
1417 gmu_wrapper: gmu@596a000 {
1418 compatible = "qcom,adreno-gmu-wrapper";
1420 reg-names = "gmu";
1421 power-domains = <&gpucc GPU_CX_GDSC>,
1423 power-domain-names = "cx", "gx";
1426 gpucc: clock-controller@5990000 {
1427 compatible = "qcom,sm6115-gpucc";
1432 #clock-cells = <1>;
1433 #reset-cells = <1>;
1434 #power-domain-cells = <1>;
1438 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1439 "qcom,smmu-500", "arm,mmu-500";
1454 clock-names = "mem",
1457 power-domains = <&gpucc GPU_CX_GDSC>;
1459 #global-interrupts = <1>;
1460 #iommu-cells = <2>;
1463 mdss: display-subsystem@5e00000 {
1464 compatible = "qcom,sm6115-mdss";
1466 reg-names = "mdss";
1468 power-domains = <&dispcc MDSS_GDSC>;
1475 interrupt-controller;
1476 #interrupt-cells = <1>;
1481 #address-cells = <2>;
1482 #size-cells = <2>;
1487 mdp: display-controller@5e01000 {
1488 compatible = "qcom,sm6115-dpu";
1491 reg-names = "mdp", "vbif";
1499 clock-names = "bus",
1506 operating-points-v2 = <&mdp_opp_table>;
1507 power-domains = <&rpmpd SM6115_VDDCX>;
1509 interrupt-parent = <&mdss>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1519 remote-endpoint = <&mdss_dsi0_in>;
1524 mdp_opp_table: opp-table {
1525 compatible = "operating-points-v2";
1527 opp-19200000 {
1528 opp-hz = /bits/ 64 <19200000>;
1529 required-opps = <&rpmpd_opp_min_svs>;
1532 opp-192000000 {
1533 opp-hz = /bits/ 64 <192000000>;
1534 required-opps = <&rpmpd_opp_low_svs>;
1537 opp-256000000 {
1538 opp-hz = /bits/ 64 <256000000>;
1539 required-opps = <&rpmpd_opp_svs>;
1542 opp-307200000 {
1543 opp-hz = /bits/ 64 <307200000>;
1544 required-opps = <&rpmpd_opp_svs_plus>;
1547 opp-384000000 {
1548 opp-hz = /bits/ 64 <384000000>;
1549 required-opps = <&rpmpd_opp_nom>;
1555 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1557 reg-names = "dsi_ctrl";
1559 interrupt-parent = <&mdss>;
1568 clock-names = "byte",
1575 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1577 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1579 operating-points-v2 = <&dsi_opp_table>;
1580 power-domains = <&rpmpd SM6115_VDDCX>;
1583 #address-cells = <1>;
1584 #size-cells = <0>;
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1595 remote-endpoint = <&dpu_intf1_out>;
1606 dsi_opp_table: opp-table {
1607 compatible = "operating-points-v2";
1609 opp-19200000 {
1610 opp-hz = /bits/ 64 <19200000>;
1611 required-opps = <&rpmpd_opp_min_svs>;
1614 opp-164000000 {
1615 opp-hz = /bits/ 64 <164000000>;
1616 required-opps = <&rpmpd_opp_low_svs>;
1619 opp-187500000 {
1620 opp-hz = /bits/ 64 <187500000>;
1621 required-opps = <&rpmpd_opp_svs>;
1627 compatible = "qcom,dsi-phy-14nm-2290";
1631 reg-names = "dsi_phy",
1635 #clock-cells = <1>;
1636 #phy-cells = <0>;
1640 clock-names = "iface", "ref";
1646 dispcc: clock-controller@5f00000 {
1647 compatible = "qcom,sm6115-dispcc";
1654 #clock-cells = <1>;
1655 #reset-cells = <1>;
1656 #power-domain-cells = <1>;
1660 compatible = "qcom,sm6115-mpss-pas";
1663 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1669 interrupt-names = "wdog", "fatal", "ready", "handover",
1670 "stop-ack", "shutdown-ack";
1673 clock-names = "xo";
1675 power-domains = <&rpmpd SM6115_VDDCX>;
1677 memory-region = <&pil_modem_mem>;
1679 qcom,smem-states = <&modem_smp2p_out 0>;
1680 qcom,smem-state-names = "stop";
1684 glink-edge {
1687 qcom,remote-pid = <1>;
1693 compatible = "arm,coresight-stm", "arm,primecell";
1696 reg-names = "stm-base", "stm-stimulus-base";
1699 clock-names = "apb_pclk";
1703 out-ports {
1706 remote-endpoint = <&funnel_in0_in>;
1713 compatible = "arm,coresight-cti", "arm,primecell";
1717 clock-names = "apb_pclk";
1723 compatible = "arm,coresight-cti", "arm,primecell";
1727 clock-names = "apb_pclk";
1733 compatible = "arm,coresight-cti", "arm,primecell";
1737 clock-names = "apb_pclk";
1743 compatible = "arm,coresight-cti", "arm,primecell";
1747 clock-names = "apb_pclk";
1753 compatible = "arm,coresight-cti", "arm,primecell";
1757 clock-names = "apb_pclk";
1763 compatible = "arm,coresight-cti", "arm,primecell";
1767 clock-names = "apb_pclk";
1773 compatible = "arm,coresight-cti", "arm,primecell";
1777 clock-names = "apb_pclk";
1783 compatible = "arm,coresight-cti", "arm,primecell";
1787 clock-names = "apb_pclk";
1793 compatible = "arm,coresight-cti", "arm,primecell";
1797 clock-names = "apb_pclk";
1803 compatible = "arm,coresight-cti", "arm,primecell";
1807 clock-names = "apb_pclk";
1813 compatible = "arm,coresight-cti", "arm,primecell";
1817 clock-names = "apb_pclk";
1823 compatible = "arm,coresight-cti", "arm,primecell";
1827 clock-names = "apb_pclk";
1833 compatible = "arm,coresight-cti", "arm,primecell";
1837 clock-names = "apb_pclk";
1843 compatible = "arm,coresight-cti", "arm,primecell";
1847 clock-names = "apb_pclk";
1853 compatible = "arm,coresight-cti", "arm,primecell";
1857 clock-names = "apb_pclk";
1863 compatible = "arm,coresight-cti", "arm,primecell";
1867 clock-names = "apb_pclk";
1873 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1877 clock-names = "apb_pclk";
1881 out-ports {
1884 remote-endpoint = <&etr_in>;
1889 in-ports {
1892 remote-endpoint = <&etf_out>;
1899 compatible = "arm,coresight-tmc", "arm,primecell";
1903 clock-names = "apb_pclk";
1907 in-ports {
1910 remote-endpoint = <&merge_funnel_out>;
1915 out-ports {
1918 remote-endpoint = <&replicator_in>;
1925 compatible = "arm,coresight-tmc", "arm,primecell";
1929 clock-names = "apb_pclk";
1933 in-ports {
1936 remote-endpoint = <&replicator_out>;
1943 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1947 clock-names = "apb_pclk";
1951 out-ports {
1954 remote-endpoint = <&merge_funnel_in0>;
1959 in-ports {
1962 remote-endpoint = <&stm_out>;
1969 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1973 clock-names = "apb_pclk";
1977 out-ports {
1980 remote-endpoint = <&merge_funnel_in1>;
1985 in-ports {
1988 remote-endpoint = <&funnel_apss1_out>;
1995 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1999 clock-names = "apb_pclk";
2003 out-ports {
2006 remote-endpoint = <&etf_in>;
2011 in-ports {
2012 #address-cells = <1>;
2013 #size-cells = <0>;
2018 remote-endpoint = <&funnel_in0_out>;
2025 remote-endpoint = <&funnel_in1_out>;
2032 compatible = "arm,coresight-etm4x", "arm,primecell";
2036 clock-names = "apb_pclk";
2037 arm,coresight-loses-context-with-cpu;
2043 out-ports {
2046 remote-endpoint = <&funnel_apss0_in0>;
2053 compatible = "arm,coresight-etm4x", "arm,primecell";
2057 clock-names = "apb_pclk";
2058 arm,coresight-loses-context-with-cpu;
2064 out-ports {
2067 remote-endpoint = <&funnel_apss0_in1>;
2074 compatible = "arm,coresight-etm4x", "arm,primecell";
2078 clock-names = "apb_pclk";
2079 arm,coresight-loses-context-with-cpu;
2085 out-ports {
2088 remote-endpoint = <&funnel_apss0_in2>;
2095 compatible = "arm,coresight-etm4x", "arm,primecell";
2099 clock-names = "apb_pclk";
2100 arm,coresight-loses-context-with-cpu;
2106 out-ports {
2109 remote-endpoint = <&funnel_apss0_in3>;
2116 compatible = "arm,coresight-etm4x", "arm,primecell";
2120 clock-names = "apb_pclk";
2121 arm,coresight-loses-context-with-cpu;
2127 out-ports {
2130 remote-endpoint = <&funnel_apss0_in4>;
2137 compatible = "arm,coresight-etm4x", "arm,primecell";
2141 clock-names = "apb_pclk";
2142 arm,coresight-loses-context-with-cpu;
2148 out-ports {
2151 remote-endpoint = <&funnel_apss0_in5>;
2158 compatible = "arm,coresight-etm4x", "arm,primecell";
2162 clock-names = "apb_pclk";
2163 arm,coresight-loses-context-with-cpu;
2169 out-ports {
2172 remote-endpoint = <&funnel_apss0_in6>;
2179 compatible = "arm,coresight-etm4x", "arm,primecell";
2183 clock-names = "apb_pclk";
2184 arm,coresight-loses-context-with-cpu;
2190 out-ports {
2193 remote-endpoint = <&funnel_apss0_in7>;
2200 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2204 clock-names = "apb_pclk";
2208 out-ports {
2211 remote-endpoint = <&funnel_apss1_in>;
2216 in-ports {
2217 #address-cells = <1>;
2218 #size-cells = <0>;
2223 remote-endpoint = <&etm0_out>;
2230 remote-endpoint = <&etm1_out>;
2237 remote-endpoint = <&etm2_out>;
2244 remote-endpoint = <&etm3_out>;
2251 remote-endpoint = <&etm4_out>;
2258 remote-endpoint = <&etm5_out>;
2265 remote-endpoint = <&etm6_out>;
2272 remote-endpoint = <&etm7_out>;
2279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2283 clock-names = "apb_pclk";
2287 out-ports {
2290 remote-endpoint = <&funnel_in1_in>;
2295 in-ports {
2298 remote-endpoint = <&funnel_apss0_out>;
2305 compatible = "qcom,sm6115-adsp-pas";
2308 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2313 interrupt-names = "wdog", "fatal", "ready",
2314 "handover", "stop-ack";
2317 clock-names = "xo";
2319 power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2322 memory-region = <&pil_adsp_mem>;
2324 qcom,smem-states = <&adsp_smp2p_out 0>;
2325 qcom,smem-state-names = "stop";
2329 glink-edge {
2332 qcom,remote-pid = <2>;
2337 qcom,glink-channels = "fastrpcglink-apps-dsp";
2339 qcom,non-secure-domain;
2340 #address-cells = <1>;
2341 #size-cells = <0>;
2343 compute-cb@3 {
2344 compatible = "qcom,fastrpc-compute-cb";
2349 compute-cb@4 {
2350 compatible = "qcom,fastrpc-compute-cb";
2355 compute-cb@5 {
2356 compatible = "qcom,fastrpc-compute-cb";
2361 compute-cb@6 {
2362 compatible = "qcom,fastrpc-compute-cb";
2367 compute-cb@7 {
2368 compatible = "qcom,fastrpc-compute-cb";
2377 compatible = "qcom,sm6115-cdsp-pas";
2380 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2385 interrupt-names = "wdog", "fatal", "ready",
2386 "handover", "stop-ack";
2389 clock-names = "xo";
2391 power-domains = <&rpmpd SM6115_VDDCX>;
2393 memory-region = <&pil_cdsp_mem>;
2395 qcom,smem-states = <&cdsp_smp2p_out 0>;
2396 qcom,smem-state-names = "stop";
2400 glink-edge {
2403 qcom,remote-pid = <5>;
2408 qcom,glink-channels = "fastrpcglink-apps-dsp";
2410 qcom,non-secure-domain;
2411 #address-cells = <1>;
2412 #size-cells = <0>;
2414 compute-cb@1 {
2415 compatible = "qcom,fastrpc-compute-cb";
2420 compute-cb@2 {
2421 compatible = "qcom,fastrpc-compute-cb";
2426 compute-cb@3 {
2427 compatible = "qcom,fastrpc-compute-cb";
2432 compute-cb@4 {
2433 compatible = "qcom,fastrpc-compute-cb";
2438 compute-cb@5 {
2439 compatible = "qcom,fastrpc-compute-cb";
2444 compute-cb@6 {
2445 compatible = "qcom,fastrpc-compute-cb";
2456 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2458 #iommu-cells = <2>;
2459 #global-interrupts = <1>;
2529 compatible = "qcom,wcn3990-wifi";
2531 reg-names = "membase";
2532 memory-region = <&wlan_msa_mem>;
2546 qcom,msa-fixed-perm;
2551 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
2558 compatible = "qcom,sm6115-apcs-hmss-global",
2559 "qcom,msm8994-apcs-kpss-global";
2562 #mbox-cells = <1>;
2566 compatible = "arm,armv7-timer-mem";
2568 #address-cells = <2>;
2569 #size-cells = <2>;
2571 clock-frequency = <19200000>;
2575 frame-number = <0>;
2582 frame-number = <1>;
2589 frame-number = <2>;
2596 frame-number = <3>;
2603 frame-number = <4>;
2610 frame-number = <5>;
2617 frame-number = <6>;
2623 intc: interrupt-controller@f200000 {
2624 compatible = "arm,gic-v3";
2627 #interrupt-cells = <3>;
2628 interrupt-controller;
2629 interrupt-parent = <&intc>;
2630 #redistributor-regions = <1>;
2631 redistributor-stride = <0x0 0x20000>;
2636 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
2640 reg-names = "freq-domain0", "freq-domain1";
2642 clock-names = "xo", "alternate";
2644 #freq-domain-cells = <1>;
2645 #clock-cells = <1>;
2649 thermal-zones {
2650 mapss-thermal {
2651 polling-delay-passive = <0>;
2652 polling-delay = <0>;
2653 thermal-sensors = <&tsens0 0>;
2656 trip-point0 {
2662 trip-point1 {
2670 cdsp-hvx-thermal {
2671 polling-delay-passive = <0>;
2672 polling-delay = <0>;
2673 thermal-sensors = <&tsens0 1>;
2676 trip-point0 {
2682 trip-point1 {
2690 wlan-thermal {
2691 polling-delay-passive = <0>;
2692 polling-delay = <0>;
2693 thermal-sensors = <&tsens0 2>;
2696 trip-point0 {
2702 trip-point1 {
2710 camera-thermal {
2711 polling-delay-passive = <0>;
2712 polling-delay = <0>;
2713 thermal-sensors = <&tsens0 3>;
2716 trip-point0 {
2722 trip-point1 {
2730 video-thermal {
2731 polling-delay-passive = <0>;
2732 polling-delay = <0>;
2733 thermal-sensors = <&tsens0 4>;
2736 trip-point0 {
2742 trip-point1 {
2750 modem1-thermal {
2751 polling-delay-passive = <0>;
2752 polling-delay = <0>;
2753 thermal-sensors = <&tsens0 5>;
2756 trip-point0 {
2762 trip-point1 {
2770 cpu4-thermal {
2771 polling-delay-passive = <0>;
2772 polling-delay = <0>;
2773 thermal-sensors = <&tsens0 6>;
2776 cpu4_alert0: trip-point0 {
2782 cpu4_alert1: trip-point1 {
2796 cpu5-thermal {
2797 polling-delay-passive = <0>;
2798 polling-delay = <0>;
2799 thermal-sensors = <&tsens0 7>;
2802 cpu5_alert0: trip-point0 {
2808 cpu5_alert1: trip-point1 {
2822 cpu6-thermal {
2823 polling-delay-passive = <0>;
2824 polling-delay = <0>;
2825 thermal-sensors = <&tsens0 8>;
2828 cpu6_alert0: trip-point0 {
2834 cpu6_alert1: trip-point1 {
2848 cpu7-thermal {
2849 polling-delay-passive = <0>;
2850 polling-delay = <0>;
2851 thermal-sensors = <&tsens0 9>;
2854 cpu7_alert0: trip-point0 {
2860 cpu7_alert1: trip-point1 {
2874 cpu45-thermal {
2875 polling-delay-passive = <0>;
2876 polling-delay = <0>;
2877 thermal-sensors = <&tsens0 10>;
2880 cpu45_alert0: trip-point0 {
2886 cpu45_alert1: trip-point1 {
2900 cpu67-thermal {
2901 polling-delay-passive = <0>;
2902 polling-delay = <0>;
2903 thermal-sensors = <&tsens0 11>;
2906 cpu67_alert0: trip-point0 {
2912 cpu67_alert1: trip-point1 {
2926 cpu0123-thermal {
2927 polling-delay-passive = <0>;
2928 polling-delay = <0>;
2929 thermal-sensors = <&tsens0 12>;
2932 cpu0123_alert0: trip-point0 {
2938 cpu0123_alert1: trip-point1 {
2952 modem0-thermal {
2953 polling-delay-passive = <0>;
2954 polling-delay = <0>;
2955 thermal-sensors = <&tsens0 13>;
2958 trip-point0 {
2964 trip-point1 {
2972 display-thermal {
2973 polling-delay-passive = <0>;
2974 polling-delay = <0>;
2975 thermal-sensors = <&tsens0 14>;
2978 trip-point0 {
2984 trip-point1 {
2992 gpu-thermal {
2993 polling-delay-passive = <0>;
2994 polling-delay = <0>;
2995 thermal-sensors = <&tsens0 15>;
2998 trip-point0 {
3004 trip-point1 {
3014 compatible = "arm,armv8-timer";