Lines Matching +full:msm8996 +full:- +full:smmu +full:- +full:v2
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/firmware/qcom,scm.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/interconnect/qcom,osm-l3.h>
19 #include <dt-bindings/interconnect/qcom,sdm845.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/phy/phy-qcom-qusb2.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,apr.h>
26 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
27 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
28 #include <dt-bindings/thermal/thermal.h>
31 interrupt-parent = <&intc>;
33 #address-cells = <2>;
34 #size-cells = <2>;
74 xo_board: xo-board {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <38400000>;
78 clock-output-names = "xo_board";
81 sleep_clk: sleep-clk {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <32764>;
89 #address-cells = <2>;
90 #size-cells = <0>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <611>;
99 dynamic-power-coefficient = <154>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 operating-points-v2 = <&cpu0_opp_table>;
104 power-domains = <&CPU_PD0>;
105 power-domain-names = "psci";
106 #cooling-cells = <2>;
107 next-level-cache = <&L2_0>;
108 L2_0: l2-cache {
110 cache-level = <2>;
111 cache-unified;
112 next-level-cache = <&L3_0>;
113 L3_0: l3-cache {
115 cache-level = <3>;
116 cache-unified;
126 enable-method = "psci";
127 capacity-dmips-mhz = <611>;
128 dynamic-power-coefficient = <154>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
130 operating-points-v2 = <&cpu0_opp_table>;
133 power-domains = <&CPU_PD1>;
134 power-domain-names = "psci";
135 #cooling-cells = <2>;
136 next-level-cache = <&L2_100>;
137 L2_100: l2-cache {
139 cache-level = <2>;
140 cache-unified;
141 next-level-cache = <&L3_0>;
150 enable-method = "psci";
151 capacity-dmips-mhz = <611>;
152 dynamic-power-coefficient = <154>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
154 operating-points-v2 = <&cpu0_opp_table>;
157 power-domains = <&CPU_PD2>;
158 power-domain-names = "psci";
159 #cooling-cells = <2>;
160 next-level-cache = <&L2_200>;
161 L2_200: l2-cache {
163 cache-level = <2>;
164 cache-unified;
165 next-level-cache = <&L3_0>;
174 enable-method = "psci";
175 capacity-dmips-mhz = <611>;
176 dynamic-power-coefficient = <154>;
177 qcom,freq-domain = <&cpufreq_hw 0>;
178 operating-points-v2 = <&cpu0_opp_table>;
181 #cooling-cells = <2>;
182 power-domains = <&CPU_PD3>;
183 power-domain-names = "psci";
184 next-level-cache = <&L2_300>;
185 L2_300: l2-cache {
187 cache-level = <2>;
188 cache-unified;
189 next-level-cache = <&L3_0>;
198 enable-method = "psci";
199 capacity-dmips-mhz = <1024>;
200 dynamic-power-coefficient = <442>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
202 operating-points-v2 = <&cpu4_opp_table>;
205 power-domains = <&CPU_PD4>;
206 power-domain-names = "psci";
207 #cooling-cells = <2>;
208 next-level-cache = <&L2_400>;
209 L2_400: l2-cache {
211 cache-level = <2>;
212 cache-unified;
213 next-level-cache = <&L3_0>;
222 enable-method = "psci";
223 capacity-dmips-mhz = <1024>;
224 dynamic-power-coefficient = <442>;
225 qcom,freq-domain = <&cpufreq_hw 1>;
226 operating-points-v2 = <&cpu4_opp_table>;
229 power-domains = <&CPU_PD5>;
230 power-domain-names = "psci";
231 #cooling-cells = <2>;
232 next-level-cache = <&L2_500>;
233 L2_500: l2-cache {
235 cache-level = <2>;
236 cache-unified;
237 next-level-cache = <&L3_0>;
246 enable-method = "psci";
247 capacity-dmips-mhz = <1024>;
248 dynamic-power-coefficient = <442>;
249 qcom,freq-domain = <&cpufreq_hw 1>;
250 operating-points-v2 = <&cpu4_opp_table>;
253 power-domains = <&CPU_PD6>;
254 power-domain-names = "psci";
255 #cooling-cells = <2>;
256 next-level-cache = <&L2_600>;
257 L2_600: l2-cache {
259 cache-level = <2>;
260 cache-unified;
261 next-level-cache = <&L3_0>;
270 enable-method = "psci";
271 capacity-dmips-mhz = <1024>;
272 dynamic-power-coefficient = <442>;
273 qcom,freq-domain = <&cpufreq_hw 1>;
274 operating-points-v2 = <&cpu4_opp_table>;
277 power-domains = <&CPU_PD7>;
278 power-domain-names = "psci";
279 #cooling-cells = <2>;
280 next-level-cache = <&L2_700>;
281 L2_700: l2-cache {
283 cache-level = <2>;
284 cache-unified;
285 next-level-cache = <&L3_0>;
289 cpu-map {
325 cpu_idle_states: idle-states {
326 entry-method = "psci";
328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
329 compatible = "arm,idle-state";
330 idle-state-name = "little-rail-power-collapse";
331 arm,psci-suspend-param = <0x40000004>;
332 entry-latency-us = <350>;
333 exit-latency-us = <461>;
334 min-residency-us = <1890>;
335 local-timer-stop;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
339 compatible = "arm,idle-state";
340 idle-state-name = "big-rail-power-collapse";
341 arm,psci-suspend-param = <0x40000004>;
342 entry-latency-us = <264>;
343 exit-latency-us = <621>;
344 min-residency-us = <952>;
345 local-timer-stop;
349 domain-idle-states {
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
351 compatible = "domain-idle-state";
352 arm,psci-suspend-param = <0x4100c244>;
353 entry-latency-us = <3263>;
354 exit-latency-us = <6562>;
355 min-residency-us = <9987>;
362 compatible = "qcom,scm-sdm845", "qcom,scm";
372 cpu0_opp_table: opp-table-cpu0 {
373 compatible = "operating-points-v2";
374 opp-shared;
376 cpu0_opp1: opp-300000000 {
377 opp-hz = /bits/ 64 <300000000>;
378 opp-peak-kBps = <800000 4800000>;
381 cpu0_opp2: opp-403200000 {
382 opp-hz = /bits/ 64 <403200000>;
383 opp-peak-kBps = <800000 4800000>;
386 cpu0_opp3: opp-480000000 {
387 opp-hz = /bits/ 64 <480000000>;
388 opp-peak-kBps = <800000 6451200>;
391 cpu0_opp4: opp-576000000 {
392 opp-hz = /bits/ 64 <576000000>;
393 opp-peak-kBps = <800000 6451200>;
396 cpu0_opp5: opp-652800000 {
397 opp-hz = /bits/ 64 <652800000>;
398 opp-peak-kBps = <800000 7680000>;
401 cpu0_opp6: opp-748800000 {
402 opp-hz = /bits/ 64 <748800000>;
403 opp-peak-kBps = <1804000 9216000>;
406 cpu0_opp7: opp-825600000 {
407 opp-hz = /bits/ 64 <825600000>;
408 opp-peak-kBps = <1804000 9216000>;
411 cpu0_opp8: opp-902400000 {
412 opp-hz = /bits/ 64 <902400000>;
413 opp-peak-kBps = <1804000 10444800>;
416 cpu0_opp9: opp-979200000 {
417 opp-hz = /bits/ 64 <979200000>;
418 opp-peak-kBps = <1804000 11980800>;
421 cpu0_opp10: opp-1056000000 {
422 opp-hz = /bits/ 64 <1056000000>;
423 opp-peak-kBps = <1804000 11980800>;
426 cpu0_opp11: opp-1132800000 {
427 opp-hz = /bits/ 64 <1132800000>;
428 opp-peak-kBps = <2188000 13516800>;
431 cpu0_opp12: opp-1228800000 {
432 opp-hz = /bits/ 64 <1228800000>;
433 opp-peak-kBps = <2188000 15052800>;
436 cpu0_opp13: opp-1324800000 {
437 opp-hz = /bits/ 64 <1324800000>;
438 opp-peak-kBps = <2188000 16588800>;
441 cpu0_opp14: opp-1420800000 {
442 opp-hz = /bits/ 64 <1420800000>;
443 opp-peak-kBps = <3072000 18124800>;
446 cpu0_opp15: opp-1516800000 {
447 opp-hz = /bits/ 64 <1516800000>;
448 opp-peak-kBps = <3072000 19353600>;
451 cpu0_opp16: opp-1612800000 {
452 opp-hz = /bits/ 64 <1612800000>;
453 opp-peak-kBps = <4068000 19353600>;
456 cpu0_opp17: opp-1689600000 {
457 opp-hz = /bits/ 64 <1689600000>;
458 opp-peak-kBps = <4068000 20889600>;
461 cpu0_opp18: opp-1766400000 {
462 opp-hz = /bits/ 64 <1766400000>;
463 opp-peak-kBps = <4068000 22425600>;
467 cpu4_opp_table: opp-table-cpu4 {
468 compatible = "operating-points-v2";
469 opp-shared;
471 cpu4_opp1: opp-300000000 {
472 opp-hz = /bits/ 64 <300000000>;
473 opp-peak-kBps = <800000 4800000>;
476 cpu4_opp2: opp-403200000 {
477 opp-hz = /bits/ 64 <403200000>;
478 opp-peak-kBps = <800000 4800000>;
481 cpu4_opp3: opp-480000000 {
482 opp-hz = /bits/ 64 <480000000>;
483 opp-peak-kBps = <1804000 4800000>;
486 cpu4_opp4: opp-576000000 {
487 opp-hz = /bits/ 64 <576000000>;
488 opp-peak-kBps = <1804000 4800000>;
491 cpu4_opp5: opp-652800000 {
492 opp-hz = /bits/ 64 <652800000>;
493 opp-peak-kBps = <1804000 4800000>;
496 cpu4_opp6: opp-748800000 {
497 opp-hz = /bits/ 64 <748800000>;
498 opp-peak-kBps = <1804000 4800000>;
501 cpu4_opp7: opp-825600000 {
502 opp-hz = /bits/ 64 <825600000>;
503 opp-peak-kBps = <2188000 9216000>;
506 cpu4_opp8: opp-902400000 {
507 opp-hz = /bits/ 64 <902400000>;
508 opp-peak-kBps = <2188000 9216000>;
511 cpu4_opp9: opp-979200000 {
512 opp-hz = /bits/ 64 <979200000>;
513 opp-peak-kBps = <2188000 9216000>;
516 cpu4_opp10: opp-1056000000 {
517 opp-hz = /bits/ 64 <1056000000>;
518 opp-peak-kBps = <3072000 9216000>;
521 cpu4_opp11: opp-1132800000 {
522 opp-hz = /bits/ 64 <1132800000>;
523 opp-peak-kBps = <3072000 11980800>;
526 cpu4_opp12: opp-1209600000 {
527 opp-hz = /bits/ 64 <1209600000>;
528 opp-peak-kBps = <4068000 11980800>;
531 cpu4_opp13: opp-1286400000 {
532 opp-hz = /bits/ 64 <1286400000>;
533 opp-peak-kBps = <4068000 11980800>;
536 cpu4_opp14: opp-1363200000 {
537 opp-hz = /bits/ 64 <1363200000>;
538 opp-peak-kBps = <4068000 15052800>;
541 cpu4_opp15: opp-1459200000 {
542 opp-hz = /bits/ 64 <1459200000>;
543 opp-peak-kBps = <4068000 15052800>;
546 cpu4_opp16: opp-1536000000 {
547 opp-hz = /bits/ 64 <1536000000>;
548 opp-peak-kBps = <5412000 15052800>;
551 cpu4_opp17: opp-1612800000 {
552 opp-hz = /bits/ 64 <1612800000>;
553 opp-peak-kBps = <5412000 15052800>;
556 cpu4_opp18: opp-1689600000 {
557 opp-hz = /bits/ 64 <1689600000>;
558 opp-peak-kBps = <5412000 19353600>;
561 cpu4_opp19: opp-1766400000 {
562 opp-hz = /bits/ 64 <1766400000>;
563 opp-peak-kBps = <6220000 19353600>;
566 cpu4_opp20: opp-1843200000 {
567 opp-hz = /bits/ 64 <1843200000>;
568 opp-peak-kBps = <6220000 19353600>;
571 cpu4_opp21: opp-1920000000 {
572 opp-hz = /bits/ 64 <1920000000>;
573 opp-peak-kBps = <7216000 19353600>;
576 cpu4_opp22: opp-1996800000 {
577 opp-hz = /bits/ 64 <1996800000>;
578 opp-peak-kBps = <7216000 20889600>;
581 cpu4_opp23: opp-2092800000 {
582 opp-hz = /bits/ 64 <2092800000>;
583 opp-peak-kBps = <7216000 20889600>;
586 cpu4_opp24: opp-2169600000 {
587 opp-hz = /bits/ 64 <2169600000>;
588 opp-peak-kBps = <7216000 20889600>;
591 cpu4_opp25: opp-2246400000 {
592 opp-hz = /bits/ 64 <2246400000>;
593 opp-peak-kBps = <7216000 20889600>;
596 cpu4_opp26: opp-2323200000 {
597 opp-hz = /bits/ 64 <2323200000>;
598 opp-peak-kBps = <7216000 20889600>;
601 cpu4_opp27: opp-2400000000 {
602 opp-hz = /bits/ 64 <2400000000>;
603 opp-peak-kBps = <7216000 22425600>;
606 cpu4_opp28: opp-2476800000 {
607 opp-hz = /bits/ 64 <2476800000>;
608 opp-peak-kBps = <7216000 22425600>;
611 cpu4_opp29: opp-2553600000 {
612 opp-hz = /bits/ 64 <2553600000>;
613 opp-peak-kBps = <7216000 22425600>;
616 cpu4_opp30: opp-2649600000 {
617 opp-hz = /bits/ 64 <2649600000>;
618 opp-peak-kBps = <7216000 22425600>;
621 cpu4_opp31: opp-2745600000 {
622 opp-hz = /bits/ 64 <2745600000>;
623 opp-peak-kBps = <7216000 25497600>;
626 cpu4_opp32: opp-2803200000 {
627 opp-hz = /bits/ 64 <2803200000>;
628 opp-peak-kBps = <7216000 25497600>;
632 dsi_opp_table: opp-table-dsi {
633 compatible = "operating-points-v2";
635 opp-19200000 {
636 opp-hz = /bits/ 64 <19200000>;
637 required-opps = <&rpmhpd_opp_min_svs>;
640 opp-180000000 {
641 opp-hz = /bits/ 64 <180000000>;
642 required-opps = <&rpmhpd_opp_low_svs>;
645 opp-275000000 {
646 opp-hz = /bits/ 64 <275000000>;
647 required-opps = <&rpmhpd_opp_svs>;
650 opp-328580000 {
651 opp-hz = /bits/ 64 <328580000>;
652 required-opps = <&rpmhpd_opp_svs_l1>;
655 opp-358000000 {
656 opp-hz = /bits/ 64 <358000000>;
657 required-opps = <&rpmhpd_opp_nom>;
661 qspi_opp_table: opp-table-qspi {
662 compatible = "operating-points-v2";
664 opp-19200000 {
665 opp-hz = /bits/ 64 <19200000>;
666 required-opps = <&rpmhpd_opp_min_svs>;
669 opp-100000000 {
670 opp-hz = /bits/ 64 <100000000>;
671 required-opps = <&rpmhpd_opp_low_svs>;
674 opp-150000000 {
675 opp-hz = /bits/ 64 <150000000>;
676 required-opps = <&rpmhpd_opp_svs>;
679 opp-300000000 {
680 opp-hz = /bits/ 64 <300000000>;
681 required-opps = <&rpmhpd_opp_nom>;
685 qup_opp_table: opp-table-qup {
686 compatible = "operating-points-v2";
688 opp-50000000 {
689 opp-hz = /bits/ 64 <50000000>;
690 required-opps = <&rpmhpd_opp_min_svs>;
693 opp-75000000 {
694 opp-hz = /bits/ 64 <75000000>;
695 required-opps = <&rpmhpd_opp_low_svs>;
698 opp-100000000 {
699 opp-hz = /bits/ 64 <100000000>;
700 required-opps = <&rpmhpd_opp_svs>;
703 opp-128000000 {
704 opp-hz = /bits/ 64 <128000000>;
705 required-opps = <&rpmhpd_opp_nom>;
710 compatible = "arm,armv8-pmuv3";
715 compatible = "arm,psci-1.0";
718 CPU_PD0: power-domain-cpu0 {
719 #power-domain-cells = <0>;
720 power-domains = <&CLUSTER_PD>;
721 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
724 CPU_PD1: power-domain-cpu1 {
725 #power-domain-cells = <0>;
726 power-domains = <&CLUSTER_PD>;
727 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
730 CPU_PD2: power-domain-cpu2 {
731 #power-domain-cells = <0>;
732 power-domains = <&CLUSTER_PD>;
733 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
736 CPU_PD3: power-domain-cpu3 {
737 #power-domain-cells = <0>;
738 power-domains = <&CLUSTER_PD>;
739 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
742 CPU_PD4: power-domain-cpu4 {
743 #power-domain-cells = <0>;
744 power-domains = <&CLUSTER_PD>;
745 domain-idle-states = <&BIG_CPU_SLEEP_0>;
748 CPU_PD5: power-domain-cpu5 {
749 #power-domain-cells = <0>;
750 power-domains = <&CLUSTER_PD>;
751 domain-idle-states = <&BIG_CPU_SLEEP_0>;
754 CPU_PD6: power-domain-cpu6 {
755 #power-domain-cells = <0>;
756 power-domains = <&CLUSTER_PD>;
757 domain-idle-states = <&BIG_CPU_SLEEP_0>;
760 CPU_PD7: power-domain-cpu7 {
761 #power-domain-cells = <0>;
762 power-domains = <&CLUSTER_PD>;
763 domain-idle-states = <&BIG_CPU_SLEEP_0>;
766 CLUSTER_PD: power-domain-cluster {
767 #power-domain-cells = <0>;
768 domain-idle-states = <&CLUSTER_SLEEP_0>;
772 reserved-memory {
773 #address-cells = <2>;
774 #size-cells = <2>;
777 hyp_mem: hyp-mem@85700000 {
779 no-map;
782 xbl_mem: xbl-mem@85e00000 {
784 no-map;
787 aop_mem: aop-mem@85fc0000 {
789 no-map;
792 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
793 compatible = "qcom,cmd-db";
795 no-map;
801 no-map;
807 no-map;
811 compatible = "qcom,rmtfs-mem";
813 no-map;
815 qcom,client-id = <1>;
821 no-map;
824 camera_mem: camera-mem@8bf00000 {
826 no-map;
829 ipa_fw_mem: ipa-fw@8c400000 {
831 no-map;
834 ipa_gsi_mem: ipa-gsi@8c410000 {
836 no-map;
841 no-map;
846 no-map;
849 wlan_msa_mem: wlan-msa@8df00000 {
851 no-map;
856 no-map;
861 no-map;
866 no-map;
871 no-map;
876 no-map;
881 no-map;
884 mdata_mem: mpss-metadata {
885 alloc-ranges = <0 0xa0000000 0 0x20000000>;
887 no-map;
891 compatible = "shared-dma-pool";
892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
899 adsp_pas: remoteproc-adsp {
900 compatible = "qcom,sdm845-adsp-pas";
902 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
907 interrupt-names = "wdog", "fatal", "ready",
908 "handover", "stop-ack";
911 clock-names = "xo";
913 memory-region = <&adsp_mem>;
917 qcom,smem-states = <&adsp_smp2p_out 0>;
918 qcom,smem-state-names = "stop";
922 glink-edge {
925 qcom,remote-pid = <2>;
929 compatible = "qcom,apr-v2";
930 qcom,glink-channels = "apr_audio_svc";
932 #address-cells = <1>;
933 #size-cells = <0>;
939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
945 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
947 compatible = "qcom,q6afe-dais";
948 #address-cells = <1>;
949 #size-cells = <0>;
950 #sound-dai-cells = <1>;
957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
959 compatible = "qcom,q6asm-dais";
960 #address-cells = <1>;
961 #size-cells = <0>;
962 #sound-dai-cells = <1>;
970 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
972 compatible = "qcom,q6adm-routing";
973 #sound-dai-cells = <0>;
980 qcom,glink-channels = "fastrpcglink-apps-dsp";
982 qcom,non-secure-domain;
983 #address-cells = <1>;
984 #size-cells = <0>;
986 compute-cb@3 {
987 compatible = "qcom,fastrpc-compute-cb";
992 compute-cb@4 {
993 compatible = "qcom,fastrpc-compute-cb";
1001 cdsp_pas: remoteproc-cdsp {
1002 compatible = "qcom,sdm845-cdsp-pas";
1004 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
1009 interrupt-names = "wdog", "fatal", "ready",
1010 "handover", "stop-ack";
1013 clock-names = "xo";
1015 memory-region = <&cdsp_mem>;
1019 qcom,smem-states = <&cdsp_smp2p_out 0>;
1020 qcom,smem-state-names = "stop";
1024 glink-edge {
1027 qcom,remote-pid = <5>;
1031 qcom,glink-channels = "fastrpcglink-apps-dsp";
1033 qcom,non-secure-domain;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1037 compute-cb@1 {
1038 compatible = "qcom,fastrpc-compute-cb";
1043 compute-cb@2 {
1044 compatible = "qcom,fastrpc-compute-cb";
1049 compute-cb@3 {
1050 compatible = "qcom,fastrpc-compute-cb";
1055 compute-cb@4 {
1056 compatible = "qcom,fastrpc-compute-cb";
1061 compute-cb@5 {
1062 compatible = "qcom,fastrpc-compute-cb";
1067 compute-cb@6 {
1068 compatible = "qcom,fastrpc-compute-cb";
1073 compute-cb@7 {
1074 compatible = "qcom,fastrpc-compute-cb";
1079 compute-cb@8 {
1080 compatible = "qcom,fastrpc-compute-cb";
1088 smp2p-cdsp {
1096 qcom,local-pid = <0>;
1097 qcom,remote-pid = <5>;
1099 cdsp_smp2p_out: master-kernel {
1100 qcom,entry-name = "master-kernel";
1101 #qcom,smem-state-cells = <1>;
1104 cdsp_smp2p_in: slave-kernel {
1105 qcom,entry-name = "slave-kernel";
1107 interrupt-controller;
1108 #interrupt-cells = <2>;
1112 smp2p-lpass {
1120 qcom,local-pid = <0>;
1121 qcom,remote-pid = <2>;
1123 adsp_smp2p_out: master-kernel {
1124 qcom,entry-name = "master-kernel";
1125 #qcom,smem-state-cells = <1>;
1128 adsp_smp2p_in: slave-kernel {
1129 qcom,entry-name = "slave-kernel";
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1136 smp2p-mpss {
1141 qcom,local-pid = <0>;
1142 qcom,remote-pid = <1>;
1144 modem_smp2p_out: master-kernel {
1145 qcom,entry-name = "master-kernel";
1146 #qcom,smem-state-cells = <1>;
1149 modem_smp2p_in: slave-kernel {
1150 qcom,entry-name = "slave-kernel";
1151 interrupt-controller;
1152 #interrupt-cells = <2>;
1155 ipa_smp2p_out: ipa-ap-to-modem {
1156 qcom,entry-name = "ipa";
1157 #qcom,smem-state-cells = <1>;
1160 ipa_smp2p_in: ipa-modem-to-ap {
1161 qcom,entry-name = "ipa";
1162 interrupt-controller;
1163 #interrupt-cells = <2>;
1167 smp2p-slpi {
1172 qcom,local-pid = <0>;
1173 qcom,remote-pid = <3>;
1175 slpi_smp2p_out: master-kernel {
1176 qcom,entry-name = "master-kernel";
1177 #qcom,smem-state-cells = <1>;
1180 slpi_smp2p_in: slave-kernel {
1181 qcom,entry-name = "slave-kernel";
1182 interrupt-controller;
1183 #interrupt-cells = <2>;
1188 #address-cells = <2>;
1189 #size-cells = <2>;
1191 dma-ranges = <0 0 0 0 0x10 0>;
1192 compatible = "simple-bus";
1194 gcc: clock-controller@100000 {
1195 compatible = "qcom,gcc-sdm845";
1202 clock-names = "bi_tcxo",
1207 #clock-cells = <1>;
1208 #reset-cells = <1>;
1209 #power-domain-cells = <1>;
1210 power-domains = <&rpmhpd SDM845_CX>;
1214 compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
1216 #address-cells = <1>;
1217 #size-cells = <1>;
1219 qusb2p_hstx_trim: hstx-trim-primary@1eb {
1224 qusb2s_hstx_trim: hstx-trim-secondary@1eb {
1231 compatible = "qcom,prng-ee";
1234 clock-names = "core";
1237 gpi_dma0: dma-controller@800000 {
1238 #dma-cells = <3>;
1239 compatible = "qcom,sdm845-gpi-dma";
1254 dma-channels = <13>;
1255 dma-channel-mask = <0xfa>;
1261 compatible = "qcom,geni-se-qup";
1263 clock-names = "m-ahb", "s-ahb";
1267 #address-cells = <2>;
1268 #size-cells = <2>;
1271 interconnect-names = "qup-core";
1275 compatible = "qcom,geni-i2c";
1277 clock-names = "se";
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&qup_i2c0_default>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 power-domains = <&rpmhpd SDM845_CX>;
1285 operating-points-v2 = <&qup_opp_table>;
1289 interconnect-names = "qup-core", "qup-config", "qup-memory";
1292 dma-names = "tx", "rx";
1297 compatible = "qcom,geni-spi";
1299 clock-names = "se";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_spi0_default>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1308 interconnect-names = "qup-core", "qup-config";
1311 dma-names = "tx", "rx";
1316 compatible = "qcom,geni-uart";
1318 clock-names = "se";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&qup_uart0_default>;
1323 power-domains = <&rpmhpd SDM845_CX>;
1324 operating-points-v2 = <&qup_opp_table>;
1327 interconnect-names = "qup-core", "qup-config";
1332 compatible = "qcom,geni-i2c";
1334 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c1_default>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1341 power-domains = <&rpmhpd SDM845_CX>;
1342 operating-points-v2 = <&qup_opp_table>;
1346 interconnect-names = "qup-core", "qup-config", "qup-memory";
1349 dma-names = "tx", "rx";
1354 compatible = "qcom,geni-spi";
1356 clock-names = "se";
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_spi1_default>;
1361 #address-cells = <1>;
1362 #size-cells = <0>;
1365 interconnect-names = "qup-core", "qup-config";
1368 dma-names = "tx", "rx";
1373 compatible = "qcom,geni-uart";
1375 clock-names = "se";
1377 pinctrl-names = "default";
1378 pinctrl-0 = <&qup_uart1_default>;
1380 power-domains = <&rpmhpd SDM845_CX>;
1381 operating-points-v2 = <&qup_opp_table>;
1384 interconnect-names = "qup-core", "qup-config";
1389 compatible = "qcom,geni-i2c";
1391 clock-names = "se";
1393 pinctrl-names = "default";
1394 pinctrl-0 = <&qup_i2c2_default>;
1396 #address-cells = <1>;
1397 #size-cells = <0>;
1398 power-domains = <&rpmhpd SDM845_CX>;
1399 operating-points-v2 = <&qup_opp_table>;
1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dma-names = "tx", "rx";
1411 compatible = "qcom,geni-spi";
1413 clock-names = "se";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&qup_spi2_default>;
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1422 interconnect-names = "qup-core", "qup-config";
1425 dma-names = "tx", "rx";
1430 compatible = "qcom,geni-uart";
1432 clock-names = "se";
1434 pinctrl-names = "default";
1435 pinctrl-0 = <&qup_uart2_default>;
1437 power-domains = <&rpmhpd SDM845_CX>;
1438 operating-points-v2 = <&qup_opp_table>;
1441 interconnect-names = "qup-core", "qup-config";
1446 compatible = "qcom,geni-i2c";
1448 clock-names = "se";
1450 pinctrl-names = "default";
1451 pinctrl-0 = <&qup_i2c3_default>;
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455 power-domains = <&rpmhpd SDM845_CX>;
1456 operating-points-v2 = <&qup_opp_table>;
1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1463 dma-names = "tx", "rx";
1468 compatible = "qcom,geni-spi";
1470 clock-names = "se";
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_spi3_default>;
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1479 interconnect-names = "qup-core", "qup-config";
1482 dma-names = "tx", "rx";
1487 compatible = "qcom,geni-uart";
1489 clock-names = "se";
1491 pinctrl-names = "default";
1492 pinctrl-0 = <&qup_uart3_default>;
1494 power-domains = <&rpmhpd SDM845_CX>;
1495 operating-points-v2 = <&qup_opp_table>;
1498 interconnect-names = "qup-core", "qup-config";
1503 compatible = "qcom,geni-i2c";
1505 clock-names = "se";
1507 pinctrl-names = "default";
1508 pinctrl-0 = <&qup_i2c4_default>;
1510 #address-cells = <1>;
1511 #size-cells = <0>;
1512 power-domains = <&rpmhpd SDM845_CX>;
1513 operating-points-v2 = <&qup_opp_table>;
1517 interconnect-names = "qup-core", "qup-config", "qup-memory";
1520 dma-names = "tx", "rx";
1525 compatible = "qcom,geni-spi";
1527 clock-names = "se";
1529 pinctrl-names = "default";
1530 pinctrl-0 = <&qup_spi4_default>;
1532 #address-cells = <1>;
1533 #size-cells = <0>;
1536 interconnect-names = "qup-core", "qup-config";
1539 dma-names = "tx", "rx";
1544 compatible = "qcom,geni-uart";
1546 clock-names = "se";
1548 pinctrl-names = "default";
1549 pinctrl-0 = <&qup_uart4_default>;
1551 power-domains = <&rpmhpd SDM845_CX>;
1552 operating-points-v2 = <&qup_opp_table>;
1555 interconnect-names = "qup-core", "qup-config";
1560 compatible = "qcom,geni-i2c";
1562 clock-names = "se";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_i2c5_default>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1569 power-domains = <&rpmhpd SDM845_CX>;
1570 operating-points-v2 = <&qup_opp_table>;
1574 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 dma-names = "tx", "rx";
1582 compatible = "qcom,geni-spi";
1584 clock-names = "se";
1586 pinctrl-names = "default";
1587 pinctrl-0 = <&qup_spi5_default>;
1589 #address-cells = <1>;
1590 #size-cells = <0>;
1593 interconnect-names = "qup-core", "qup-config";
1596 dma-names = "tx", "rx";
1601 compatible = "qcom,geni-uart";
1603 clock-names = "se";
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&qup_uart5_default>;
1608 power-domains = <&rpmhpd SDM845_CX>;
1609 operating-points-v2 = <&qup_opp_table>;
1612 interconnect-names = "qup-core", "qup-config";
1617 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1621 pinctrl-names = "default";
1622 pinctrl-0 = <&qup_i2c6_default>;
1624 #address-cells = <1>;
1625 #size-cells = <0>;
1626 power-domains = <&rpmhpd SDM845_CX>;
1627 operating-points-v2 = <&qup_opp_table>;
1631 interconnect-names = "qup-core", "qup-config", "qup-memory";
1634 dma-names = "tx", "rx";
1639 compatible = "qcom,geni-spi";
1641 clock-names = "se";
1643 pinctrl-names = "default";
1644 pinctrl-0 = <&qup_spi6_default>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1650 interconnect-names = "qup-core", "qup-config";
1653 dma-names = "tx", "rx";
1658 compatible = "qcom,geni-uart";
1660 clock-names = "se";
1662 pinctrl-names = "default";
1663 pinctrl-0 = <&qup_uart6_default>;
1665 power-domains = <&rpmhpd SDM845_CX>;
1666 operating-points-v2 = <&qup_opp_table>;
1669 interconnect-names = "qup-core", "qup-config";
1674 compatible = "qcom,geni-i2c";
1676 clock-names = "se";
1678 pinctrl-names = "default";
1679 pinctrl-0 = <&qup_i2c7_default>;
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1683 power-domains = <&rpmhpd SDM845_CX>;
1684 operating-points-v2 = <&qup_opp_table>;
1689 compatible = "qcom,geni-spi";
1691 clock-names = "se";
1693 pinctrl-names = "default";
1694 pinctrl-0 = <&qup_spi7_default>;
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1700 interconnect-names = "qup-core", "qup-config";
1703 dma-names = "tx", "rx";
1708 compatible = "qcom,geni-uart";
1710 clock-names = "se";
1712 pinctrl-names = "default";
1713 pinctrl-0 = <&qup_uart7_default>;
1715 power-domains = <&rpmhpd SDM845_CX>;
1716 operating-points-v2 = <&qup_opp_table>;
1719 interconnect-names = "qup-core", "qup-config";
1724 gpi_dma1: dma-controller@a00000 {
1725 #dma-cells = <3>;
1726 compatible = "qcom,sdm845-gpi-dma";
1741 dma-channels = <13>;
1742 dma-channel-mask = <0xfa>;
1748 compatible = "qcom,geni-se-qup";
1750 clock-names = "m-ahb", "s-ahb";
1754 #address-cells = <2>;
1755 #size-cells = <2>;
1758 interconnect-names = "qup-core";
1762 compatible = "qcom,geni-i2c";
1764 clock-names = "se";
1766 pinctrl-names = "default";
1767 pinctrl-0 = <&qup_i2c8_default>;
1769 #address-cells = <1>;
1770 #size-cells = <0>;
1771 power-domains = <&rpmhpd SDM845_CX>;
1772 operating-points-v2 = <&qup_opp_table>;
1776 interconnect-names = "qup-core", "qup-config", "qup-memory";
1779 dma-names = "tx", "rx";
1784 compatible = "qcom,geni-spi";
1786 clock-names = "se";
1788 pinctrl-names = "default";
1789 pinctrl-0 = <&qup_spi8_default>;
1791 #address-cells = <1>;
1792 #size-cells = <0>;
1795 interconnect-names = "qup-core", "qup-config";
1798 dma-names = "tx", "rx";
1803 compatible = "qcom,geni-uart";
1805 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_uart8_default>;
1810 power-domains = <&rpmhpd SDM845_CX>;
1811 operating-points-v2 = <&qup_opp_table>;
1814 interconnect-names = "qup-core", "qup-config";
1819 compatible = "qcom,geni-i2c";
1821 clock-names = "se";
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&qup_i2c9_default>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 power-domains = <&rpmhpd SDM845_CX>;
1829 operating-points-v2 = <&qup_opp_table>;
1833 interconnect-names = "qup-core", "qup-config", "qup-memory";
1836 dma-names = "tx", "rx";
1841 compatible = "qcom,geni-spi";
1843 clock-names = "se";
1845 pinctrl-names = "default";
1846 pinctrl-0 = <&qup_spi9_default>;
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1852 interconnect-names = "qup-core", "qup-config";
1855 dma-names = "tx", "rx";
1860 compatible = "qcom,geni-debug-uart";
1862 clock-names = "se";
1864 pinctrl-names = "default";
1865 pinctrl-0 = <&qup_uart9_default>;
1867 power-domains = <&rpmhpd SDM845_CX>;
1868 operating-points-v2 = <&qup_opp_table>;
1871 interconnect-names = "qup-core", "qup-config";
1876 compatible = "qcom,geni-i2c";
1878 clock-names = "se";
1880 pinctrl-names = "default";
1881 pinctrl-0 = <&qup_i2c10_default>;
1883 #address-cells = <1>;
1884 #size-cells = <0>;
1885 power-domains = <&rpmhpd SDM845_CX>;
1886 operating-points-v2 = <&qup_opp_table>;
1890 interconnect-names = "qup-core", "qup-config", "qup-memory";
1893 dma-names = "tx", "rx";
1898 compatible = "qcom,geni-spi";
1900 clock-names = "se";
1902 pinctrl-names = "default";
1903 pinctrl-0 = <&qup_spi10_default>;
1905 #address-cells = <1>;
1906 #size-cells = <0>;
1909 interconnect-names = "qup-core", "qup-config";
1912 dma-names = "tx", "rx";
1917 compatible = "qcom,geni-uart";
1919 clock-names = "se";
1921 pinctrl-names = "default";
1922 pinctrl-0 = <&qup_uart10_default>;
1924 power-domains = <&rpmhpd SDM845_CX>;
1925 operating-points-v2 = <&qup_opp_table>;
1928 interconnect-names = "qup-core", "qup-config";
1933 compatible = "qcom,geni-i2c";
1935 clock-names = "se";
1937 pinctrl-names = "default";
1938 pinctrl-0 = <&qup_i2c11_default>;
1940 #address-cells = <1>;
1941 #size-cells = <0>;
1942 power-domains = <&rpmhpd SDM845_CX>;
1943 operating-points-v2 = <&qup_opp_table>;
1947 interconnect-names = "qup-core", "qup-config", "qup-memory";
1950 dma-names = "tx", "rx";
1955 compatible = "qcom,geni-spi";
1957 clock-names = "se";
1959 pinctrl-names = "default";
1960 pinctrl-0 = <&qup_spi11_default>;
1962 #address-cells = <1>;
1963 #size-cells = <0>;
1966 interconnect-names = "qup-core", "qup-config";
1969 dma-names = "tx", "rx";
1974 compatible = "qcom,geni-uart";
1976 clock-names = "se";
1978 pinctrl-names = "default";
1979 pinctrl-0 = <&qup_uart11_default>;
1981 power-domains = <&rpmhpd SDM845_CX>;
1982 operating-points-v2 = <&qup_opp_table>;
1985 interconnect-names = "qup-core", "qup-config";
1990 compatible = "qcom,geni-i2c";
1992 clock-names = "se";
1994 pinctrl-names = "default";
1995 pinctrl-0 = <&qup_i2c12_default>;
1997 #address-cells = <1>;
1998 #size-cells = <0>;
1999 power-domains = <&rpmhpd SDM845_CX>;
2000 operating-points-v2 = <&qup_opp_table>;
2004 interconnect-names = "qup-core", "qup-config", "qup-memory";
2007 dma-names = "tx", "rx";
2012 compatible = "qcom,geni-spi";
2014 clock-names = "se";
2016 pinctrl-names = "default";
2017 pinctrl-0 = <&qup_spi12_default>;
2019 #address-cells = <1>;
2020 #size-cells = <0>;
2023 interconnect-names = "qup-core", "qup-config";
2026 dma-names = "tx", "rx";
2031 compatible = "qcom,geni-uart";
2033 clock-names = "se";
2035 pinctrl-names = "default";
2036 pinctrl-0 = <&qup_uart12_default>;
2038 power-domains = <&rpmhpd SDM845_CX>;
2039 operating-points-v2 = <&qup_opp_table>;
2042 interconnect-names = "qup-core", "qup-config";
2047 compatible = "qcom,geni-i2c";
2049 clock-names = "se";
2051 pinctrl-names = "default";
2052 pinctrl-0 = <&qup_i2c13_default>;
2054 #address-cells = <1>;
2055 #size-cells = <0>;
2056 power-domains = <&rpmhpd SDM845_CX>;
2057 operating-points-v2 = <&qup_opp_table>;
2061 interconnect-names = "qup-core", "qup-config", "qup-memory";
2064 dma-names = "tx", "rx";
2069 compatible = "qcom,geni-spi";
2071 clock-names = "se";
2073 pinctrl-names = "default";
2074 pinctrl-0 = <&qup_spi13_default>;
2076 #address-cells = <1>;
2077 #size-cells = <0>;
2080 interconnect-names = "qup-core", "qup-config";
2083 dma-names = "tx", "rx";
2088 compatible = "qcom,geni-uart";
2090 clock-names = "se";
2092 pinctrl-names = "default";
2093 pinctrl-0 = <&qup_uart13_default>;
2095 power-domains = <&rpmhpd SDM845_CX>;
2096 operating-points-v2 = <&qup_opp_table>;
2099 interconnect-names = "qup-core", "qup-config";
2104 compatible = "qcom,geni-i2c";
2106 clock-names = "se";
2108 pinctrl-names = "default";
2109 pinctrl-0 = <&qup_i2c14_default>;
2111 #address-cells = <1>;
2112 #size-cells = <0>;
2113 power-domains = <&rpmhpd SDM845_CX>;
2114 operating-points-v2 = <&qup_opp_table>;
2118 interconnect-names = "qup-core", "qup-config", "qup-memory";
2121 dma-names = "tx", "rx";
2126 compatible = "qcom,geni-spi";
2128 clock-names = "se";
2130 pinctrl-names = "default";
2131 pinctrl-0 = <&qup_spi14_default>;
2133 #address-cells = <1>;
2134 #size-cells = <0>;
2137 interconnect-names = "qup-core", "qup-config";
2140 dma-names = "tx", "rx";
2145 compatible = "qcom,geni-uart";
2147 clock-names = "se";
2149 pinctrl-names = "default";
2150 pinctrl-0 = <&qup_uart14_default>;
2152 power-domains = <&rpmhpd SDM845_CX>;
2153 operating-points-v2 = <&qup_opp_table>;
2156 interconnect-names = "qup-core", "qup-config";
2161 compatible = "qcom,geni-i2c";
2163 clock-names = "se";
2165 pinctrl-names = "default";
2166 pinctrl-0 = <&qup_i2c15_default>;
2168 #address-cells = <1>;
2169 #size-cells = <0>;
2170 power-domains = <&rpmhpd SDM845_CX>;
2171 operating-points-v2 = <&qup_opp_table>;
2176 interconnect-names = "qup-core", "qup-config", "qup-memory";
2179 dma-names = "tx", "rx";
2183 compatible = "qcom,geni-spi";
2185 clock-names = "se";
2187 pinctrl-names = "default";
2188 pinctrl-0 = <&qup_spi15_default>;
2190 #address-cells = <1>;
2191 #size-cells = <0>;
2194 interconnect-names = "qup-core", "qup-config";
2197 dma-names = "tx", "rx";
2202 compatible = "qcom,geni-uart";
2204 clock-names = "se";
2206 pinctrl-names = "default";
2207 pinctrl-0 = <&qup_uart15_default>;
2209 power-domains = <&rpmhpd SDM845_CX>;
2210 operating-points-v2 = <&qup_opp_table>;
2213 interconnect-names = "qup-core", "qup-config";
2218 llcc: system-cache-controller@1100000 {
2219 compatible = "qcom,sdm845-llcc";
2223 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2229 compatible = "qcom,sdm845-dcc", "qcom,dcc";
2235 compatible = "qcom,sdm845-llcc-bwmon";
2240 operating-points-v2 = <&llcc_bwmon_opp_table>;
2242 llcc_bwmon_opp_table: opp-table {
2243 compatible = "operating-points-v2";
2247 * cpu4_opp_table bandwidth for gladiator_noc-mem_noc
2249 * bandwidth table of qcom,llccbw (qcom,bw-tbl,
2250 * bus width: 4 bytes) from msm-4.9 downstream
2253 opp-0 {
2254 opp-peak-kBps = <800000>;
2256 opp-1 {
2257 opp-peak-kBps = <1804000>;
2259 opp-2 {
2260 opp-peak-kBps = <3072000>;
2262 opp-3 {
2263 opp-peak-kBps = <5412000>;
2265 opp-4 {
2266 opp-peak-kBps = <7216000>;
2272 compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
2277 operating-points-v2 = <&cpu_bwmon_opp_table>;
2279 cpu_bwmon_opp_table: opp-table {
2280 compatible = "operating-points-v2";
2286 * from bandwidth table of qcom,cpu4-l3lat-mon
2287 * (qcom,core-dev-table, bus width: 16 bytes)
2288 * from msm-4.9 downstream kernel.
2290 opp-0 {
2291 opp-peak-kBps = <4800000>;
2293 opp-1 {
2294 opp-peak-kBps = <9216000>;
2296 opp-2 {
2297 opp-peak-kBps = <15052800>;
2299 opp-3 {
2300 opp-peak-kBps = <20889600>;
2302 opp-4 {
2303 opp-peak-kBps = <25497600>;
2309 compatible = "qcom,pcie-sdm845";
2315 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2317 linux,pci-domain = <0>;
2318 bus-range = <0x00 0xff>;
2319 num-lanes = <1>;
2321 #address-cells = <3>;
2322 #size-cells = <2>;
2328 interrupt-names = "msi";
2329 #interrupt-cells = <1>;
2330 interrupt-map-mask = <0 0 0 0x7>;
2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2343 clock-names = "pipe",
2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2369 reset-names = "pci";
2371 power-domains = <&gcc PCIE_0_GDSC>;
2374 phy-names = "pciephy";
2380 compatible = "qcom,sdm845-qmp-pcie-phy";
2382 #address-cells = <2>;
2383 #size-cells = <2>;
2389 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2392 reset-names = "phy";
2394 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2395 assigned-clock-rates = <100000000>;
2405 clock-names = "pipe0";
2407 #clock-cells = <0>;
2408 #phy-cells = <0>;
2409 clock-output-names = "pcie_0_pipe_clk";
2414 compatible = "qcom,pcie-sdm845";
2420 reg-names = "parf", "dbi", "elbi", "config", "mhi";
2422 linux,pci-domain = <1>;
2423 bus-range = <0x00 0xff>;
2424 num-lanes = <1>;
2426 #address-cells = <3>;
2427 #size-cells = <2>;
2433 interrupt-names = "msi";
2434 #interrupt-cells = <1>;
2435 interrupt-map-mask = <0 0 0 0x7>;
2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2449 clock-names = "pipe",
2458 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2459 assigned-clock-rates = <19200000>;
2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2479 reset-names = "pci";
2481 power-domains = <&gcc PCIE_1_GDSC>;
2484 phy-names = "pciephy";
2490 compatible = "qcom,sdm845-qhp-pcie-phy";
2492 #address-cells = <2>;
2493 #size-cells = <2>;
2499 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2502 reset-names = "phy";
2504 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
2505 assigned-clock-rates = <100000000>;
2514 clock-names = "pipe0";
2516 #clock-cells = <0>;
2517 #phy-cells = <0>;
2518 clock-output-names = "pcie_1_pipe_clk";
2523 compatible = "qcom,sdm845-mem-noc";
2525 #interconnect-cells = <2>;
2526 qcom,bcm-voters = <&apps_bcm_voter>;
2530 compatible = "qcom,sdm845-dc-noc";
2532 #interconnect-cells = <2>;
2533 qcom,bcm-voters = <&apps_bcm_voter>;
2537 compatible = "qcom,sdm845-config-noc";
2539 #interconnect-cells = <2>;
2540 qcom,bcm-voters = <&apps_bcm_voter>;
2544 compatible = "qcom,sdm845-system-noc";
2546 #interconnect-cells = <2>;
2547 qcom,bcm-voters = <&apps_bcm_voter>;
2551 compatible = "qcom,sdm845-aggre1-noc";
2553 #interconnect-cells = <2>;
2554 qcom,bcm-voters = <&apps_bcm_voter>;
2558 compatible = "qcom,sdm845-aggre2-noc";
2560 #interconnect-cells = <2>;
2561 qcom,bcm-voters = <&apps_bcm_voter>;
2565 compatible = "qcom,sdm845-mmss-noc";
2567 #interconnect-cells = <2>;
2568 qcom,bcm-voters = <&apps_bcm_voter>;
2572 compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
2573 "jedec,ufs-2.0";
2576 reg-names = "std", "ice";
2579 phy-names = "ufsphy";
2580 lanes-per-direction = <2>;
2581 power-domains = <&gcc UFS_PHY_GDSC>;
2582 #reset-cells = <1>;
2584 reset-names = "rst";
2588 clock-names =
2608 freq-table-hz =
2621 interconnect-names = "ufs-ddr", "cpu-ufs";
2627 compatible = "qcom,sdm845-qmp-ufs-phy";
2629 #address-cells = <2>;
2630 #size-cells = <2>;
2632 clock-names = "ref",
2638 reset-names = "ufsphy";
2647 #phy-cells = <0>;
2651 cryptobam: dma-controller@1dc4000 {
2652 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
2656 clock-names = "bam_clk";
2657 #dma-cells = <1>;
2659 qcom,controlled-remotely;
2667 compatible = "qcom,crypto-v5.4";
2672 clock-names = "iface", "bus", "core";
2674 dma-names = "rx", "tx";
2682 compatible = "qcom,sdm845-ipa";
2689 reg-names = "ipa-reg",
2690 "ipa-shared",
2693 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
2697 interrupt-names = "ipa",
2699 "ipa-clock-query",
2700 "ipa-setup-ready";
2703 clock-names = "core";
2708 interconnect-names = "memory",
2712 qcom,smem-states = <&ipa_smp2p_out 0>,
2714 qcom,smem-state-names = "ipa-clock-enabled-valid",
2715 "ipa-clock-enabled";
2721 compatible = "qcom,tcsr-mutex";
2723 #hwlock-cells = <1>;
2727 compatible = "qcom,sdm845-tcsr", "syscon";
2732 compatible = "qcom,sdm845-pinctrl";
2735 gpio-controller;
2736 #gpio-cells = <2>;
2737 interrupt-controller;
2738 #interrupt-cells = <2>;
2739 gpio-ranges = <&tlmm 0 0 151>;
2740 wakeup-parent = <&pdc_intc>;
2742 cci0_default: cci0-default-state {
2747 bias-pull-up;
2748 drive-strength = <2>; /* 2 mA */
2751 cci0_sleep: cci0-sleep-state {
2756 drive-strength = <2>; /* 2 mA */
2757 bias-pull-down;
2760 cci1_default: cci1-default-state {
2765 bias-pull-up;
2766 drive-strength = <2>; /* 2 mA */
2769 cci1_sleep: cci1-sleep-state {
2774 drive-strength = <2>; /* 2 mA */
2775 bias-pull-down;
2778 qspi_clk: qspi-clk-state {
2783 qspi_cs0: qspi-cs0-state {
2788 qspi_cs1: qspi-cs1-state {
2793 qspi_data0: qspi-data0-state {
2798 qspi_data1: qspi-data1-state {
2803 qspi_data23: qspi-data23-state {
2808 qup_i2c0_default: qup-i2c0-default-state {
2813 qup_i2c1_default: qup-i2c1-default-state {
2818 qup_i2c2_default: qup-i2c2-default-state {
2823 qup_i2c3_default: qup-i2c3-default-state {
2828 qup_i2c4_default: qup-i2c4-default-state {
2833 qup_i2c5_default: qup-i2c5-default-state {
2838 qup_i2c6_default: qup-i2c6-default-state {
2843 qup_i2c7_default: qup-i2c7-default-state {
2848 qup_i2c8_default: qup-i2c8-default-state {
2853 qup_i2c9_default: qup-i2c9-default-state {
2858 qup_i2c10_default: qup-i2c10-default-state {
2863 qup_i2c11_default: qup-i2c11-default-state {
2868 qup_i2c12_default: qup-i2c12-default-state {
2873 qup_i2c13_default: qup-i2c13-default-state {
2878 qup_i2c14_default: qup-i2c14-default-state {
2883 qup_i2c15_default: qup-i2c15-default-state {
2888 qup_spi0_default: qup-spi0-default-state {
2893 qup_spi1_default: qup-spi1-default-state {
2898 qup_spi2_default: qup-spi2-default-state {
2903 qup_spi3_default: qup-spi3-default-state {
2908 qup_spi4_default: qup-spi4-default-state {
2913 qup_spi5_default: qup-spi5-default-state {
2918 qup_spi6_default: qup-spi6-default-state {
2923 qup_spi7_default: qup-spi7-default-state {
2928 qup_spi8_default: qup-spi8-default-state {
2933 qup_spi9_default: qup-spi9-default-state {
2938 qup_spi10_default: qup-spi10-default-state {
2943 qup_spi11_default: qup-spi11-default-state {
2948 qup_spi12_default: qup-spi12-default-state {
2953 qup_spi13_default: qup-spi13-default-state {
2958 qup_spi14_default: qup-spi14-default-state {
2963 qup_spi15_default: qup-spi15-default-state {
2968 qup_uart0_default: qup-uart0-default-state {
2969 qup_uart0_tx: tx-pins {
2974 qup_uart0_rx: rx-pins {
2980 qup_uart1_default: qup-uart1-default-state {
2981 qup_uart1_tx: tx-pins {
2986 qup_uart1_rx: rx-pins {
2992 qup_uart2_default: qup-uart2-default-state {
2993 qup_uart2_tx: tx-pins {
2998 qup_uart2_rx: rx-pins {
3004 qup_uart3_default: qup-uart3-default-state {
3005 qup_uart3_tx: tx-pins {
3010 qup_uart3_rx: rx-pins {
3016 qup_uart3_4pin: qup-uart3-4pin-state {
3017 qup_uart3_4pin_cts: cts-pins {
3022 qup_uart3_4pin_rts_tx: rts-tx-pins {
3027 qup_uart3_4pin_rx: rx-pins {
3033 qup_uart4_default: qup-uart4-default-state {
3034 qup_uart4_tx: tx-pins {
3039 qup_uart4_rx: rx-pins {
3045 qup_uart5_default: qup-uart5-default-state {
3046 qup_uart5_tx: tx-pins {
3051 qup_uart5_rx: rx-pins {
3057 qup_uart6_default: qup-uart6-default-state {
3058 qup_uart6_tx: tx-pins {
3063 qup_uart6_rx: rx-pins {
3069 qup_uart6_4pin: qup-uart6-4pin-state {
3070 qup_uart6_4pin_cts: cts-pins {
3073 bias-pull-down;
3076 qup_uart6_4pin_rts_tx: rts-tx-pins {
3079 drive-strength = <2>;
3080 bias-disable;
3083 qup_uart6_4pin_rx: rx-pins {
3086 bias-pull-up;
3090 qup_uart7_default: qup-uart7-default-state {
3091 qup_uart7_tx: tx-pins {
3096 qup_uart7_rx: rx-pins {
3102 qup_uart8_default: qup-uart8-default-state {
3103 qup_uart8_tx: tx-pins {
3108 qup_uart8_rx: rx-pins {
3114 qup_uart9_default: qup-uart9-default-state {
3115 qup_uart9_tx: tx-pins {
3120 qup_uart9_rx: rx-pins {
3126 qup_uart10_default: qup-uart10-default-state {
3127 qup_uart10_tx: tx-pins {
3132 qup_uart10_rx: rx-pins {
3138 qup_uart11_default: qup-uart11-default-state {
3139 qup_uart11_tx: tx-pins {
3144 qup_uart11_rx: rx-pins {
3150 qup_uart12_default: qup-uart12-default-state {
3151 qup_uart12_tx: tx-pins {
3156 qup_uart12_rx: rx-pins {
3162 qup_uart13_default: qup-uart13-default-state {
3163 qup_uart13_tx: tx-pins {
3168 qup_uart13_rx: rx-pins {
3174 qup_uart14_default: qup-uart14-default-state {
3175 qup_uart14_tx: tx-pins {
3180 qup_uart14_rx: rx-pins {
3186 qup_uart15_default: qup-uart15-default-state {
3187 qup_uart15_tx: tx-pins {
3192 qup_uart15_rx: rx-pins {
3198 quat_mi2s_sleep: quat-mi2s-sleep-state {
3201 drive-strength = <2>;
3202 bias-pull-down;
3205 quat_mi2s_active: quat-mi2s-active-state {
3208 drive-strength = <8>;
3209 bias-disable;
3210 output-high;
3213 quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state {
3216 drive-strength = <2>;
3217 bias-pull-down;
3220 quat_mi2s_sd0_active: quat-mi2s-sd0-active-state {
3223 drive-strength = <8>;
3224 bias-disable;
3227 quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state {
3230 drive-strength = <2>;
3231 bias-pull-down;
3234 quat_mi2s_sd1_active: quat-mi2s-sd1-active-state {
3237 drive-strength = <8>;
3238 bias-disable;
3241 quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state {
3244 drive-strength = <2>;
3245 bias-pull-down;
3248 quat_mi2s_sd2_active: quat-mi2s-sd2-active-state {
3251 drive-strength = <8>;
3252 bias-disable;
3255 quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state {
3258 drive-strength = <2>;
3259 bias-pull-down;
3262 quat_mi2s_sd3_active: quat-mi2s-sd3-active-state {
3265 drive-strength = <8>;
3266 bias-disable;
3271 compatible = "qcom,sdm845-mss-pil";
3273 reg-names = "qdsp6", "rmb";
3275 interrupts-extended =
3282 interrupt-names = "wdog", "fatal", "ready",
3283 "handover", "stop-ack",
3284 "shutdown-ack";
3294 clock-names = "iface", "bus", "mem", "gpll0_mss",
3299 qcom,smem-states = <&modem_smp2p_out 0>;
3300 qcom,smem-state-names = "stop";
3304 reset-names = "mss_restart", "pdc_reset";
3306 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3308 power-domains = <&rpmhpd SDM845_CX>,
3311 power-domain-names = "cx", "mx", "mss";
3316 memory-region = <&mba_region>;
3320 memory-region = <&mpss_region>;
3324 memory-region = <&mdata_mem>;
3327 glink-edge {
3330 qcom,remote-pid = <1>;
3335 gpucc: clock-controller@5090000 {
3336 compatible = "qcom,sdm845-gpucc";
3338 #clock-cells = <1>;
3339 #reset-cells = <1>;
3340 #power-domain-cells = <1>;
3344 clock-names = "bi_tcxo",
3350 compatible = "qcom,sdm845-slpi-pas";
3353 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
3358 interrupt-names = "wdog", "fatal", "ready",
3359 "handover", "stop-ack";
3362 clock-names = "xo";
3366 power-domains = <&rpmhpd SDM845_CX>,
3368 power-domain-names = "lcx", "lmx";
3370 memory-region = <&slpi_mem>;
3372 qcom,smem-states = <&slpi_smp2p_out 0>;
3373 qcom,smem-state-names = "stop";
3377 glink-edge {
3380 qcom,remote-pid = <3>;
3385 qcom,glink-channels = "fastrpcglink-apps-dsp";
3387 qcom,non-secure-domain;
3390 memory-region = <&fastrpc_mem>;
3391 #address-cells = <1>;
3392 #size-cells = <0>;
3394 compute-cb@0 {
3395 compatible = "qcom,fastrpc-compute-cb";
3403 compatible = "arm,coresight-stm", "arm,primecell";
3406 reg-names = "stm-base", "stm-stimulus-base";
3409 clock-names = "apb_pclk";
3411 out-ports {
3414 remote-endpoint =
3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3426 clock-names = "apb_pclk";
3428 out-ports {
3431 remote-endpoint =
3437 in-ports {
3438 #address-cells = <1>;
3439 #size-cells = <0>;
3444 remote-endpoint = <&stm_out>;
3451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3455 clock-names = "apb_pclk";
3457 out-ports {
3460 remote-endpoint =
3466 in-ports {
3467 #address-cells = <1>;
3468 #size-cells = <0>;
3473 remote-endpoint =
3481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3485 clock-names = "apb_pclk";
3487 out-ports {
3490 remote-endpoint = <&etf_in>;
3495 in-ports {
3496 #address-cells = <1>;
3497 #size-cells = <0>;
3502 remote-endpoint =
3510 remote-endpoint =
3518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
3522 clock-names = "apb_pclk";
3524 out-ports {
3527 remote-endpoint = <&etr_in>;
3532 in-ports {
3535 remote-endpoint = <&etf_out>;
3542 compatible = "arm,coresight-tmc", "arm,primecell";
3546 clock-names = "apb_pclk";
3548 out-ports {
3551 remote-endpoint =
3557 in-ports {
3558 #address-cells = <1>;
3559 #size-cells = <0>;
3564 remote-endpoint =
3572 compatible = "arm,coresight-tmc", "arm,primecell";
3576 clock-names = "apb_pclk";
3577 arm,scatter-gather;
3579 in-ports {
3582 remote-endpoint =
3590 compatible = "arm,coresight-etm4x", "arm,primecell";
3596 clock-names = "apb_pclk";
3597 arm,coresight-loses-context-with-cpu;
3599 out-ports {
3602 remote-endpoint =
3610 compatible = "arm,coresight-etm4x", "arm,primecell";
3616 clock-names = "apb_pclk";
3617 arm,coresight-loses-context-with-cpu;
3619 out-ports {
3622 remote-endpoint =
3630 compatible = "arm,coresight-etm4x", "arm,primecell";
3636 clock-names = "apb_pclk";
3637 arm,coresight-loses-context-with-cpu;
3639 out-ports {
3642 remote-endpoint =
3650 compatible = "arm,coresight-etm4x", "arm,primecell";
3656 clock-names = "apb_pclk";
3657 arm,coresight-loses-context-with-cpu;
3659 out-ports {
3662 remote-endpoint =
3670 compatible = "arm,coresight-etm4x", "arm,primecell";
3676 clock-names = "apb_pclk";
3677 arm,coresight-loses-context-with-cpu;
3679 out-ports {
3682 remote-endpoint =
3690 compatible = "arm,coresight-etm4x", "arm,primecell";
3696 clock-names = "apb_pclk";
3697 arm,coresight-loses-context-with-cpu;
3699 out-ports {
3702 remote-endpoint =
3710 compatible = "arm,coresight-etm4x", "arm,primecell";
3716 clock-names = "apb_pclk";
3717 arm,coresight-loses-context-with-cpu;
3719 out-ports {
3722 remote-endpoint =
3730 compatible = "arm,coresight-etm4x", "arm,primecell";
3736 clock-names = "apb_pclk";
3737 arm,coresight-loses-context-with-cpu;
3739 out-ports {
3742 remote-endpoint =
3750 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3754 clock-names = "apb_pclk";
3756 out-ports {
3759 remote-endpoint =
3765 in-ports {
3766 #address-cells = <1>;
3767 #size-cells = <0>;
3772 remote-endpoint =
3780 remote-endpoint =
3788 remote-endpoint =
3796 remote-endpoint =
3804 remote-endpoint =
3812 remote-endpoint =
3820 remote-endpoint =
3828 remote-endpoint =
3836 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3840 clock-names = "apb_pclk";
3842 out-ports {
3845 remote-endpoint =
3851 in-ports {
3854 remote-endpoint =
3862 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
3867 interrupt-names = "hc_irq", "pwr_irq";
3872 clock-names = "iface", "core", "xo";
3874 power-domains = <&rpmhpd SDM845_CX>;
3875 operating-points-v2 = <&sdhc2_opp_table>;
3879 sdhc2_opp_table: opp-table {
3880 compatible = "operating-points-v2";
3882 opp-9600000 {
3883 opp-hz = /bits/ 64 <9600000>;
3884 required-opps = <&rpmhpd_opp_min_svs>;
3887 opp-19200000 {
3888 opp-hz = /bits/ 64 <19200000>;
3889 required-opps = <&rpmhpd_opp_low_svs>;
3892 opp-100000000 {
3893 opp-hz = /bits/ 64 <100000000>;
3894 required-opps = <&rpmhpd_opp_svs>;
3897 opp-201500000 {
3898 opp-hz = /bits/ 64 <201500000>;
3899 required-opps = <&rpmhpd_opp_svs_l1>;
3905 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
3908 #address-cells = <1>;
3909 #size-cells = <0>;
3913 clock-names = "iface", "core";
3914 power-domains = <&rpmhpd SDM845_CX>;
3915 operating-points-v2 = <&qspi_opp_table>;
3919 slim: slim-ngd@171c0000 {
3920 compatible = "qcom,slim-ngd-v2.1.0";
3925 dma-names = "rx", "tx";
3928 #address-cells = <1>;
3929 #size-cells = <0>;
3934 compatible = "qcom,sdm845-lmh";
3938 qcom,lmh-temp-arm-millicelsius = <65000>;
3939 qcom,lmh-temp-low-millicelsius = <94500>;
3940 qcom,lmh-temp-high-millicelsius = <95000>;
3941 interrupt-controller;
3942 #interrupt-cells = <1>;
3946 compatible = "qcom,sdm845-lmh";
3950 qcom,lmh-temp-arm-millicelsius = <65000>;
3951 qcom,lmh-temp-low-millicelsius = <94500>;
3952 qcom,lmh-temp-high-millicelsius = <95000>;
3953 interrupt-controller;
3954 #interrupt-cells = <1>;
3958 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3961 #phy-cells = <0>;
3965 clock-names = "cfg_ahb", "ref";
3969 nvmem-cells = <&qusb2p_hstx_trim>;
3973 compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
3976 #phy-cells = <0>;
3980 clock-names = "cfg_ahb", "ref";
3984 nvmem-cells = <&qusb2s_hstx_trim>;
3988 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
3993 #address-cells = <2>;
3994 #size-cells = <2>;
4001 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4005 reset-names = "phy", "common";
4007 usb_1_ssphy: usb3-phy@88e9200 {
4014 #clock-cells = <0>;
4015 #phy-cells = <0>;
4017 clock-names = "pipe0";
4018 clock-output-names = "usb3_phy_pipe_clk_src";
4021 dp_phy: dp-phy@88ea200 {
4027 #clock-cells = <1>;
4028 #phy-cells = <0>;
4033 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
4036 #address-cells = <2>;
4037 #size-cells = <2>;
4044 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
4048 reset-names = "phy", "common";
4055 #clock-cells = <0>;
4056 #phy-cells = <0>;
4058 clock-names = "pipe0";
4059 clock-output-names = "usb3_uni_phy_pipe_clk_src";
4064 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4067 #address-cells = <2>;
4068 #size-cells = <2>;
4070 dma-ranges;
4077 clock-names = "cfg_noc",
4083 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4085 assigned-clock-rates = <19200000>, <150000000>;
4091 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4094 power-domains = <&gcc USB30_PRIM_GDSC>;
4100 interconnect-names = "usb-ddr", "apps-usb";
4110 phy-names = "usb2-phy", "usb3-phy";
4115 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
4118 #address-cells = <2>;
4119 #size-cells = <2>;
4121 dma-ranges;
4128 clock-names = "cfg_noc",
4134 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
4136 assigned-clock-rates = <19200000>, <150000000>;
4142 interrupt-names = "hs_phy_irq", "ss_phy_irq",
4145 power-domains = <&gcc USB30_SEC_GDSC>;
4151 interconnect-names = "usb-ddr", "apps-usb";
4161 phy-names = "usb2-phy", "usb3-phy";
4165 venus: video-codec@aa00000 {
4166 compatible = "qcom,sdm845-venus-v2";
4169 power-domains = <&videocc VENUS_GDSC>,
4173 power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
4174 operating-points-v2 = <&venus_opp_table>;
4182 clock-names = "core", "iface", "bus",
4187 memory-region = <&venus_mem>;
4190 interconnect-names = "video-mem", "cpu-cfg";
4194 video-core0 {
4195 compatible = "venus-decoder";
4198 video-core1 {
4199 compatible = "venus-encoder";
4202 venus_opp_table: opp-table {
4203 compatible = "operating-points-v2";
4205 opp-100000000 {
4206 opp-hz = /bits/ 64 <100000000>;
4207 required-opps = <&rpmhpd_opp_min_svs>;
4210 opp-200000000 {
4211 opp-hz = /bits/ 64 <200000000>;
4212 required-opps = <&rpmhpd_opp_low_svs>;
4215 opp-320000000 {
4216 opp-hz = /bits/ 64 <320000000>;
4217 required-opps = <&rpmhpd_opp_svs>;
4220 opp-380000000 {
4221 opp-hz = /bits/ 64 <380000000>;
4222 required-opps = <&rpmhpd_opp_svs_l1>;
4225 opp-444000000 {
4226 opp-hz = /bits/ 64 <444000000>;
4227 required-opps = <&rpmhpd_opp_nom>;
4230 opp-533000097 {
4231 opp-hz = /bits/ 64 <533000097>;
4232 required-opps = <&rpmhpd_opp_turbo>;
4237 videocc: clock-controller@ab00000 {
4238 compatible = "qcom,sdm845-videocc";
4241 clock-names = "bi_tcxo";
4242 #clock-cells = <1>;
4243 #power-domain-cells = <1>;
4244 #reset-cells = <1>;
4248 compatible = "qcom,sdm845-camss";
4260 reg-names = "csid0",
4281 interrupt-names = "csid0",
4292 power-domains = <&clock_camcc IFE_0_GDSC>,
4332 clock-names = "camnoc_axi",
4377 #address-cells = <1>;
4378 #size-cells = <0>;
4399 compatible = "qcom,sdm845-cci", "qcom,msm8996-cci";
4400 #address-cells = <1>;
4401 #size-cells = <0>;
4405 power-domains = <&clock_camcc TITAN_TOP_GDSC>;
4413 clock-names = "camnoc_axi",
4420 assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
4422 assigned-clock-rates = <80000000>, <37500000>;
4424 pinctrl-names = "default", "sleep";
4425 pinctrl-0 = <&cci0_default &cci1_default>;
4426 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4430 cci_i2c0: i2c-bus@0 {
4432 clock-frequency = <1000000>;
4433 #address-cells = <1>;
4434 #size-cells = <0>;
4437 cci_i2c1: i2c-bus@1 {
4439 clock-frequency = <1000000>;
4440 #address-cells = <1>;
4441 #size-cells = <0>;
4445 clock_camcc: clock-controller@ad00000 {
4446 compatible = "qcom,sdm845-camcc";
4448 #clock-cells = <1>;
4449 #reset-cells = <1>;
4450 #power-domain-cells = <1>;
4452 clock-names = "bi_tcxo";
4455 mdss: display-subsystem@ae00000 {
4456 compatible = "qcom,sdm845-mdss";
4458 reg-names = "mdss";
4460 power-domains = <&dispcc MDSS_GDSC>;
4464 clock-names = "iface", "core";
4467 interrupt-controller;
4468 #interrupt-cells = <1>;
4472 interconnect-names = "mdp0-mem", "mdp1-mem";
4479 #address-cells = <2>;
4480 #size-cells = <2>;
4483 mdss_mdp: display-controller@ae01000 {
4484 compatible = "qcom,sdm845-dpu";
4487 reg-names = "mdp", "vbif";
4494 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
4496 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
4497 assigned-clock-rates = <19200000>;
4498 operating-points-v2 = <&mdp_opp_table>;
4499 power-domains = <&rpmhpd SDM845_CX>;
4501 interrupt-parent = <&mdss>;
4505 #address-cells = <1>;
4506 #size-cells = <0>;
4511 remote-endpoint = <&dp_in>;
4518 remote-endpoint = <&mdss_dsi0_in>;
4525 remote-endpoint = <&mdss_dsi1_in>;
4530 mdp_opp_table: opp-table {
4531 compatible = "operating-points-v2";
4533 opp-19200000 {
4534 opp-hz = /bits/ 64 <19200000>;
4535 required-opps = <&rpmhpd_opp_min_svs>;
4538 opp-171428571 {
4539 opp-hz = /bits/ 64 <171428571>;
4540 required-opps = <&rpmhpd_opp_low_svs>;
4543 opp-344000000 {
4544 opp-hz = /bits/ 64 <344000000>;
4545 required-opps = <&rpmhpd_opp_svs_l1>;
4548 opp-430000000 {
4549 opp-hz = /bits/ 64 <430000000>;
4550 required-opps = <&rpmhpd_opp_nom>;
4555 mdss_dp: displayport-controller@ae90000 {
4557 compatible = "qcom,sdm845-dp";
4565 interrupt-parent = <&mdss>;
4573 clock-names = "core_iface", "core_aux", "ctrl_link",
4575 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4577 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4579 phy-names = "dp";
4581 operating-points-v2 = <&dp_opp_table>;
4582 power-domains = <&rpmhpd SDM845_CX>;
4585 #address-cells = <1>;
4586 #size-cells = <0>;
4590 remote-endpoint = <&dpu_intf0_out>;
4600 dp_opp_table: opp-table {
4601 compatible = "operating-points-v2";
4603 opp-162000000 {
4604 opp-hz = /bits/ 64 <162000000>;
4605 required-opps = <&rpmhpd_opp_low_svs>;
4608 opp-270000000 {
4609 opp-hz = /bits/ 64 <270000000>;
4610 required-opps = <&rpmhpd_opp_svs>;
4613 opp-540000000 {
4614 opp-hz = /bits/ 64 <540000000>;
4615 required-opps = <&rpmhpd_opp_svs_l1>;
4618 opp-810000000 {
4619 opp-hz = /bits/ 64 <810000000>;
4620 required-opps = <&rpmhpd_opp_nom>;
4626 compatible = "qcom,sdm845-dsi-ctrl",
4627 "qcom,mdss-dsi-ctrl";
4629 reg-names = "dsi_ctrl";
4631 interrupt-parent = <&mdss>;
4640 clock-names = "byte",
4646 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
4647 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4649 operating-points-v2 = <&dsi_opp_table>;
4650 power-domains = <&rpmhpd SDM845_CX>;
4656 #address-cells = <1>;
4657 #size-cells = <0>;
4660 #address-cells = <1>;
4661 #size-cells = <0>;
4666 remote-endpoint = <&dpu_intf1_out>;
4679 compatible = "qcom,dsi-phy-10nm";
4683 reg-names = "dsi_phy",
4687 #clock-cells = <1>;
4688 #phy-cells = <0>;
4692 clock-names = "iface", "ref";
4698 compatible = "qcom,sdm845-dsi-ctrl",
4699 "qcom,mdss-dsi-ctrl";
4701 reg-names = "dsi_ctrl";
4703 interrupt-parent = <&mdss>;
4712 clock-names = "byte",
4718 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
4719 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4721 operating-points-v2 = <&dsi_opp_table>;
4722 power-domains = <&rpmhpd SDM845_CX>;
4728 #address-cells = <1>;
4729 #size-cells = <0>;
4732 #address-cells = <1>;
4733 #size-cells = <0>;
4738 remote-endpoint = <&dpu_intf2_out>;
4751 compatible = "qcom,dsi-phy-10nm";
4755 reg-names = "dsi_phy",
4759 #clock-cells = <1>;
4760 #phy-cells = <0>;
4764 clock-names = "iface", "ref";
4771 compatible = "qcom,adreno-630.2", "qcom,adreno";
4774 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
4785 operating-points-v2 = <&gpu_opp_table>;
4790 interconnect-names = "gfx-mem";
4794 gpu_opp_table: opp-table {
4795 compatible = "operating-points-v2";
4797 opp-710000000 {
4798 opp-hz = /bits/ 64 <710000000>;
4799 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4800 opp-peak-kBps = <7216000>;
4803 opp-675000000 {
4804 opp-hz = /bits/ 64 <675000000>;
4805 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4806 opp-peak-kBps = <7216000>;
4809 opp-596000000 {
4810 opp-hz = /bits/ 64 <596000000>;
4811 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4812 opp-peak-kBps = <6220000>;
4815 opp-520000000 {
4816 opp-hz = /bits/ 64 <520000000>;
4817 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4818 opp-peak-kBps = <6220000>;
4821 opp-414000000 {
4822 opp-hz = /bits/ 64 <414000000>;
4823 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4824 opp-peak-kBps = <4068000>;
4827 opp-342000000 {
4828 opp-hz = /bits/ 64 <342000000>;
4829 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4830 opp-peak-kBps = <2724000>;
4833 opp-257000000 {
4834 opp-hz = /bits/ 64 <257000000>;
4835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4836 opp-peak-kBps = <1648000>;
4842 compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
4844 #iommu-cells = <1>;
4845 #global-interrupts = <2>;
4858 clock-names = "bus", "iface";
4860 power-domains = <&gpucc GPU_CX_GDSC>;
4864 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4869 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4873 interrupt-names = "hfi", "gmu";
4879 clock-names = "gmu", "cxo", "axi", "memnoc";
4881 power-domains = <&gpucc GPU_CX_GDSC>,
4883 power-domain-names = "cx", "gx";
4887 operating-points-v2 = <&gmu_opp_table>;
4891 gmu_opp_table: opp-table {
4892 compatible = "operating-points-v2";
4894 opp-400000000 {
4895 opp-hz = /bits/ 64 <400000000>;
4896 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4899 opp-200000000 {
4900 opp-hz = /bits/ 64 <200000000>;
4901 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4906 dispcc: clock-controller@af00000 {
4907 compatible = "qcom,sdm845-dispcc";
4918 clock-names = "bi_tcxo",
4927 #clock-cells = <1>;
4928 #reset-cells = <1>;
4929 #power-domain-cells = <1>;
4932 pdc_intc: interrupt-controller@b220000 {
4933 compatible = "qcom,sdm845-pdc", "qcom,pdc";
4935 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4936 #interrupt-cells = <2>;
4937 interrupt-parent = <&intc>;
4938 interrupt-controller;
4941 pdc_reset: reset-controller@b2e0000 {
4942 compatible = "qcom,sdm845-pdc-global";
4944 #reset-cells = <1>;
4947 tsens0: thermal-sensor@c263000 {
4948 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4954 interrupt-names = "uplow", "critical";
4955 #thermal-sensor-cells = <1>;
4958 tsens1: thermal-sensor@c265000 {
4959 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
4965 interrupt-names = "uplow", "critical";
4966 #thermal-sensor-cells = <1>;
4969 aoss_reset: reset-controller@c2a0000 {
4970 compatible = "qcom,sdm845-aoss-cc";
4972 #reset-cells = <1>;
4975 aoss_qmp: power-management@c300000 {
4976 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
4981 #clock-cells = <0>;
4984 #cooling-cells = <2>;
4988 #cooling-cells = <2>;
4993 compatible = "qcom,sdm845-rpmh-stats";
4998 compatible = "qcom,spmi-pmic-arb";
5004 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
5005 interrupt-names = "periph_irq";
5009 #address-cells = <2>;
5010 #size-cells = <0>;
5011 interrupt-controller;
5012 #interrupt-cells = <4>;
5016 compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
5019 #address-cells = <1>;
5020 #size-cells = <1>;
5024 pil-reloc@94c {
5025 compatible = "qcom,pil-reloc-info";
5031 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
5033 #iommu-cells = <2>;
5034 #global-interrupts = <1>;
5102 lpasscc: clock-controller@17014000 {
5103 compatible = "qcom,sdm845-lpasscc";
5105 reg-names = "cc", "qdsp6ss";
5106 #clock-cells = <1>;
5111 compatible = "qcom,sdm845-gladiator-noc";
5113 #interconnect-cells = <2>;
5114 qcom,bcm-voters = <&apps_bcm_voter>;
5118 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
5125 compatible = "qcom,sdm845-apss-shared";
5127 #mbox-cells = <1>;
5132 compatible = "qcom,rpmh-rsc";
5136 reg-names = "drv-0", "drv-1", "drv-2";
5140 qcom,tcs-offset = <0xd00>;
5141 qcom,drv-id = <2>;
5142 qcom,tcs-config = <ACTIVE_TCS 2>,
5146 power-domains = <&CLUSTER_PD>;
5148 apps_bcm_voter: bcm-voter {
5149 compatible = "qcom,bcm-voter";
5152 rpmhcc: clock-controller {
5153 compatible = "qcom,sdm845-rpmh-clk";
5154 #clock-cells = <1>;
5155 clock-names = "xo";
5159 rpmhpd: power-controller {
5160 compatible = "qcom,sdm845-rpmhpd";
5161 #power-domain-cells = <1>;
5162 operating-points-v2 = <&rpmhpd_opp_table>;
5164 rpmhpd_opp_table: opp-table {
5165 compatible = "operating-points-v2";
5168 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5172 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
5176 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5180 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5184 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5188 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5196 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
5200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5204 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5210 intc: interrupt-controller@17a00000 {
5211 compatible = "arm,gic-v3";
5212 #address-cells = <2>;
5213 #size-cells = <2>;
5215 #interrupt-cells = <3>;
5216 interrupt-controller;
5221 msi-controller@17a40000 {
5222 compatible = "arm,gic-v3-its";
5223 msi-controller;
5224 #msi-cells = <1>;
5230 slimbam: dma-controller@17184000 {
5231 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
5232 qcom,controlled-remotely;
5234 num-channels = <31>;
5236 #dma-cells = <1>;
5238 qcom,num-ees = <2>;
5243 #address-cells = <1>;
5244 #size-cells = <1>;
5246 compatible = "arm,armv7-timer-mem";
5250 frame-number = <0>;
5258 frame-number = <1>;
5265 frame-number = <2>;
5272 frame-number = <3>;
5279 frame-number = <4>;
5286 frame-number = <5>;
5293 frame-number = <6>;
5301 compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
5305 clock-names = "xo", "alternate";
5307 #interconnect-cells = <1>;
5311 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
5313 reg-names = "freq-domain0", "freq-domain1";
5315 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5318 clock-names = "xo", "alternate";
5320 #freq-domain-cells = <1>;
5321 #clock-cells = <1>;
5325 compatible = "qcom,wcn3990-wifi";
5328 reg-names = "membase";
5329 memory-region = <&wlan_msa_mem>;
5330 clock-names = "cxo_ref_clk_pin";
5352 thermal-zones {
5353 cpu0-thermal {
5354 polling-delay-passive = <250>;
5355 polling-delay = <1000>;
5357 thermal-sensors = <&tsens0 1>;
5360 cpu0_alert0: trip-point0 {
5366 cpu0_alert1: trip-point1 {
5372 cpu0_crit: cpu-crit {
5380 cpu1-thermal {
5381 polling-delay-passive = <250>;
5382 polling-delay = <1000>;
5384 thermal-sensors = <&tsens0 2>;
5387 cpu1_alert0: trip-point0 {
5393 cpu1_alert1: trip-point1 {
5399 cpu1_crit: cpu-crit {
5407 cpu2-thermal {
5408 polling-delay-passive = <250>;
5409 polling-delay = <1000>;
5411 thermal-sensors = <&tsens0 3>;
5414 cpu2_alert0: trip-point0 {
5420 cpu2_alert1: trip-point1 {
5426 cpu2_crit: cpu-crit {
5434 cpu3-thermal {
5435 polling-delay-passive = <250>;
5436 polling-delay = <1000>;
5438 thermal-sensors = <&tsens0 4>;
5441 cpu3_alert0: trip-point0 {
5447 cpu3_alert1: trip-point1 {
5453 cpu3_crit: cpu-crit {
5461 cpu4-thermal {
5462 polling-delay-passive = <250>;
5463 polling-delay = <1000>;
5465 thermal-sensors = <&tsens0 7>;
5468 cpu4_alert0: trip-point0 {
5474 cpu4_alert1: trip-point1 {
5480 cpu4_crit: cpu-crit {
5488 cpu5-thermal {
5489 polling-delay-passive = <250>;
5490 polling-delay = <1000>;
5492 thermal-sensors = <&tsens0 8>;
5495 cpu5_alert0: trip-point0 {
5501 cpu5_alert1: trip-point1 {
5507 cpu5_crit: cpu-crit {
5515 cpu6-thermal {
5516 polling-delay-passive = <250>;
5517 polling-delay = <1000>;
5519 thermal-sensors = <&tsens0 9>;
5522 cpu6_alert0: trip-point0 {
5528 cpu6_alert1: trip-point1 {
5534 cpu6_crit: cpu-crit {
5542 cpu7-thermal {
5543 polling-delay-passive = <250>;
5544 polling-delay = <1000>;
5546 thermal-sensors = <&tsens0 10>;
5549 cpu7_alert0: trip-point0 {
5555 cpu7_alert1: trip-point1 {
5561 cpu7_crit: cpu-crit {
5569 aoss0-thermal {
5570 polling-delay-passive = <250>;
5571 polling-delay = <1000>;
5573 thermal-sensors = <&tsens0 0>;
5576 aoss0_alert0: trip-point0 {
5584 cluster0-thermal {
5585 polling-delay-passive = <250>;
5586 polling-delay = <1000>;
5588 thermal-sensors = <&tsens0 5>;
5591 cluster0_alert0: trip-point0 {
5604 cluster1-thermal {
5605 polling-delay-passive = <250>;
5606 polling-delay = <1000>;
5608 thermal-sensors = <&tsens0 6>;
5611 cluster1_alert0: trip-point0 {
5624 gpu-top-thermal {
5625 polling-delay-passive = <250>;
5626 polling-delay = <1000>;
5628 thermal-sensors = <&tsens0 11>;
5631 gpu1_alert0: trip-point0 {
5639 gpu-bottom-thermal {
5640 polling-delay-passive = <250>;
5641 polling-delay = <1000>;
5643 thermal-sensors = <&tsens0 12>;
5646 gpu2_alert0: trip-point0 {
5654 aoss1-thermal {
5655 polling-delay-passive = <250>;
5656 polling-delay = <1000>;
5658 thermal-sensors = <&tsens1 0>;
5661 aoss1_alert0: trip-point0 {
5669 q6-modem-thermal {
5670 polling-delay-passive = <250>;
5671 polling-delay = <1000>;
5673 thermal-sensors = <&tsens1 1>;
5676 q6_modem_alert0: trip-point0 {
5684 mem-thermal {
5685 polling-delay-passive = <250>;
5686 polling-delay = <1000>;
5688 thermal-sensors = <&tsens1 2>;
5691 mem_alert0: trip-point0 {
5699 wlan-thermal {
5700 polling-delay-passive = <250>;
5701 polling-delay = <1000>;
5703 thermal-sensors = <&tsens1 3>;
5706 wlan_alert0: trip-point0 {
5714 q6-hvx-thermal {
5715 polling-delay-passive = <250>;
5716 polling-delay = <1000>;
5718 thermal-sensors = <&tsens1 4>;
5721 q6_hvx_alert0: trip-point0 {
5729 camera-thermal {
5730 polling-delay-passive = <250>;
5731 polling-delay = <1000>;
5733 thermal-sensors = <&tsens1 5>;
5736 camera_alert0: trip-point0 {
5744 video-thermal {
5745 polling-delay-passive = <250>;
5746 polling-delay = <1000>;
5748 thermal-sensors = <&tsens1 6>;
5751 video_alert0: trip-point0 {
5759 modem-thermal {
5760 polling-delay-passive = <250>;
5761 polling-delay = <1000>;
5763 thermal-sensors = <&tsens1 7>;
5766 modem_alert0: trip-point0 {
5776 compatible = "arm,armv8-timer";