Lines Matching +full:0 +full:x04180000
76 #clock-cells = <0>;
83 #clock-cells = <0>;
90 #size-cells = <0>;
92 CPU0: cpu@0 {
95 reg = <0x0 0x0>;
96 clocks = <&cpufreq_hw 0>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x100>;
125 clocks = <&cpufreq_hw 0>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
148 reg = <0x0 0x200>;
149 clocks = <&cpufreq_hw 0>;
153 qcom,freq-domain = <&cpufreq_hw 0>;
172 reg = <0x0 0x300>;
173 clocks = <&cpufreq_hw 0>;
177 qcom,freq-domain = <&cpufreq_hw 0>;
196 reg = <0x0 0x400>;
220 reg = <0x0 0x500>;
244 reg = <0x0 0x600>;
268 reg = <0x0 0x700>;
328 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
331 arm,psci-suspend-param = <0x40000004>;
338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
341 arm,psci-suspend-param = <0x40000004>;
350 CLUSTER_SLEEP_0: cluster-sleep-0 {
352 arm,psci-suspend-param = <0x4100c244>;
369 reg = <0 0x80000000 0 0>;
719 #power-domain-cells = <0>;
725 #power-domain-cells = <0>;
731 #power-domain-cells = <0>;
737 #power-domain-cells = <0>;
743 #power-domain-cells = <0>;
749 #power-domain-cells = <0>;
755 #power-domain-cells = <0>;
761 #power-domain-cells = <0>;
767 #power-domain-cells = <0>;
778 reg = <0 0x85700000 0 0x600000>;
783 reg = <0 0x85e00000 0 0x100000>;
788 reg = <0 0x85fc0000 0 0x20000>;
794 reg = <0x0 0x85fe0000 0 0x20000>;
800 reg = <0x0 0x86000000 0 0x200000>;
806 reg = <0 0x86200000 0 0x2d00000>;
812 reg = <0 0x88f00000 0 0x200000>;
820 reg = <0 0x8ab00000 0 0x1400000>;
825 reg = <0 0x8bf00000 0 0x500000>;
830 reg = <0 0x8c400000 0 0x10000>;
835 reg = <0 0x8c410000 0 0x5000>;
840 reg = <0 0x8c415000 0 0x2000>;
845 reg = <0 0x8c500000 0 0x1a00000>;
850 reg = <0 0x8df00000 0 0x100000>;
855 reg = <0 0x8e000000 0 0x7800000>;
860 reg = <0 0x95800000 0 0x500000>;
865 reg = <0 0x95d00000 0 0x800000>;
870 reg = <0 0x96500000 0 0x200000>;
875 reg = <0 0x96700000 0 0x1400000>;
880 reg = <0 0x97b00000 0 0x100000>;
885 alloc-ranges = <0 0xa0000000 0 0x20000000>;
886 size = <0 0x4000>;
892 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
893 alignment = <0x0 0x400000>;
894 size = <0x0 0x1000000>;
903 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
917 qcom,smem-states = <&adsp_smp2p_out 0>;
933 #size-cells = <0>;
949 #size-cells = <0>;
961 #size-cells = <0>;
963 iommus = <&apps_smmu 0x1821 0x0>;
973 #sound-dai-cells = <0>;
984 #size-cells = <0>;
989 iommus = <&apps_smmu 0x1823 0x0>;
995 iommus = <&apps_smmu 0x1824 0x0>;
1005 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1019 qcom,smem-states = <&cdsp_smp2p_out 0>;
1035 #size-cells = <0>;
1040 iommus = <&apps_smmu 0x1401 0x30>;
1046 iommus = <&apps_smmu 0x1402 0x30>;
1052 iommus = <&apps_smmu 0x1403 0x30>;
1058 iommus = <&apps_smmu 0x1404 0x30>;
1064 iommus = <&apps_smmu 0x1405 0x30>;
1070 iommus = <&apps_smmu 0x1406 0x30>;
1076 iommus = <&apps_smmu 0x1407 0x30>;
1082 iommus = <&apps_smmu 0x1408 0x30>;
1096 qcom,local-pid = <0>;
1120 qcom,local-pid = <0>;
1141 qcom,local-pid = <0>;
1172 qcom,local-pid = <0>;
1187 soc: soc@0 {
1190 ranges = <0 0 0 0 0x10 0>;
1191 dma-ranges = <0 0 0 0 0x10 0>;
1196 reg = <0 0x00100000 0 0x1f0000>;
1215 reg = <0 0x00784000 0 0x8ff>;
1220 reg = <0x1eb 0x1>;
1225 reg = <0x1eb 0x2>;
1232 reg = <0 0x00793000 0 0x1000>;
1240 reg = <0 0x00800000 0 0x60000>;
1255 dma-channel-mask = <0xfa>;
1256 iommus = <&apps_smmu 0x0016 0x0>;
1262 reg = <0 0x008c0000 0 0x6000>;
1266 iommus = <&apps_smmu 0x3 0x0>;
1270 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
1276 reg = <0 0x00880000 0 0x4000>;
1280 pinctrl-0 = <&qup_i2c0_default>;
1283 #size-cells = <0>;
1286 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1287 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1288 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1290 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1291 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1298 reg = <0 0x00880000 0 0x4000>;
1302 pinctrl-0 = <&qup_spi0_default>;
1305 #size-cells = <0>;
1306 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1307 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1309 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1310 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1317 reg = <0 0x00880000 0 0x4000>;
1321 pinctrl-0 = <&qup_uart0_default>;
1325 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1326 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1333 reg = <0 0x00884000 0 0x4000>;
1337 pinctrl-0 = <&qup_i2c1_default>;
1340 #size-cells = <0>;
1343 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1344 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1345 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1347 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1355 reg = <0 0x00884000 0 0x4000>;
1359 pinctrl-0 = <&qup_spi1_default>;
1362 #size-cells = <0>;
1363 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1364 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1366 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1374 reg = <0 0x00884000 0 0x4000>;
1378 pinctrl-0 = <&qup_uart1_default>;
1382 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1383 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1390 reg = <0 0x00888000 0 0x4000>;
1394 pinctrl-0 = <&qup_i2c2_default>;
1397 #size-cells = <0>;
1400 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1401 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1402 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1412 reg = <0 0x00888000 0 0x4000>;
1416 pinctrl-0 = <&qup_spi2_default>;
1419 #size-cells = <0>;
1420 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1421 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1423 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1431 reg = <0 0x00888000 0 0x4000>;
1435 pinctrl-0 = <&qup_uart2_default>;
1439 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1440 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1447 reg = <0 0x0088c000 0 0x4000>;
1451 pinctrl-0 = <&qup_i2c3_default>;
1454 #size-cells = <0>;
1457 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1458 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1459 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1469 reg = <0 0x0088c000 0 0x4000>;
1473 pinctrl-0 = <&qup_spi3_default>;
1476 #size-cells = <0>;
1477 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1478 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1480 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1488 reg = <0 0x0088c000 0 0x4000>;
1492 pinctrl-0 = <&qup_uart3_default>;
1496 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1497 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1504 reg = <0 0x00890000 0 0x4000>;
1508 pinctrl-0 = <&qup_i2c4_default>;
1511 #size-cells = <0>;
1514 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1515 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1516 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1526 reg = <0 0x00890000 0 0x4000>;
1530 pinctrl-0 = <&qup_spi4_default>;
1533 #size-cells = <0>;
1534 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1535 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1537 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1545 reg = <0 0x00890000 0 0x4000>;
1549 pinctrl-0 = <&qup_uart4_default>;
1553 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1554 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1561 reg = <0 0x00894000 0 0x4000>;
1565 pinctrl-0 = <&qup_i2c5_default>;
1568 #size-cells = <0>;
1571 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1572 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1573 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1575 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1583 reg = <0 0x00894000 0 0x4000>;
1587 pinctrl-0 = <&qup_spi5_default>;
1590 #size-cells = <0>;
1591 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1592 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1594 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1602 reg = <0 0x00894000 0 0x4000>;
1606 pinctrl-0 = <&qup_uart5_default>;
1610 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1611 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1618 reg = <0 0x00898000 0 0x4000>;
1622 pinctrl-0 = <&qup_i2c6_default>;
1625 #size-cells = <0>;
1628 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1629 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
1630 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
1632 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1640 reg = <0 0x00898000 0 0x4000>;
1644 pinctrl-0 = <&qup_spi6_default>;
1647 #size-cells = <0>;
1648 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1649 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1651 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1659 reg = <0 0x00898000 0 0x4000>;
1663 pinctrl-0 = <&qup_uart6_default>;
1667 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1668 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1675 reg = <0 0x0089c000 0 0x4000>;
1679 pinctrl-0 = <&qup_i2c7_default>;
1682 #size-cells = <0>;
1690 reg = <0 0x0089c000 0 0x4000>;
1694 pinctrl-0 = <&qup_spi7_default>;
1697 #size-cells = <0>;
1698 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1699 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1701 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1709 reg = <0 0x0089c000 0 0x4000>;
1713 pinctrl-0 = <&qup_uart7_default>;
1717 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
1718 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
1727 reg = <0 0x00a00000 0 0x60000>;
1742 dma-channel-mask = <0xfa>;
1743 iommus = <&apps_smmu 0x06d6 0x0>;
1749 reg = <0 0x00ac0000 0 0x6000>;
1753 iommus = <&apps_smmu 0x6c3 0x0>;
1757 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
1763 reg = <0 0x00a80000 0 0x4000>;
1767 pinctrl-0 = <&qup_i2c8_default>;
1770 #size-cells = <0>;
1773 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1774 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1775 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1777 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1778 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1785 reg = <0 0x00a80000 0 0x4000>;
1789 pinctrl-0 = <&qup_spi8_default>;
1792 #size-cells = <0>;
1793 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1794 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1797 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1804 reg = <0 0x00a80000 0 0x4000>;
1808 pinctrl-0 = <&qup_uart8_default>;
1812 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1813 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1820 reg = <0 0x00a84000 0 0x4000>;
1824 pinctrl-0 = <&qup_i2c9_default>;
1827 #size-cells = <0>;
1830 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1831 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1832 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1834 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1842 reg = <0 0x00a84000 0 0x4000>;
1846 pinctrl-0 = <&qup_spi9_default>;
1849 #size-cells = <0>;
1850 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1851 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1861 reg = <0 0x00a84000 0 0x4000>;
1865 pinctrl-0 = <&qup_uart9_default>;
1869 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1870 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1877 reg = <0 0x00a88000 0 0x4000>;
1881 pinctrl-0 = <&qup_i2c10_default>;
1884 #size-cells = <0>;
1887 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1888 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1889 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1891 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1899 reg = <0 0x00a88000 0 0x4000>;
1903 pinctrl-0 = <&qup_spi10_default>;
1906 #size-cells = <0>;
1907 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1908 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1910 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1918 reg = <0 0x00a88000 0 0x4000>;
1922 pinctrl-0 = <&qup_uart10_default>;
1926 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1927 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1934 reg = <0 0x00a8c000 0 0x4000>;
1938 pinctrl-0 = <&qup_i2c11_default>;
1941 #size-cells = <0>;
1944 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1945 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
1946 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
1948 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1956 reg = <0 0x00a8c000 0 0x4000>;
1960 pinctrl-0 = <&qup_spi11_default>;
1963 #size-cells = <0>;
1964 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1965 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1967 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1975 reg = <0 0x00a8c000 0 0x4000>;
1979 pinctrl-0 = <&qup_uart11_default>;
1983 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
1984 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
1991 reg = <0 0x00a90000 0 0x4000>;
1995 pinctrl-0 = <&qup_i2c12_default>;
1998 #size-cells = <0>;
2001 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2002 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2003 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2005 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
2013 reg = <0 0x00a90000 0 0x4000>;
2017 pinctrl-0 = <&qup_spi12_default>;
2020 #size-cells = <0>;
2021 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2022 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2024 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2032 reg = <0 0x00a90000 0 0x4000>;
2036 pinctrl-0 = <&qup_uart12_default>;
2040 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2041 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2048 reg = <0 0x00a94000 0 0x4000>;
2052 pinctrl-0 = <&qup_i2c13_default>;
2055 #size-cells = <0>;
2058 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2059 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2060 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2062 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2070 reg = <0 0x00a94000 0 0x4000>;
2074 pinctrl-0 = <&qup_spi13_default>;
2077 #size-cells = <0>;
2078 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2079 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2081 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2089 reg = <0 0x00a94000 0 0x4000>;
2093 pinctrl-0 = <&qup_uart13_default>;
2097 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2098 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2105 reg = <0 0x00a98000 0 0x4000>;
2109 pinctrl-0 = <&qup_i2c14_default>;
2112 #size-cells = <0>;
2115 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2116 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2117 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2119 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
2127 reg = <0 0x00a98000 0 0x4000>;
2131 pinctrl-0 = <&qup_spi14_default>;
2134 #size-cells = <0>;
2135 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2136 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2138 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2146 reg = <0 0x00a98000 0 0x4000>;
2150 pinctrl-0 = <&qup_uart14_default>;
2154 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2155 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2162 reg = <0 0x00a9c000 0 0x4000>;
2166 pinctrl-0 = <&qup_i2c15_default>;
2169 #size-cells = <0>;
2173 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2174 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
2175 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
2177 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2184 reg = <0 0x00a9c000 0 0x4000>;
2188 pinctrl-0 = <&qup_spi15_default>;
2191 #size-cells = <0>;
2192 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2193 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2195 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2203 reg = <0 0x00a9c000 0 0x4000>;
2207 pinctrl-0 = <&qup_uart15_default>;
2211 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
2212 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
2220 reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>,
2221 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
2222 <0 0x01300000 0 0x50000>;
2230 reg = <0x0 0x010a2000 0x0 0x1000>,
2231 <0x0 0x010ae000 0x0 0x2000>;
2236 reg = <0 0x0114a000 0 0x1000>;
2253 opp-0 {
2273 reg = <0 0x01436400 0 0x600>;
2290 opp-0 {
2310 reg = <0 0x01c00000 0 0x2000>,
2311 <0 0x60000000 0 0xf1d>,
2312 <0 0x60000f20 0 0xa8>,
2313 <0 0x60100000 0 0x100000>,
2314 <0 0x01c07000 0 0x1000>;
2317 linux,pci-domain = <0>;
2318 bus-range = <0x00 0xff>;
2324 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2325 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
2330 interrupt-map-mask = <0 0 0 0x7>;
2331 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2332 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2333 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2334 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2351 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
2352 <0x100 &apps_smmu 0x1c11 0x1>,
2353 <0x200 &apps_smmu 0x1c12 0x1>,
2354 <0x300 &apps_smmu 0x1c13 0x1>,
2355 <0x400 &apps_smmu 0x1c14 0x1>,
2356 <0x500 &apps_smmu 0x1c15 0x1>,
2357 <0x600 &apps_smmu 0x1c16 0x1>,
2358 <0x700 &apps_smmu 0x1c17 0x1>,
2359 <0x800 &apps_smmu 0x1c18 0x1>,
2360 <0x900 &apps_smmu 0x1c19 0x1>,
2361 <0xa00 &apps_smmu 0x1c1a 0x1>,
2362 <0xb00 &apps_smmu 0x1c1b 0x1>,
2363 <0xc00 &apps_smmu 0x1c1c 0x1>,
2364 <0xd00 &apps_smmu 0x1c1d 0x1>,
2365 <0xe00 &apps_smmu 0x1c1e 0x1>,
2366 <0xf00 &apps_smmu 0x1c1f 0x1>;
2381 reg = <0 0x01c06000 0 0x18c>;
2400 reg = <0 0x01c06200 0 0x128>,
2401 <0 0x01c06400 0 0x1fc>,
2402 <0 0x01c06800 0 0x218>,
2403 <0 0x01c06600 0 0x70>;
2407 #clock-cells = <0>;
2408 #phy-cells = <0>;
2415 reg = <0 0x01c08000 0 0x2000>,
2416 <0 0x40000000 0 0xf1d>,
2417 <0 0x40000f20 0 0xa8>,
2418 <0 0x40100000 0 0x100000>,
2419 <0 0x01c0c000 0 0x1000>;
2423 bus-range = <0x00 0xff>;
2429 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2430 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2435 interrupt-map-mask = <0 0 0 0x7>;
2436 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2437 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2438 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2439 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2461 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2462 <0x100 &apps_smmu 0x1c01 0x1>,
2463 <0x200 &apps_smmu 0x1c02 0x1>,
2464 <0x300 &apps_smmu 0x1c03 0x1>,
2465 <0x400 &apps_smmu 0x1c04 0x1>,
2466 <0x500 &apps_smmu 0x1c05 0x1>,
2467 <0x600 &apps_smmu 0x1c06 0x1>,
2468 <0x700 &apps_smmu 0x1c07 0x1>,
2469 <0x800 &apps_smmu 0x1c08 0x1>,
2470 <0x900 &apps_smmu 0x1c09 0x1>,
2471 <0xa00 &apps_smmu 0x1c0a 0x1>,
2472 <0xb00 &apps_smmu 0x1c0b 0x1>,
2473 <0xc00 &apps_smmu 0x1c0c 0x1>,
2474 <0xd00 &apps_smmu 0x1c0d 0x1>,
2475 <0xe00 &apps_smmu 0x1c0e 0x1>,
2476 <0xf00 &apps_smmu 0x1c0f 0x1>;
2491 reg = <0 0x01c0a000 0 0x800>;
2510 reg = <0 0x01c0a800 0 0x800>,
2511 <0 0x01c0a800 0 0x800>,
2512 <0 0x01c0b800 0 0x400>;
2516 #clock-cells = <0>;
2517 #phy-cells = <0>;
2524 reg = <0 0x01380000 0 0x27200>;
2531 reg = <0 0x014e0000 0 0x400>;
2538 reg = <0 0x01500000 0 0x5080>;
2545 reg = <0 0x01620000 0 0x18080>;
2552 reg = <0 0x016e0000 0 0x15080>;
2559 reg = <0 0x01700000 0 0x1f300>;
2566 reg = <0 0x01740000 0 0x1c100>;
2574 reg = <0 0x01d84000 0 0x2500>,
2575 <0 0x01d90000 0 0x8000>;
2586 iommus = <&apps_smmu 0x100 0xf>;
2610 <0 0>,
2611 <0 0>,
2613 <0 0>,
2614 <0 0>,
2615 <0 0>,
2616 <0 0>,
2619 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>,
2620 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2628 reg = <0 0x01d87000 0 0x18c>;
2637 resets = <&ufs_mem_hc 0>;
2642 reg = <0 0x01d87400 0 0x108>,
2643 <0 0x01d87600 0 0x1e0>,
2644 <0 0x01d87c00 0 0x1dc>,
2645 <0 0x01d87800 0 0x108>,
2646 <0 0x01d87a00 0 0x1e0>;
2647 #phy-cells = <0>;
2653 reg = <0 0x01dc4000 0 0x24000>;
2658 qcom,ee = <0>;
2660 iommus = <&apps_smmu 0x704 0x1>,
2661 <&apps_smmu 0x706 0x1>,
2662 <&apps_smmu 0x714 0x1>,
2663 <&apps_smmu 0x716 0x1>;
2668 reg = <0 0x01dfa000 0 0x6000>;
2675 iommus = <&apps_smmu 0x704 0x1>,
2676 <&apps_smmu 0x706 0x1>,
2677 <&apps_smmu 0x714 0x1>,
2678 <&apps_smmu 0x716 0x1>;
2684 iommus = <&apps_smmu 0x720 0x0>,
2685 <&apps_smmu 0x722 0x0>;
2686 reg = <0 0x01e40000 0 0x7000>,
2687 <0 0x01e47000 0 0x2000>,
2688 <0 0x01e04000 0 0x2c000>;
2695 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2705 interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
2706 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
2707 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2712 qcom,smem-states = <&ipa_smp2p_out 0>,
2722 reg = <0 0x01f40000 0 0x20000>;
2728 reg = <0 0x01f60000 0 0x20000>;
2733 reg = <0 0x03400000 0 0xc00000>;
2739 gpio-ranges = <&tlmm 0 0 151>;
3272 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
3277 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3299 qcom,smem-states = <&modem_smp2p_out 0>;
3306 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
3337 reg = <0 0x05090000 0 0x9000>;
3351 reg = <0 0x5c00000 0 0x4000>;
3354 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3372 qcom,smem-states = <&slpi_smp2p_out 0>;
3392 #size-cells = <0>;
3394 compute-cb@0 {
3396 reg = <0>;
3404 reg = <0 0x06002000 0 0x1000>,
3405 <0 0x16280000 0 0x180000>;
3423 reg = <0 0x06041000 0 0x1000>;
3439 #size-cells = <0>;
3452 reg = <0 0x06043000 0 0x1000>;
3468 #size-cells = <0>;
3482 reg = <0 0x06045000 0 0x1000>;
3497 #size-cells = <0>;
3499 port@0 {
3500 reg = <0>;
3519 reg = <0 0x06046000 0 0x1000>;
3543 reg = <0 0x06047000 0 0x1000>;
3559 #size-cells = <0>;
3573 reg = <0 0x06048000 0 0x1000>;
3591 reg = <0 0x07040000 0 0x1000>;
3611 reg = <0 0x07140000 0 0x1000>;
3631 reg = <0 0x07240000 0 0x1000>;
3651 reg = <0 0x07340000 0 0x1000>;
3671 reg = <0 0x07440000 0 0x1000>;
3691 reg = <0 0x07540000 0 0x1000>;
3711 reg = <0 0x07640000 0 0x1000>;
3731 reg = <0 0x07740000 0 0x1000>;
3751 reg = <0 0x07800000 0 0x1000>;
3767 #size-cells = <0>;
3769 port@0 {
3770 reg = <0>;
3837 reg = <0 0x07810000 0 0x1000>;
3863 reg = <0 0x08804000 0 0x1000>;
3873 iommus = <&apps_smmu 0xa0 0xf>;
3906 reg = <0 0x088df000 0 0x600>;
3907 iommus = <&apps_smmu 0x160 0x0>;
3909 #size-cells = <0>;
3921 reg = <0 0x171c0000 0 0x2c000>;
3927 iommus = <&apps_smmu 0x1806 0x0>;
3929 #size-cells = <0>;
3935 reg = <0 0x17d70800 0 0x400>;
3947 reg = <0 0x17d78800 0 0x400>;
3959 reg = <0 0x088e2000 0 0x400>;
3961 #phy-cells = <0>;
3974 reg = <0 0x088e3000 0 0x400>;
3976 #phy-cells = <0>;
3989 reg = <0 0x088e9000 0 0x18c>,
3990 <0 0x088e8000 0 0x38>,
3991 <0 0x088ea000 0 0x40>;
4008 reg = <0 0x088e9200 0 0x128>,
4009 <0 0x088e9400 0 0x200>,
4010 <0 0x088e9c00 0 0x218>,
4011 <0 0x088e9600 0 0x128>,
4012 <0 0x088e9800 0 0x200>,
4013 <0 0x088e9a00 0 0x100>;
4014 #clock-cells = <0>;
4015 #phy-cells = <0>;
4022 reg = <0 0x088ea200 0 0x200>,
4023 <0 0x088ea400 0 0x200>,
4024 <0 0x088eaa00 0 0x200>,
4025 <0 0x088ea600 0 0x200>,
4026 <0 0x088ea800 0 0x200>;
4028 #phy-cells = <0>;
4034 reg = <0 0x088eb000 0 0x18c>;
4051 reg = <0 0x088eb200 0 0x128>,
4052 <0 0x088eb400 0 0x1fc>,
4053 <0 0x088eb800 0 0x218>,
4054 <0 0x088eb600 0 0x70>;
4055 #clock-cells = <0>;
4056 #phy-cells = <0>;
4065 reg = <0 0x0a6f8800 0 0x400>;
4098 interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
4099 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4104 reg = <0 0x0a600000 0 0xcd00>;
4106 iommus = <&apps_smmu 0x740 0>;
4116 reg = <0 0x0a8f8800 0 0x400>;
4149 interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
4150 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
4155 reg = <0 0x0a800000 0 0xcd00>;
4157 iommus = <&apps_smmu 0x760 0>;
4167 reg = <0 0x0aa00000 0 0xff000>;
4185 iommus = <&apps_smmu 0x10a0 0x8>,
4186 <&apps_smmu 0x10b0 0x0>;
4188 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
4189 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
4239 reg = <0 0x0ab00000 0 0x10000>;
4250 reg = <0 0x0acb3000 0 0x1000>,
4251 <0 0x0acba000 0 0x1000>,
4252 <0 0x0acc8000 0 0x1000>,
4253 <0 0x0ac65000 0 0x1000>,
4254 <0 0x0ac66000 0 0x1000>,
4255 <0 0x0ac67000 0 0x1000>,
4256 <0 0x0ac68000 0 0x1000>,
4257 <0 0x0acaf000 0 0x4000>,
4258 <0 0x0acb6000 0 0x4000>,
4259 <0 0x0acc4000 0 0x4000>;
4369 iommus = <&apps_smmu 0x0808 0x0>,
4370 <&apps_smmu 0x0810 0x8>,
4371 <&apps_smmu 0x0c08 0x0>,
4372 <&apps_smmu 0x0c10 0x8>;
4378 #size-cells = <0>;
4380 port@0 {
4381 reg = <0>;
4401 #size-cells = <0>;
4403 reg = <0 0x0ac4a000 0 0x4000>;
4425 pinctrl-0 = <&cci0_default &cci1_default>;
4430 cci_i2c0: i2c-bus@0 {
4431 reg = <0>;
4434 #size-cells = <0>;
4441 #size-cells = <0>;
4447 reg = <0 0x0ad00000 0 0x10000>;
4457 reg = <0 0x0ae00000 0 0x1000>;
4470 interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
4471 <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
4474 iommus = <&apps_smmu 0x880 0x8>,
4475 <&apps_smmu 0xc80 0x8>;
4485 reg = <0 0x0ae01000 0 0x8f000>,
4486 <0 0x0aeb0000 0 0x2008>;
4502 interrupts = <0>;
4506 #size-cells = <0>;
4508 port@0 {
4509 reg = <0>;
4559 reg = <0 0x0ae90000 0 0x200>,
4560 <0 0x0ae90200 0 0x200>,
4561 <0 0x0ae90400 0 0x600>,
4562 <0 0x0ae90a00 0 0x600>,
4563 <0 0x0ae91000 0 0x600>;
4577 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4586 #size-cells = <0>;
4587 port@0 {
4588 reg = <0>;
4628 reg = <0 0x0ae94000 0 0x400>;
4647 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4657 #size-cells = <0>;
4661 #size-cells = <0>;
4663 port@0 {
4664 reg = <0>;
4680 reg = <0 0x0ae94400 0 0x200>,
4681 <0 0x0ae94600 0 0x280>,
4682 <0 0x0ae94a00 0 0x1e0>;
4688 #phy-cells = <0>;
4700 reg = <0 0x0ae96000 0 0x400>;
4719 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4729 #size-cells = <0>;
4733 #size-cells = <0>;
4735 port@0 {
4736 reg = <0>;
4752 reg = <0 0x0ae96400 0 0x200>,
4753 <0 0x0ae96600 0 0x280>,
4754 <0 0x0ae96a00 0 0x10e>;
4760 #phy-cells = <0>;
4773 reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>;
4783 iommus = <&adreno_smmu 0>;
4789 interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
4843 reg = <0 0x05040000 0 0x10000>;
4866 reg = <0 0x0506a000 0 0x30000>,
4867 <0 0x0b280000 0 0x10000>,
4868 <0 0x0b480000 0 0x10000>;
4908 reg = <0 0x0af00000 0 0x10000>;
4912 <&mdss_dsi0_phy 0>,
4914 <&mdss_dsi1_phy 0>,
4916 <&dp_phy 0>,
4934 reg = <0 0x0b220000 0 0x30000>;
4935 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
4943 reg = <0 0x0b2e0000 0 0x20000>;
4949 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4950 <0 0x0c222000 0 0x1ff>; /* SROT */
4960 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4961 <0 0x0c223000 0 0x1ff>; /* SROT */
4971 reg = <0 0x0c2a0000 0 0x31000>;
4977 reg = <0 0x0c300000 0 0x400>;
4979 mboxes = <&apss_shared 0>;
4981 #clock-cells = <0>;
4994 reg = <0 0x0c3f0000 0 0x400>;
4999 reg = <0 0x0c440000 0 0x1100>,
5000 <0 0x0c600000 0 0x2000000>,
5001 <0 0x0e600000 0 0x100000>,
5002 <0 0x0e700000 0 0xa0000>,
5003 <0 0x0c40a000 0 0x26000>;
5007 qcom,ee = <0>;
5008 qcom,channel = <0>;
5010 #size-cells = <0>;
5017 reg = <0 0x146bf000 0 0x1000>;
5022 ranges = <0 0 0x146bf000 0x1000>;
5026 reg = <0x94c 0xc8>;
5032 reg = <0 0x15000000 0 0x80000>;
5104 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
5112 reg = <0 0x17900000 0 0xd080>;
5119 reg = <0 0x17980000 0 0x1000>;
5121 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5126 reg = <0 0x17990000 0 0x1000>;
5133 reg = <0 0x179c0000 0 0x10000>,
5134 <0 0x179d0000 0 0x10000>,
5135 <0 0x179e0000 0 0x10000>;
5136 reg-names = "drv-0", "drv-1", "drv-2";
5140 qcom,tcs-offset = <0xd00>;
5217 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5218 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5225 reg = <0 0x17a40000 0 0x20000>;
5233 reg = <0 0x17184000 0 0x2a000>;
5239 iommus = <&apps_smmu 0x1806 0x0>;
5245 ranges = <0 0 0 0x20000000>;
5247 reg = <0 0x17c90000 0 0x1000>;
5250 frame-number = <0>;
5253 reg = <0x17ca0000 0x1000>,
5254 <0x17cb0000 0x1000>;
5260 reg = <0x17cc0000 0x1000>;
5267 reg = <0x17cd0000 0x1000>;
5274 reg = <0x17ce0000 0x1000>;
5281 reg = <0x17cf0000 0x1000>;
5288 reg = <0x17d00000 0x1000>;
5295 reg = <0x17d10000 0x1000>;
5302 reg = <0 0x17d41000 0 0x1400>;
5312 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
5315 interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
5327 reg = <0 0x18800000 0 0x800000>;
5345 iommus = <&apps_smmu 0x0040 0x1>;
5573 thermal-sensors = <&tsens0 0>;
5658 thermal-sensors = <&tsens1 0>;
5780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;