Lines Matching +full:qcom +full:- +full:ipcc
1 // SPDX-License-Identifier: BSD-3-Clause
7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/mailbox/qcom-ipcc.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,gpr.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/sound/qcom,q6afe.h>
21 #include <dt-bindings/thermal/thermal.h>
24 interrupt-parent = <&intc>;
26 #address-cells = <2>;
27 #size-cells = <2>;
30 xo_board_clk: xo-board-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
43 #address-cells = <2>;
44 #size-cells = <0>;
48 compatible = "arm,cortex-a78c";
51 enable-method = "psci";
52 capacity-dmips-mhz = <602>;
53 next-level-cache = <&L2_0>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
56 qcom,freq-domain = <&cpufreq_hw 0>;
57 operating-points-v2 = <&cpu0_opp_table>;
59 #cooling-cells = <2>;
60 L2_0: l2-cache {
62 cache-level = <2>;
63 cache-unified;
64 next-level-cache = <&L3_0>;
65 L3_0: l3-cache {
67 cache-level = <3>;
68 cache-unified;
75 compatible = "arm,cortex-a78c";
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&L2_100>;
81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 operating-points-v2 = <&cpu0_opp_table>;
86 #cooling-cells = <2>;
87 L2_100: l2-cache {
89 cache-level = <2>;
90 cache-unified;
91 next-level-cache = <&L3_0>;
97 compatible = "arm,cortex-a78c";
100 enable-method = "psci";
101 capacity-dmips-mhz = <602>;
102 next-level-cache = <&L2_200>;
103 power-domains = <&CPU_PD2>;
104 power-domain-names = "psci";
105 qcom,freq-domain = <&cpufreq_hw 0>;
106 operating-points-v2 = <&cpu0_opp_table>;
108 #cooling-cells = <2>;
109 L2_200: l2-cache {
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&L3_0>;
119 compatible = "arm,cortex-a78c";
122 enable-method = "psci";
123 capacity-dmips-mhz = <602>;
124 next-level-cache = <&L2_300>;
125 power-domains = <&CPU_PD3>;
126 power-domain-names = "psci";
127 qcom,freq-domain = <&cpufreq_hw 0>;
128 operating-points-v2 = <&cpu0_opp_table>;
130 #cooling-cells = <2>;
131 L2_300: l2-cache {
133 cache-level = <2>;
134 cache-unified;
135 next-level-cache = <&L3_0>;
141 compatible = "arm,cortex-x1c";
144 enable-method = "psci";
145 capacity-dmips-mhz = <1024>;
146 next-level-cache = <&L2_400>;
147 power-domains = <&CPU_PD4>;
148 power-domain-names = "psci";
149 qcom,freq-domain = <&cpufreq_hw 1>;
150 operating-points-v2 = <&cpu4_opp_table>;
152 #cooling-cells = <2>;
153 L2_400: l2-cache {
155 cache-level = <2>;
156 cache-unified;
157 next-level-cache = <&L3_0>;
163 compatible = "arm,cortex-x1c";
166 enable-method = "psci";
167 capacity-dmips-mhz = <1024>;
168 next-level-cache = <&L2_500>;
169 power-domains = <&CPU_PD5>;
170 power-domain-names = "psci";
171 qcom,freq-domain = <&cpufreq_hw 1>;
172 operating-points-v2 = <&cpu4_opp_table>;
174 #cooling-cells = <2>;
175 L2_500: l2-cache {
177 cache-level = <2>;
178 cache-unified;
179 next-level-cache = <&L3_0>;
185 compatible = "arm,cortex-x1c";
188 enable-method = "psci";
189 capacity-dmips-mhz = <1024>;
190 next-level-cache = <&L2_600>;
191 power-domains = <&CPU_PD6>;
192 power-domain-names = "psci";
193 qcom,freq-domain = <&cpufreq_hw 1>;
194 operating-points-v2 = <&cpu4_opp_table>;
196 #cooling-cells = <2>;
197 L2_600: l2-cache {
199 cache-level = <2>;
200 cache-unified;
201 next-level-cache = <&L3_0>;
207 compatible = "arm,cortex-x1c";
210 enable-method = "psci";
211 capacity-dmips-mhz = <1024>;
212 next-level-cache = <&L2_700>;
213 power-domains = <&CPU_PD7>;
214 power-domain-names = "psci";
215 qcom,freq-domain = <&cpufreq_hw 1>;
216 operating-points-v2 = <&cpu4_opp_table>;
218 #cooling-cells = <2>;
219 L2_700: l2-cache {
221 cache-level = <2>;
222 cache-unified;
223 next-level-cache = <&L3_0>;
227 cpu-map {
263 idle-states {
264 entry-method = "psci";
266 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
267 compatible = "arm,idle-state";
268 idle-state-name = "little-rail-power-collapse";
269 arm,psci-suspend-param = <0x40000004>;
270 entry-latency-us = <355>;
271 exit-latency-us = <909>;
272 min-residency-us = <3934>;
273 local-timer-stop;
276 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
277 compatible = "arm,idle-state";
278 idle-state-name = "big-rail-power-collapse";
279 arm,psci-suspend-param = <0x40000004>;
280 entry-latency-us = <241>;
281 exit-latency-us = <1461>;
282 min-residency-us = <4488>;
283 local-timer-stop;
287 domain-idle-states {
288 CLUSTER_SLEEP_0: cluster-sleep-0 {
289 compatible = "domain-idle-state";
290 arm,psci-suspend-param = <0x4100c344>;
291 entry-latency-us = <3263>;
292 exit-latency-us = <6562>;
293 min-residency-us = <9987>;
300 compatible = "qcom,scm-sc8280xp", "qcom,scm";
305 aggre1_noc: interconnect-aggre1-noc {
306 compatible = "qcom,sc8280xp-aggre1-noc";
307 #interconnect-cells = <2>;
308 qcom,bcm-voters = <&apps_bcm_voter>;
311 aggre2_noc: interconnect-aggre2-noc {
312 compatible = "qcom,sc8280xp-aggre2-noc";
313 #interconnect-cells = <2>;
314 qcom,bcm-voters = <&apps_bcm_voter>;
317 clk_virt: interconnect-clk-virt {
318 compatible = "qcom,sc8280xp-clk-virt";
319 #interconnect-cells = <2>;
320 qcom,bcm-voters = <&apps_bcm_voter>;
323 config_noc: interconnect-config-noc {
324 compatible = "qcom,sc8280xp-config-noc";
325 #interconnect-cells = <2>;
326 qcom,bcm-voters = <&apps_bcm_voter>;
329 dc_noc: interconnect-dc-noc {
330 compatible = "qcom,sc8280xp-dc-noc";
331 #interconnect-cells = <2>;
332 qcom,bcm-voters = <&apps_bcm_voter>;
335 gem_noc: interconnect-gem-noc {
336 compatible = "qcom,sc8280xp-gem-noc";
337 #interconnect-cells = <2>;
338 qcom,bcm-voters = <&apps_bcm_voter>;
341 lpass_noc: interconnect-lpass-ag-noc {
342 compatible = "qcom,sc8280xp-lpass-ag-noc";
343 #interconnect-cells = <2>;
344 qcom,bcm-voters = <&apps_bcm_voter>;
347 mc_virt: interconnect-mc-virt {
348 compatible = "qcom,sc8280xp-mc-virt";
349 #interconnect-cells = <2>;
350 qcom,bcm-voters = <&apps_bcm_voter>;
353 mmss_noc: interconnect-mmss-noc {
354 compatible = "qcom,sc8280xp-mmss-noc";
355 #interconnect-cells = <2>;
356 qcom,bcm-voters = <&apps_bcm_voter>;
359 nspa_noc: interconnect-nspa-noc {
360 compatible = "qcom,sc8280xp-nspa-noc";
361 #interconnect-cells = <2>;
362 qcom,bcm-voters = <&apps_bcm_voter>;
365 nspb_noc: interconnect-nspb-noc {
366 compatible = "qcom,sc8280xp-nspb-noc";
367 #interconnect-cells = <2>;
368 qcom,bcm-voters = <&apps_bcm_voter>;
371 system_noc: interconnect-system-noc {
372 compatible = "qcom,sc8280xp-system-noc";
373 #interconnect-cells = <2>;
374 qcom,bcm-voters = <&apps_bcm_voter>;
383 cpu0_opp_table: opp-table-cpu0 {
384 compatible = "operating-points-v2";
385 opp-shared;
387 opp-300000000 {
388 opp-hz = /bits/ 64 <300000000>;
389 opp-peak-kBps = <(300000 * 32)>;
391 opp-403200000 {
392 opp-hz = /bits/ 64 <403200000>;
393 opp-peak-kBps = <(384000 * 32)>;
395 opp-499200000 {
396 opp-hz = /bits/ 64 <499200000>;
397 opp-peak-kBps = <(480000 * 32)>;
399 opp-595200000 {
400 opp-hz = /bits/ 64 <595200000>;
401 opp-peak-kBps = <(576000 * 32)>;
403 opp-691200000 {
404 opp-hz = /bits/ 64 <691200000>;
405 opp-peak-kBps = <(672000 * 32)>;
407 opp-806400000 {
408 opp-hz = /bits/ 64 <806400000>;
409 opp-peak-kBps = <(768000 * 32)>;
411 opp-902400000 {
412 opp-hz = /bits/ 64 <902400000>;
413 opp-peak-kBps = <(864000 * 32)>;
415 opp-1017600000 {
416 opp-hz = /bits/ 64 <1017600000>;
417 opp-peak-kBps = <(960000 * 32)>;
419 opp-1113600000 {
420 opp-hz = /bits/ 64 <1113600000>;
421 opp-peak-kBps = <(1075200 * 32)>;
423 opp-1209600000 {
424 opp-hz = /bits/ 64 <1209600000>;
425 opp-peak-kBps = <(1171200 * 32)>;
427 opp-1324800000 {
428 opp-hz = /bits/ 64 <1324800000>;
429 opp-peak-kBps = <(1267200 * 32)>;
431 opp-1440000000 {
432 opp-hz = /bits/ 64 <1440000000>;
433 opp-peak-kBps = <(1363200 * 32)>;
435 opp-1555200000 {
436 opp-hz = /bits/ 64 <1555200000>;
437 opp-peak-kBps = <(1536000 * 32)>;
439 opp-1670400000 {
440 opp-hz = /bits/ 64 <1670400000>;
441 opp-peak-kBps = <(1612800 * 32)>;
443 opp-1785600000 {
444 opp-hz = /bits/ 64 <1785600000>;
445 opp-peak-kBps = <(1689600 * 32)>;
447 opp-1881600000 {
448 opp-hz = /bits/ 64 <1881600000>;
449 opp-peak-kBps = <(1689600 * 32)>;
451 opp-1996800000 {
452 opp-hz = /bits/ 64 <1996800000>;
453 opp-peak-kBps = <(1689600 * 32)>;
455 opp-2112000000 {
456 opp-hz = /bits/ 64 <2112000000>;
457 opp-peak-kBps = <(1689600 * 32)>;
459 opp-2227200000 {
460 opp-hz = /bits/ 64 <2227200000>;
461 opp-peak-kBps = <(1689600 * 32)>;
463 opp-2342400000 {
464 opp-hz = /bits/ 64 <2342400000>;
465 opp-peak-kBps = <(1689600 * 32)>;
467 opp-2438400000 {
468 opp-hz = /bits/ 64 <2438400000>;
469 opp-peak-kBps = <(1689600 * 32)>;
473 cpu4_opp_table: opp-table-cpu4 {
474 compatible = "operating-points-v2";
475 opp-shared;
477 opp-825600000 {
478 opp-hz = /bits/ 64 <825600000>;
479 opp-peak-kBps = <(768000 * 32)>;
481 opp-940800000 {
482 opp-hz = /bits/ 64 <940800000>;
483 opp-peak-kBps = <(864000 * 32)>;
485 opp-1056000000 {
486 opp-hz = /bits/ 64 <1056000000>;
487 opp-peak-kBps = <(960000 * 32)>;
489 opp-1171200000 {
490 opp-hz = /bits/ 64 <1171200000>;
491 opp-peak-kBps = <(1171200 * 32)>;
493 opp-1286400000 {
494 opp-hz = /bits/ 64 <1286400000>;
495 opp-peak-kBps = <(1267200 * 32)>;
497 opp-1401600000 {
498 opp-hz = /bits/ 64 <1401600000>;
499 opp-peak-kBps = <(1363200 * 32)>;
501 opp-1516800000 {
502 opp-hz = /bits/ 64 <1516800000>;
503 opp-peak-kBps = <(1459200 * 32)>;
505 opp-1632000000 {
506 opp-hz = /bits/ 64 <1632000000>;
507 opp-peak-kBps = <(1612800 * 32)>;
509 opp-1747200000 {
510 opp-hz = /bits/ 64 <1747200000>;
511 opp-peak-kBps = <(1689600 * 32)>;
513 opp-1862400000 {
514 opp-hz = /bits/ 64 <1862400000>;
515 opp-peak-kBps = <(1689600 * 32)>;
517 opp-1977600000 {
518 opp-hz = /bits/ 64 <1977600000>;
519 opp-peak-kBps = <(1689600 * 32)>;
521 opp-2073600000 {
522 opp-hz = /bits/ 64 <2073600000>;
523 opp-peak-kBps = <(1689600 * 32)>;
525 opp-2169600000 {
526 opp-hz = /bits/ 64 <2169600000>;
527 opp-peak-kBps = <(1689600 * 32)>;
529 opp-2284800000 {
530 opp-hz = /bits/ 64 <2284800000>;
531 opp-peak-kBps = <(1689600 * 32)>;
533 opp-2400000000 {
534 opp-hz = /bits/ 64 <2400000000>;
535 opp-peak-kBps = <(1689600 * 32)>;
537 opp-2496000000 {
538 opp-hz = /bits/ 64 <2496000000>;
539 opp-peak-kBps = <(1689600 * 32)>;
541 opp-2592000000 {
542 opp-hz = /bits/ 64 <2592000000>;
543 opp-peak-kBps = <(1689600 * 32)>;
545 opp-2688000000 {
546 opp-hz = /bits/ 64 <2688000000>;
547 opp-peak-kBps = <(1689600 * 32)>;
549 opp-2803200000 {
550 opp-hz = /bits/ 64 <2803200000>;
551 opp-peak-kBps = <(1689600 * 32)>;
553 opp-2899200000 {
554 opp-hz = /bits/ 64 <2899200000>;
555 opp-peak-kBps = <(1689600 * 32)>;
557 opp-2995200000 {
558 opp-hz = /bits/ 64 <2995200000>;
559 opp-peak-kBps = <(1689600 * 32)>;
563 qup_opp_table_100mhz: opp-table-qup100mhz {
564 compatible = "operating-points-v2";
566 opp-75000000 {
567 opp-hz = /bits/ 64 <75000000>;
568 required-opps = <&rpmhpd_opp_low_svs>;
571 opp-100000000 {
572 opp-hz = /bits/ 64 <100000000>;
573 required-opps = <&rpmhpd_opp_svs>;
578 compatible = "arm,armv8-pmuv3";
583 compatible = "arm,psci-1.0";
586 CPU_PD0: power-domain-cpu0 {
587 #power-domain-cells = <0>;
588 power-domains = <&CLUSTER_PD>;
589 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
592 CPU_PD1: power-domain-cpu1 {
593 #power-domain-cells = <0>;
594 power-domains = <&CLUSTER_PD>;
595 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
598 CPU_PD2: power-domain-cpu2 {
599 #power-domain-cells = <0>;
600 power-domains = <&CLUSTER_PD>;
601 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
604 CPU_PD3: power-domain-cpu3 {
605 #power-domain-cells = <0>;
606 power-domains = <&CLUSTER_PD>;
607 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
610 CPU_PD4: power-domain-cpu4 {
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&BIG_CPU_SLEEP_0>;
616 CPU_PD5: power-domain-cpu5 {
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&BIG_CPU_SLEEP_0>;
622 CPU_PD6: power-domain-cpu6 {
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&BIG_CPU_SLEEP_0>;
628 CPU_PD7: power-domain-cpu7 {
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&BIG_CPU_SLEEP_0>;
634 CLUSTER_PD: power-domain-cpu-cluster0 {
635 #power-domain-cells = <0>;
636 domain-idle-states = <&CLUSTER_SLEEP_0>;
640 reserved-memory {
641 #address-cells = <2>;
642 #size-cells = <2>;
645 reserved-region@80000000 {
647 no-map;
650 cmd_db: cmd-db-region@80860000 {
651 compatible = "qcom,cmd-db";
653 no-map;
656 reserved-region@80880000 {
658 no-map;
661 smem_mem: smem-region@80900000 {
662 compatible = "qcom,smem";
664 no-map;
668 reserved-region@80b00000 {
670 no-map;
673 reserved-region@83b00000 {
675 no-map;
678 reserved-region@85b00000 {
680 no-map;
683 pil_adsp_mem: adsp-region@86c00000 {
685 no-map;
688 pil_nsp0_mem: cdsp0-region@8a100000 {
690 no-map;
693 pil_nsp1_mem: cdsp1-region@8c600000 {
695 no-map;
698 reserved-region@aeb00000 {
700 no-map;
704 smp2p-adsp {
705 compatible = "qcom,smp2p";
706 qcom,smem = <443>, <429>;
707 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
710 mboxes = <&ipcc IPCC_CLIENT_LPASS
713 qcom,local-pid = <0>;
714 qcom,remote-pid = <2>;
716 smp2p_adsp_out: master-kernel {
717 qcom,entry-name = "master-kernel";
718 #qcom,smem-state-cells = <1>;
721 smp2p_adsp_in: slave-kernel {
722 qcom,entry-name = "slave-kernel";
723 interrupt-controller;
724 #interrupt-cells = <2>;
728 smp2p-nsp0 {
729 compatible = "qcom,smp2p";
730 qcom,smem = <94>, <432>;
731 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
734 mboxes = <&ipcc IPCC_CLIENT_CDSP
737 qcom,local-pid = <0>;
738 qcom,remote-pid = <5>;
740 smp2p_nsp0_out: master-kernel {
741 qcom,entry-name = "master-kernel";
742 #qcom,smem-state-cells = <1>;
745 smp2p_nsp0_in: slave-kernel {
746 qcom,entry-name = "slave-kernel";
747 interrupt-controller;
748 #interrupt-cells = <2>;
752 smp2p-nsp1 {
753 compatible = "qcom,smp2p";
754 qcom,smem = <617>, <616>;
755 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
758 mboxes = <&ipcc IPCC_CLIENT_NSP1
761 qcom,local-pid = <0>;
762 qcom,remote-pid = <12>;
764 smp2p_nsp1_out: master-kernel {
765 qcom,entry-name = "master-kernel";
766 #qcom,smem-state-cells = <1>;
769 smp2p_nsp1_in: slave-kernel {
770 qcom,entry-name = "slave-kernel";
771 interrupt-controller;
772 #interrupt-cells = <2>;
777 compatible = "simple-bus";
778 #address-cells = <2>;
779 #size-cells = <2>;
781 dma-ranges = <0 0 0 0 0x10 0>;
784 compatible = "qcom,sc8280xp-ethqos";
787 reg-names = "stmmaceth", "rgmii";
793 clock-names = "stmmaceth",
800 interrupt-names = "macirq", "eth_lpi";
803 power-domains = <&gcc EMAC_0_GDSC>;
807 rx-fifo-depth = <4096>;
808 tx-fifo-depth = <4096>;
813 gcc: clock-controller@100000 {
814 compatible = "qcom,gcc-sc8280xp";
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 #power-domain-cells = <1>;
852 power-domains = <&rpmhpd SC8280XP_CX>;
855 ipcc: mailbox@408000 { label
856 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
859 interrupt-controller;
860 #interrupt-cells = <3>;
861 #mbox-cells = <2>;
865 compatible = "qcom,geni-se-qup";
869 clock-names = "m-ahb", "s-ahb";
872 #address-cells = <2>;
873 #size-cells = <2>;
879 compatible = "qcom,geni-i2c";
881 #address-cells = <1>;
882 #size-cells = <0>;
884 clock-names = "se";
886 power-domains = <&rpmhpd SC8280XP_CX>;
890 interconnect-names = "qup-core", "qup-config", "qup-memory";
895 compatible = "qcom,geni-spi";
897 #address-cells = <1>;
898 #size-cells = <0>;
900 clock-names = "se";
902 power-domains = <&rpmhpd SC8280XP_CX>;
906 interconnect-names = "qup-core", "qup-config", "qup-memory";
911 compatible = "qcom,geni-i2c";
913 #address-cells = <1>;
914 #size-cells = <0>;
916 clock-names = "se";
918 power-domains = <&rpmhpd SC8280XP_CX>;
922 interconnect-names = "qup-core", "qup-config", "qup-memory";
927 compatible = "qcom,geni-spi";
929 #address-cells = <1>;
930 #size-cells = <0>;
932 clock-names = "se";
934 power-domains = <&rpmhpd SC8280XP_CX>;
938 interconnect-names = "qup-core", "qup-config", "qup-memory";
943 compatible = "qcom,geni-uart";
946 clock-names = "se";
948 operating-points-v2 = <&qup_opp_table_100mhz>;
949 power-domains = <&rpmhpd SC8280XP_CX>;
952 interconnect-names = "qup-core", "qup-config";
957 compatible = "qcom,geni-i2c";
959 #address-cells = <1>;
960 #size-cells = <0>;
962 clock-names = "se";
964 power-domains = <&rpmhpd SC8280XP_CX>;
968 interconnect-names = "qup-core", "qup-config", "qup-memory";
973 compatible = "qcom,geni-spi";
975 #address-cells = <1>;
976 #size-cells = <0>;
978 clock-names = "se";
980 power-domains = <&rpmhpd SC8280XP_CX>;
984 interconnect-names = "qup-core", "qup-config", "qup-memory";
989 compatible = "qcom,geni-i2c";
991 #address-cells = <1>;
992 #size-cells = <0>;
994 clock-names = "se";
996 power-domains = <&rpmhpd SC8280XP_CX>;
1000 interconnect-names = "qup-core", "qup-config", "qup-memory";
1005 compatible = "qcom,geni-spi";
1007 #address-cells = <1>;
1008 #size-cells = <0>;
1010 clock-names = "se";
1012 power-domains = <&rpmhpd SC8280XP_CX>;
1016 interconnect-names = "qup-core", "qup-config", "qup-memory";
1021 compatible = "qcom,geni-i2c";
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1026 clock-names = "se";
1028 power-domains = <&rpmhpd SC8280XP_CX>;
1032 interconnect-names = "qup-core", "qup-config", "qup-memory";
1037 compatible = "qcom,geni-spi";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1042 clock-names = "se";
1044 power-domains = <&rpmhpd SC8280XP_CX>;
1048 interconnect-names = "qup-core", "qup-config", "qup-memory";
1053 compatible = "qcom,geni-i2c";
1055 clock-names = "se";
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1060 power-domains = <&rpmhpd SC8280XP_CX>;
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1069 compatible = "qcom,geni-spi";
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1074 clock-names = "se";
1076 power-domains = <&rpmhpd SC8280XP_CX>;
1080 interconnect-names = "qup-core", "qup-config", "qup-memory";
1085 compatible = "qcom,geni-i2c";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 clock-names = "se";
1092 power-domains = <&rpmhpd SC8280XP_CX>;
1096 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 compatible = "qcom,geni-spi";
1103 #address-cells = <1>;
1104 #size-cells = <0>;
1106 clock-names = "se";
1108 power-domains = <&rpmhpd SC8280XP_CX>;
1112 interconnect-names = "qup-core", "qup-config", "qup-memory";
1117 compatible = "qcom,geni-i2c";
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 clock-names = "se";
1124 power-domains = <&rpmhpd SC8280XP_CX>;
1128 interconnect-names = "qup-core", "qup-config", "qup-memory";
1133 compatible = "qcom,geni-spi";
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1138 clock-names = "se";
1140 power-domains = <&rpmhpd SC8280XP_CX>;
1144 interconnect-names = "qup-core", "qup-config", "qup-memory";
1150 compatible = "qcom,geni-se-qup";
1154 clock-names = "m-ahb", "s-ahb";
1157 #address-cells = <2>;
1158 #size-cells = <2>;
1164 compatible = "qcom,geni-i2c";
1166 #address-cells = <1>;
1167 #size-cells = <0>;
1168 clock-names = "se";
1171 power-domains = <&rpmhpd SC8280XP_CX>;
1175 interconnect-names = "qup-core", "qup-config", "qup-memory";
1180 compatible = "qcom,geni-spi";
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1185 clock-names = "se";
1187 power-domains = <&rpmhpd SC8280XP_CX>;
1191 interconnect-names = "qup-core", "qup-config", "qup-memory";
1196 compatible = "qcom,geni-i2c";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 clock-names = "se";
1203 power-domains = <&rpmhpd SC8280XP_CX>;
1207 interconnect-names = "qup-core", "qup-config", "qup-memory";
1212 compatible = "qcom,geni-spi";
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1217 clock-names = "se";
1219 power-domains = <&rpmhpd SC8280XP_CX>;
1223 interconnect-names = "qup-core", "qup-config", "qup-memory";
1228 compatible = "qcom,geni-i2c";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 clock-names = "se";
1235 power-domains = <&rpmhpd SC8280XP_CX>;
1239 interconnect-names = "qup-core", "qup-config", "qup-memory";
1244 compatible = "qcom,geni-spi";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1249 clock-names = "se";
1251 power-domains = <&rpmhpd SC8280XP_CX>;
1255 interconnect-names = "qup-core", "qup-config", "qup-memory";
1260 compatible = "qcom,geni-uart";
1263 clock-names = "se";
1265 operating-points-v2 = <&qup_opp_table_100mhz>;
1266 power-domains = <&rpmhpd SC8280XP_CX>;
1269 interconnect-names = "qup-core", "qup-config";
1274 compatible = "qcom,geni-i2c";
1276 #address-cells = <1>;
1277 #size-cells = <0>;
1278 clock-names = "se";
1281 power-domains = <&rpmhpd SC8280XP_CX>;
1285 interconnect-names = "qup-core", "qup-config", "qup-memory";
1290 compatible = "qcom,geni-spi";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1295 clock-names = "se";
1297 power-domains = <&rpmhpd SC8280XP_CX>;
1301 interconnect-names = "qup-core", "qup-config", "qup-memory";
1306 compatible = "qcom,geni-i2c";
1308 clock-names = "se";
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1313 power-domains = <&rpmhpd SC8280XP_CX>;
1317 interconnect-names = "qup-core", "qup-config", "qup-memory";
1322 compatible = "qcom,geni-spi";
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1327 clock-names = "se";
1329 power-domains = <&rpmhpd SC8280XP_CX>;
1333 interconnect-names = "qup-core", "qup-config", "qup-memory";
1338 compatible = "qcom,geni-i2c";
1340 #address-cells = <1>;
1341 #size-cells = <0>;
1342 clock-names = "se";
1345 power-domains = <&rpmhpd SC8280XP_CX>;
1349 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 compatible = "qcom,geni-spi";
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1359 clock-names = "se";
1361 power-domains = <&rpmhpd SC8280XP_CX>;
1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1370 compatible = "qcom,geni-i2c";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1374 clock-names = "se";
1377 power-domains = <&rpmhpd SC8280XP_CX>;
1381 interconnect-names = "qup-core", "qup-config", "qup-memory";
1386 compatible = "qcom,geni-spi";
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1391 clock-names = "se";
1393 power-domains = <&rpmhpd SC8280XP_CX>;
1397 interconnect-names = "qup-core", "qup-config", "qup-memory";
1402 compatible = "qcom,geni-i2c";
1404 #address-cells = <1>;
1405 #size-cells = <0>;
1406 clock-names = "se";
1409 power-domains = <&rpmhpd SC8280XP_CX>;
1413 interconnect-names = "qup-core", "qup-config", "qup-memory";
1418 compatible = "qcom,geni-spi";
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1423 clock-names = "se";
1425 power-domains = <&rpmhpd SC8280XP_CX>;
1429 interconnect-names = "qup-core", "qup-config", "qup-memory";
1435 compatible = "qcom,geni-se-qup";
1439 clock-names = "m-ahb", "s-ahb";
1442 #address-cells = <2>;
1443 #size-cells = <2>;
1449 compatible = "qcom,geni-i2c";
1451 #address-cells = <1>;
1452 #size-cells = <0>;
1454 clock-names = "se";
1456 power-domains = <&rpmhpd SC8280XP_CX>;
1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1465 compatible = "qcom,geni-spi";
1467 #address-cells = <1>;
1468 #size-cells = <0>;
1470 clock-names = "se";
1472 power-domains = <&rpmhpd SC8280XP_CX>;
1476 interconnect-names = "qup-core", "qup-config", "qup-memory";
1481 compatible = "qcom,geni-i2c";
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1486 clock-names = "se";
1488 power-domains = <&rpmhpd SC8280XP_CX>;
1492 interconnect-names = "qup-core", "qup-config", "qup-memory";
1497 compatible = "qcom,geni-spi";
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1502 clock-names = "se";
1504 power-domains = <&rpmhpd SC8280XP_CX>;
1508 interconnect-names = "qup-core", "qup-config", "qup-memory";
1513 compatible = "qcom,geni-i2c";
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1518 clock-names = "se";
1520 power-domains = <&rpmhpd SC8280XP_CX>;
1524 interconnect-names = "qup-core", "qup-config", "qup-memory";
1529 compatible = "qcom,geni-spi";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1534 clock-names = "se";
1536 power-domains = <&rpmhpd SC8280XP_CX>;
1540 interconnect-names = "qup-core", "qup-config", "qup-memory";
1545 compatible = "qcom,geni-i2c";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1550 clock-names = "se";
1552 power-domains = <&rpmhpd SC8280XP_CX>;
1556 interconnect-names = "qup-core", "qup-config", "qup-memory";
1561 compatible = "qcom,geni-spi";
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1566 clock-names = "se";
1568 power-domains = <&rpmhpd SC8280XP_CX>;
1572 interconnect-names = "qup-core", "qup-config", "qup-memory";
1577 compatible = "qcom,geni-i2c";
1579 #address-cells = <1>;
1580 #size-cells = <0>;
1582 clock-names = "se";
1584 power-domains = <&rpmhpd SC8280XP_CX>;
1588 interconnect-names = "qup-core", "qup-config", "qup-memory";
1593 compatible = "qcom,geni-spi";
1595 #address-cells = <1>;
1596 #size-cells = <0>;
1598 clock-names = "se";
1600 power-domains = <&rpmhpd SC8280XP_CX>;
1604 interconnect-names = "qup-core", "qup-config", "qup-memory";
1609 compatible = "qcom,geni-i2c";
1611 #address-cells = <1>;
1612 #size-cells = <0>;
1614 clock-names = "se";
1616 power-domains = <&rpmhpd SC8280XP_CX>;
1620 interconnect-names = "qup-core", "qup-config", "qup-memory";
1625 compatible = "qcom,geni-spi";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1630 clock-names = "se";
1632 power-domains = <&rpmhpd SC8280XP_CX>;
1636 interconnect-names = "qup-core", "qup-config", "qup-memory";
1641 compatible = "qcom,geni-i2c";
1643 #address-cells = <1>;
1644 #size-cells = <0>;
1646 clock-names = "se";
1648 power-domains = <&rpmhpd SC8280XP_CX>;
1652 interconnect-names = "qup-core", "qup-config", "qup-memory";
1657 compatible = "qcom,geni-spi";
1659 #address-cells = <1>;
1660 #size-cells = <0>;
1662 clock-names = "se";
1664 power-domains = <&rpmhpd SC8280XP_CX>;
1668 interconnect-names = "qup-core", "qup-config", "qup-memory";
1673 compatible = "qcom,geni-i2c";
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1678 clock-names = "se";
1680 power-domains = <&rpmhpd SC8280XP_CX>;
1684 interconnect-names = "qup-core", "qup-config", "qup-memory";
1689 compatible = "qcom,geni-spi";
1691 #address-cells = <1>;
1692 #size-cells = <0>;
1694 clock-names = "se";
1696 power-domains = <&rpmhpd SC8280XP_CX>;
1700 interconnect-names = "qup-core", "qup-config", "qup-memory";
1706 compatible = "qcom,prng-ee";
1709 clock-names = "core";
1714 compatible = "qcom,pcie-sc8280xp";
1721 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1722 #address-cells = <3>;
1723 #size-cells = <2>;
1726 bus-range = <0x00 0xff>;
1728 dma-coherent;
1730 linux,pci-domain = <6>;
1731 num-lanes = <1>;
1737 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1739 #interrupt-cells = <1>;
1740 interrupt-map-mask = <0 0 0 0x7>;
1741 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1755 clock-names = "aux",
1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1766 assigned-clock-rates = <19200000>;
1770 interconnect-names = "pcie-mem", "cpu-pcie";
1773 reset-names = "pci";
1775 power-domains = <&gcc PCIE_4_GDSC>;
1778 phy-names = "pciephy";
1784 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1793 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1796 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1797 assigned-clock-rates = <100000000>;
1799 power-domains = <&gcc PCIE_4_GDSC>;
1802 reset-names = "phy";
1804 #clock-cells = <0>;
1805 clock-output-names = "pcie_4_pipe_clk";
1807 #phy-cells = <0>;
1814 compatible = "qcom,pcie-sc8280xp";
1821 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1822 #address-cells = <3>;
1823 #size-cells = <2>;
1826 bus-range = <0x00 0xff>;
1828 dma-coherent;
1830 linux,pci-domain = <5>;
1831 num-lanes = <2>;
1837 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1839 #interrupt-cells = <1>;
1840 interrupt-map-mask = <0 0 0 0x7>;
1841 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1854 clock-names = "aux",
1863 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1864 assigned-clock-rates = <19200000>;
1868 interconnect-names = "pcie-mem", "cpu-pcie";
1871 reset-names = "pci";
1873 power-domains = <&gcc PCIE_3B_GDSC>;
1876 phy-names = "pciephy";
1882 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1891 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1894 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1895 assigned-clock-rates = <100000000>;
1897 power-domains = <&gcc PCIE_3B_GDSC>;
1900 reset-names = "phy";
1902 #clock-cells = <0>;
1903 clock-output-names = "pcie_3b_pipe_clk";
1905 #phy-cells = <0>;
1912 compatible = "qcom,pcie-sc8280xp";
1919 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1920 #address-cells = <3>;
1921 #size-cells = <2>;
1924 bus-range = <0x00 0xff>;
1926 dma-coherent;
1928 linux,pci-domain = <4>;
1929 num-lanes = <4>;
1935 interrupt-names = "msi0", "msi1", "msi2", "msi3";
1937 #interrupt-cells = <1>;
1938 interrupt-map-mask = <0 0 0 0x7>;
1939 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1952 clock-names = "aux",
1961 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1962 assigned-clock-rates = <19200000>;
1966 interconnect-names = "pcie-mem", "cpu-pcie";
1969 reset-names = "pci";
1971 power-domains = <&gcc PCIE_3A_GDSC>;
1974 phy-names = "pciephy";
1980 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1990 clock-names = "aux", "cfg_ahb", "ref", "rchng",
1993 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1994 assigned-clock-rates = <100000000>;
1996 power-domains = <&gcc PCIE_3A_GDSC>;
1999 reset-names = "phy";
2001 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2003 #clock-cells = <0>;
2004 clock-output-names = "pcie_3a_pipe_clk";
2006 #phy-cells = <0>;
2013 compatible = "qcom,pcie-sc8280xp";
2020 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2021 #address-cells = <3>;
2022 #size-cells = <2>;
2025 bus-range = <0x00 0xff>;
2027 dma-coherent;
2029 linux,pci-domain = <3>;
2030 num-lanes = <2>;
2036 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2038 #interrupt-cells = <1>;
2039 interrupt-map-mask = <0 0 0 0x7>;
2040 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2053 clock-names = "aux",
2062 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2063 assigned-clock-rates = <19200000>;
2067 interconnect-names = "pcie-mem", "cpu-pcie";
2070 reset-names = "pci";
2072 power-domains = <&gcc PCIE_2B_GDSC>;
2075 phy-names = "pciephy";
2081 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2090 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2093 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2094 assigned-clock-rates = <100000000>;
2096 power-domains = <&gcc PCIE_2B_GDSC>;
2099 reset-names = "phy";
2101 #clock-cells = <0>;
2102 clock-output-names = "pcie_2b_pipe_clk";
2104 #phy-cells = <0>;
2111 compatible = "qcom,pcie-sc8280xp";
2118 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2119 #address-cells = <3>;
2120 #size-cells = <2>;
2123 bus-range = <0x00 0xff>;
2125 dma-coherent;
2127 linux,pci-domain = <2>;
2128 num-lanes = <4>;
2134 interrupt-names = "msi0", "msi1", "msi2", "msi3";
2136 #interrupt-cells = <1>;
2137 interrupt-map-mask = <0 0 0 0x7>;
2138 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2151 clock-names = "aux",
2160 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2161 assigned-clock-rates = <19200000>;
2165 interconnect-names = "pcie-mem", "cpu-pcie";
2168 reset-names = "pci";
2170 power-domains = <&gcc PCIE_2A_GDSC>;
2173 phy-names = "pciephy";
2179 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2189 clock-names = "aux", "cfg_ahb", "ref", "rchng",
2192 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2193 assigned-clock-rates = <100000000>;
2195 power-domains = <&gcc PCIE_2A_GDSC>;
2198 reset-names = "phy";
2200 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2202 #clock-cells = <0>;
2203 clock-output-names = "pcie_2a_pipe_clk";
2205 #phy-cells = <0>;
2211 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2212 "jedec,ufs-2.0";
2216 phy-names = "ufsphy";
2217 lanes-per-direction = <2>;
2218 #reset-cells = <1>;
2220 reset-names = "rst";
2222 power-domains = <&gcc UFS_PHY_GDSC>;
2223 required-opps = <&rpmhpd_opp_nom>;
2226 dma-coherent;
2236 clock-names = "core_clk",
2244 freq-table-hz = <75000000 300000000>,
2256 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2261 clock-names = "ref", "ref_aux";
2263 power-domains = <&gcc UFS_PHY_GDSC>;
2266 reset-names = "ufsphy";
2268 #phy-cells = <0>;
2274 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2275 "jedec,ufs-2.0";
2279 phy-names = "ufsphy";
2280 lanes-per-direction = <2>;
2281 #reset-cells = <1>;
2283 reset-names = "rst";
2285 power-domains = <&gcc UFS_CARD_GDSC>;
2288 dma-coherent;
2298 clock-names = "core_clk",
2306 freq-table-hz = <75000000 300000000>,
2318 compatible = "qcom,sc8280xp-qmp-ufs-phy";
2323 clock-names = "ref", "ref_aux";
2325 power-domains = <&gcc UFS_CARD_GDSC>;
2328 reset-names = "ufsphy";
2330 #phy-cells = <0>;
2336 compatible = "qcom,tcsr-mutex";
2338 #hwlock-cells = <1>;
2342 compatible = "qcom,sc8280xp-tcsr", "syscon";
2347 compatible = "qcom,adreno-690.0", "qcom,adreno";
2352 reg-names = "kgsl_3d0_reg_memory",
2357 operating-points-v2 = <&gpu_opp_table>;
2359 qcom,gmu = <&gmu>;
2361 interconnect-names = "gfx-mem";
2362 #cooling-cells = <2>;
2366 gpu_opp_table: opp-table {
2367 compatible = "operating-points-v2";
2369 opp-270000000 {
2370 opp-hz = /bits/ 64 <270000000>;
2371 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2372 opp-peak-kBps = <451000>;
2375 opp-410000000 {
2376 opp-hz = /bits/ 64 <410000000>;
2377 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2378 opp-peak-kBps = <1555000>;
2381 opp-500000000 {
2382 opp-hz = /bits/ 64 <500000000>;
2383 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2384 opp-peak-kBps = <1555000>;
2387 opp-547000000 {
2388 opp-hz = /bits/ 64 <547000000>;
2389 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2390 opp-peak-kBps = <1555000>;
2393 opp-606000000 {
2394 opp-hz = /bits/ 64 <606000000>;
2395 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2396 opp-peak-kBps = <2736000>;
2399 opp-640000000 {
2400 opp-hz = /bits/ 64 <640000000>;
2401 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2402 opp-peak-kBps = <2736000>;
2405 opp-655000000 {
2406 opp-hz = /bits/ 64 <655000000>;
2407 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2408 opp-peak-kBps = <2736000>;
2411 opp-690000000 {
2412 opp-hz = /bits/ 64 <690000000>;
2413 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2414 opp-peak-kBps = <2736000>;
2420 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2424 reg-names = "gmu", "rscc", "gmu_pdc";
2427 interrupt-names = "hfi", "gmu";
2435 clock-names = "gmu",
2442 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2444 power-domain-names = "cx",
2447 operating-points-v2 = <&gmu_opp_table>;
2449 gmu_opp_table: opp-table {
2450 compatible = "operating-points-v2";
2452 opp-200000000 {
2453 opp-hz = /bits/ 64 <200000000>;
2454 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2457 opp-500000000 {
2458 opp-hz = /bits/ 64 <500000000>;
2459 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2464 gpucc: clock-controller@3d90000 {
2465 compatible = "qcom,sc8280xp-gpucc";
2470 clock-names = "bi_tcxo",
2474 power-domains = <&rpmhpd SC8280XP_GFX>;
2475 #clock-cells = <1>;
2476 #reset-cells = <1>;
2477 #power-domain-cells = <1>;
2481 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2482 "qcom,smmu-500", "arm,mmu-500";
2484 #iommu-cells = <2>;
2485 #global-interrupts = <2>;
2508 clock-names = "gcc_gpu_memnoc_gfx_clk",
2516 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2517 dma-coherent;
2521 compatible = "qcom,sc8280xp-usb-hs-phy",
2522 "qcom,usb-snps-hs-5nm-phy";
2525 clock-names = "ref";
2528 #phy-cells = <0>;
2534 compatible = "qcom,sc8280xp-usb-hs-phy",
2535 "qcom,usb-snps-hs-5nm-phy";
2538 clock-names = "ref";
2541 #phy-cells = <0>;
2547 compatible = "qcom,sc8280xp-usb-hs-phy",
2548 "qcom,usb-snps-hs-5nm-phy";
2551 clock-names = "ref";
2554 #phy-cells = <0>;
2560 compatible = "qcom,sc8280xp-usb-hs-phy",
2561 "qcom,usb-snps-hs-5nm-phy";
2564 clock-names = "ref";
2567 #phy-cells = <0>;
2573 compatible = "qcom,sc8280xp-usb-hs-phy",
2574 "qcom,usb-snps-hs-5nm-phy";
2577 clock-names = "ref";
2580 #phy-cells = <0>;
2586 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2593 clock-names = "aux", "ref", "com_aux", "pipe";
2597 reset-names = "phy", "phy_phy";
2599 power-domains = <&gcc USB30_MP_GDSC>;
2601 #clock-cells = <0>;
2602 clock-output-names = "usb2_phy0_pipe_clk";
2604 #phy-cells = <0>;
2610 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2617 clock-names = "aux", "ref", "com_aux", "pipe";
2621 reset-names = "phy", "phy_phy";
2623 power-domains = <&gcc USB30_MP_GDSC>;
2625 #clock-cells = <0>;
2626 clock-output-names = "usb2_phy1_pipe_clk";
2628 #phy-cells = <0>;
2634 compatible = "qcom,sc8280xp-adsp-pas";
2637 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2643 interrupt-names = "wdog", "fatal", "ready",
2644 "handover", "stop-ack", "shutdown-ack";
2647 clock-names = "xo";
2649 power-domains = <&rpmhpd SC8280XP_LCX>,
2651 power-domain-names = "lcx", "lmx";
2653 memory-region = <&pil_adsp_mem>;
2655 qcom,qmp = <&aoss_qmp>;
2657 qcom,smem-states = <&smp2p_adsp_out 0>;
2658 qcom,smem-state-names = "stop";
2662 remoteproc_adsp_glink: glink-edge {
2663 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2666 mboxes = <&ipcc IPCC_CLIENT_LPASS
2670 qcom,remote-pid = <2>;
2673 compatible = "qcom,gpr";
2674 qcom,glink-channels = "adsp_apps";
2675 qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2676 qcom,intents = <512 20>;
2677 #address-cells = <1>;
2678 #size-cells = <0>;
2681 compatible = "qcom,q6apm";
2683 #sound-dai-cells = <0>;
2684 qcom,protection-domain = "avs/audio",
2687 compatible = "qcom,q6apm-dais";
2692 compatible = "qcom,q6apm-lpass-dais";
2693 #sound-dai-cells = <1>;
2698 compatible = "qcom,q6prm";
2700 qcom,protection-domain = "avs/audio",
2702 q6prmcc: clock-controller {
2703 compatible = "qcom,q6prm-lpass-clocks";
2704 #clock-cells = <2>;
2712 compatible = "qcom,sc8280xp-lpass-rx-macro";
2719 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2720 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2722 assigned-clock-rates = <19200000>, <19200000>;
2724 clock-output-names = "mclk";
2725 #clock-cells = <0>;
2726 #sound-dai-cells = <1>;
2728 pinctrl-names = "default";
2729 pinctrl-0 = <&rx_swr_default>;
2734 swr1: soundwire-controller@3210000 {
2735 compatible = "qcom,soundwire-v1.6.0";
2739 clock-names = "iface";
2741 reset-names = "swr_audio_cgcr";
2744 qcom,din-ports = <0>;
2745 qcom,dout-ports = <5>;
2747 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2748 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2749 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2750 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2751 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2752 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2753 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2754 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2755 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2757 #sound-dai-cells = <1>;
2758 #address-cells = <2>;
2759 #size-cells = <0>;
2765 compatible = "qcom,sc8280xp-lpass-tx-macro";
2767 pinctrl-names = "default";
2768 pinctrl-0 = <&tx_swr_default>;
2775 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2776 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2778 assigned-clock-rates = <19200000>, <19200000>;
2779 clock-output-names = "mclk";
2781 #clock-cells = <0>;
2782 #sound-dai-cells = <1>;
2788 compatible = "qcom,sc8280xp-lpass-wsa-macro";
2795 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2796 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2798 assigned-clock-rates = <19200000>, <19200000>;
2800 #clock-cells = <0>;
2801 clock-output-names = "mclk";
2802 #sound-dai-cells = <1>;
2804 pinctrl-names = "default";
2805 pinctrl-0 = <&wsa_swr_default>;
2810 swr0: soundwire-controller@3250000 {
2812 compatible = "qcom,soundwire-v1.6.0";
2815 clock-names = "iface";
2817 reset-names = "swr_audio_cgcr";
2820 qcom,din-ports = <2>;
2821 qcom,dout-ports = <6>;
2823 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2824 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2825 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2826 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2827 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2829 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2830 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2831 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2833 #sound-dai-cells = <1>;
2834 #address-cells = <2>;
2835 #size-cells = <0>;
2840 lpass_audiocc: clock-controller@32a9000 {
2841 compatible = "qcom,sc8280xp-lpassaudiocc";
2843 #clock-cells = <1>;
2844 #reset-cells = <1>;
2847 swr2: soundwire-controller@3330000 {
2848 compatible = "qcom,soundwire-v1.6.0";
2852 interrupt-names = "core", "wakeup";
2855 clock-names = "iface";
2857 reset-names = "swr_audio_cgcr";
2859 #sound-dai-cells = <1>;
2860 #address-cells = <2>;
2861 #size-cells = <0>;
2863 qcom,din-ports = <4>;
2864 qcom,dout-ports = <0>;
2865 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2866 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
2867 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2868 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2869 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2870 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2871 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2872 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2873 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
2879 compatible = "qcom,sc8280xp-lpass-va-macro";
2885 clock-names = "mclk", "macro", "dcodec", "npl";
2886 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2887 assigned-clock-rates = <19200000>;
2889 #clock-cells = <0>;
2890 clock-output-names = "fsgen";
2891 #sound-dai-cells = <1>;
2897 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2900 gpio-controller;
2901 #gpio-cells = <2>;
2902 gpio-ranges = <&lpass_tlmm 0 0 19>;
2906 clock-names = "core", "audio";
2910 tx_swr_default: tx-swr-default-state {
2911 clk-pins {
2914 drive-strength = <2>;
2915 slew-rate = <1>;
2916 bias-disable;
2919 data-pins {
2922 drive-strength = <2>;
2923 slew-rate = <1>;
2924 bias-bus-hold;
2928 rx_swr_default: rx-swr-default-state {
2929 clk-pins {
2932 drive-strength = <2>;
2933 slew-rate = <1>;
2934 bias-disable;
2937 data-pins {
2940 drive-strength = <2>;
2941 slew-rate = <1>;
2942 bias-bus-hold;
2946 dmic01_default: dmic01-default-state {
2947 clk-pins {
2950 drive-strength = <8>;
2951 output-high;
2954 data-pins {
2957 drive-strength = <8>;
2958 input-enable;
2962 dmic01_sleep: dmic01-sleep-state {
2963 clk-pins {
2966 drive-strength = <2>;
2967 bias-disable;
2968 output-low;
2971 data-pins {
2974 drive-strength = <2>;
2975 bias-pull-down;
2976 input-enable;
2980 dmic02_default: dmic02-default-state {
2981 clk-pins {
2984 drive-strength = <8>;
2985 output-high;
2988 data-pins {
2991 drive-strength = <8>;
2992 input-enable;
2996 dmic02_sleep: dmic02-sleep-state {
2997 clk-pins {
3000 drive-strength = <2>;
3001 bias-disable;
3002 output-low;
3005 data-pins {
3008 drive-strength = <2>;
3009 bias-pull-down;
3010 input-enable;
3014 wsa_swr_default: wsa-swr-default-state {
3015 clk-pins {
3018 drive-strength = <2>;
3019 slew-rate = <1>;
3020 bias-disable;
3023 data-pins {
3026 drive-strength = <2>;
3027 slew-rate = <1>;
3028 bias-bus-hold;
3032 wsa2_swr_default: wsa2-swr-default-state {
3033 clk-pins {
3036 drive-strength = <2>;
3037 slew-rate = <1>;
3038 bias-disable;
3041 data-pins {
3044 drive-strength = <2>;
3045 slew-rate = <1>;
3046 bias-bus-hold;
3051 lpasscc: clock-controller@33e0000 {
3052 compatible = "qcom,sc8280xp-lpasscc";
3054 #clock-cells = <1>;
3055 #reset-cells = <1>;
3059 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3064 interrupt-names = "hc_irq", "pwr_irq";
3069 clock-names = "iface", "core", "xo";
3073 interconnect-names = "sdhc-ddr","cpu-sdhc";
3075 power-domains = <&rpmhpd SC8280XP_CX>;
3076 operating-points-v2 = <&sdc2_opp_table>;
3077 bus-width = <4>;
3078 dma-coherent;
3082 sdc2_opp_table: opp-table {
3083 compatible = "operating-points-v2";
3085 opp-100000000 {
3086 opp-hz = /bits/ 64 <100000000>;
3087 required-opps = <&rpmhpd_opp_low_svs>;
3088 opp-peak-kBps = <1800000 400000>;
3089 opp-avg-kBps = <100000 0>;
3092 opp-202000000 {
3093 opp-hz = /bits/ 64 <202000000>;
3094 required-opps = <&rpmhpd_opp_svs_l1>;
3095 opp-peak-kBps = <5400000 1600000>;
3096 opp-avg-kBps = <200000 0>;
3102 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3109 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3111 power-domains = <&gcc USB30_PRIM_GDSC>;
3115 reset-names = "phy", "common";
3117 #clock-cells = <1>;
3118 #phy-cells = <1>;
3123 #address-cells = <1>;
3124 #size-cells = <0>;
3141 compatible = "qcom,sc8280xp-usb-hs-phy",
3142 "qcom,usb-snps-hs-5nm-phy";
3144 #phy-cells = <0>;
3147 clock-names = "ref";
3155 compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3162 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3164 power-domains = <&gcc USB30_SEC_GDSC>;
3168 reset-names = "phy", "common";
3170 #clock-cells = <1>;
3171 #phy-cells = <1>;
3176 #address-cells = <1>;
3177 #size-cells = <0>;
3194 compatible = "qcom,sc8280xp-dp-phy";
3202 clock-names = "aux", "cfg_ahb";
3203 power-domains = <&rpmhpd SC8280XP_MX>;
3205 #clock-cells = <1>;
3206 #phy-cells = <0>;
3212 compatible = "qcom,sc8280xp-dp-phy";
3220 clock-names = "aux", "cfg_ahb";
3221 power-domains = <&rpmhpd SC8280XP_MX>;
3223 #clock-cells = <1>;
3224 #phy-cells = <0>;
3230 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3237 operating-points-v2 = <&llcc_bwmon_opp_table>;
3239 llcc_bwmon_opp_table: opp-table {
3240 compatible = "operating-points-v2";
3242 opp-0 {
3243 opp-peak-kBps = <762000>;
3245 opp-1 {
3246 opp-peak-kBps = <1720000>;
3248 opp-2 {
3249 opp-peak-kBps = <2086000>;
3251 opp-3 {
3252 opp-peak-kBps = <2597000>;
3254 opp-4 {
3255 opp-peak-kBps = <2929000>;
3257 opp-5 {
3258 opp-peak-kBps = <3879000>;
3260 opp-6 {
3261 opp-peak-kBps = <5161000>;
3263 opp-7 {
3264 opp-peak-kBps = <5931000>;
3266 opp-8 {
3267 opp-peak-kBps = <6515000>;
3269 opp-9 {
3270 opp-peak-kBps = <7980000>;
3272 opp-10 {
3273 opp-peak-kBps = <8136000>;
3275 opp-11 {
3276 opp-peak-kBps = <10437000>;
3278 opp-12 {
3279 opp-peak-kBps = <12191000>;
3285 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3291 operating-points-v2 = <&cpu_bwmon_opp_table>;
3293 cpu_bwmon_opp_table: opp-table {
3294 compatible = "operating-points-v2";
3296 opp-0 {
3297 opp-peak-kBps = <2288000>;
3299 opp-1 {
3300 opp-peak-kBps = <4577000>;
3302 opp-2 {
3303 opp-peak-kBps = <7110000>;
3305 opp-3 {
3306 opp-peak-kBps = <9155000>;
3308 opp-4 {
3309 opp-peak-kBps = <12298000>;
3311 opp-5 {
3312 opp-peak-kBps = <14236000>;
3314 opp-6 {
3315 opp-peak-kBps = <15258001>;
3320 system-cache-controller@9200000 {
3321 compatible = "qcom,sc8280xp-llcc";
3327 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3334 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3336 #address-cells = <2>;
3337 #size-cells = <2>;
3349 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3352 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3354 assigned-clock-rates = <19200000>, <200000000>;
3356 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3360 interrupt-names = "pwr_event",
3365 power-domains = <&gcc USB30_PRIM_GDSC>;
3366 required-opps = <&rpmhpd_opp_nom>;
3372 interconnect-names = "usb-ddr", "apps-usb";
3374 wakeup-source;
3384 phy-names = "usb2-phy", "usb3-phy";
3394 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3396 #address-cells = <2>;
3397 #size-cells = <2>;
3409 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3412 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3414 assigned-clock-rates = <19200000>, <200000000>;
3416 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3420 interrupt-names = "pwr_event",
3425 power-domains = <&gcc USB30_SEC_GDSC>;
3426 required-opps = <&rpmhpd_opp_nom>;
3432 interconnect-names = "usb-ddr", "apps-usb";
3434 wakeup-source;
3444 phy-names = "usb2-phy", "usb3-phy";
3453 mdss0: display-subsystem@ae00000 {
3454 compatible = "qcom,sc8280xp-mdss";
3456 reg-names = "mdss";
3461 clock-names = "iface",
3467 interconnect-names = "mdp0-mem", "mdp1-mem";
3469 power-domains = <&dispcc0 MDSS_GDSC>;
3472 interrupt-controller;
3473 #interrupt-cells = <1>;
3474 #address-cells = <2>;
3475 #size-cells = <2>;
3480 mdss0_mdp: display-controller@ae01000 {
3481 compatible = "qcom,sc8280xp-dpu";
3484 reg-names = "mdp", "vbif";
3492 clock-names = "bus",
3498 interrupt-parent = <&mdss0>;
3500 power-domains = <&rpmhpd SC8280XP_MMCX>;
3502 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3503 assigned-clock-rates = <19200000>;
3504 operating-points-v2 = <&mdss0_mdp_opp_table>;
3507 #address-cells = <1>;
3508 #size-cells = <0>;
3513 remote-endpoint = <&mdss0_dp0_in>;
3520 remote-endpoint = <&mdss0_dp1_in>;
3527 remote-endpoint = <&mdss0_dp3_in>;
3534 remote-endpoint = <&mdss0_dp2_in>;
3539 mdss0_mdp_opp_table: opp-table {
3540 compatible = "operating-points-v2";
3542 opp-200000000 {
3543 opp-hz = /bits/ 64 <200000000>;
3544 required-opps = <&rpmhpd_opp_low_svs>;
3547 opp-300000000 {
3548 opp-hz = /bits/ 64 <300000000>;
3549 required-opps = <&rpmhpd_opp_svs>;
3552 opp-375000000 {
3553 opp-hz = /bits/ 64 <375000000>;
3554 required-opps = <&rpmhpd_opp_svs_l1>;
3557 opp-500000000 {
3558 opp-hz = /bits/ 64 <500000000>;
3559 required-opps = <&rpmhpd_opp_nom>;
3561 opp-600000000 {
3562 opp-hz = /bits/ 64 <600000000>;
3563 required-opps = <&rpmhpd_opp_turbo_l1>;
3568 mdss0_dp0: displayport-controller@ae90000 {
3569 compatible = "qcom,sc8280xp-dp";
3575 interrupt-parent = <&mdss0>;
3582 clock-names = "core_iface", "core_aux",
3587 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3589 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3593 phy-names = "dp";
3595 #sound-dai-cells = <0>;
3597 operating-points-v2 = <&mdss0_dp0_opp_table>;
3598 power-domains = <&rpmhpd SC8280XP_MMCX>;
3603 #address-cells = <1>;
3604 #size-cells = <0>;
3610 remote-endpoint = <&mdss0_intf0_out>;
3622 mdss0_dp0_opp_table: opp-table {
3623 compatible = "operating-points-v2";
3625 opp-160000000 {
3626 opp-hz = /bits/ 64 <160000000>;
3627 required-opps = <&rpmhpd_opp_low_svs>;
3630 opp-270000000 {
3631 opp-hz = /bits/ 64 <270000000>;
3632 required-opps = <&rpmhpd_opp_svs>;
3635 opp-540000000 {
3636 opp-hz = /bits/ 64 <540000000>;
3637 required-opps = <&rpmhpd_opp_svs_l1>;
3640 opp-810000000 {
3641 opp-hz = /bits/ 64 <810000000>;
3642 required-opps = <&rpmhpd_opp_nom>;
3647 mdss0_dp1: displayport-controller@ae98000 {
3648 compatible = "qcom,sc8280xp-dp";
3654 interrupt-parent = <&mdss0>;
3661 clock-names = "core_iface", "core_aux",
3665 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
3667 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3671 phy-names = "dp";
3673 #sound-dai-cells = <0>;
3675 operating-points-v2 = <&mdss0_dp1_opp_table>;
3676 power-domains = <&rpmhpd SC8280XP_MMCX>;
3681 #address-cells = <1>;
3682 #size-cells = <0>;
3688 remote-endpoint = <&mdss0_intf4_out>;
3700 mdss0_dp1_opp_table: opp-table {
3701 compatible = "operating-points-v2";
3703 opp-160000000 {
3704 opp-hz = /bits/ 64 <160000000>;
3705 required-opps = <&rpmhpd_opp_low_svs>;
3708 opp-270000000 {
3709 opp-hz = /bits/ 64 <270000000>;
3710 required-opps = <&rpmhpd_opp_svs>;
3713 opp-540000000 {
3714 opp-hz = /bits/ 64 <540000000>;
3715 required-opps = <&rpmhpd_opp_svs_l1>;
3718 opp-810000000 {
3719 opp-hz = /bits/ 64 <810000000>;
3720 required-opps = <&rpmhpd_opp_nom>;
3725 mdss0_dp2: displayport-controller@ae9a000 {
3726 compatible = "qcom,sc8280xp-dp";
3738 clock-names = "core_iface", "core_aux",
3741 interrupt-parent = <&mdss0>;
3744 phy-names = "dp";
3745 power-domains = <&rpmhpd SC8280XP_MMCX>;
3747 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
3749 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3750 operating-points-v2 = <&mdss0_dp2_opp_table>;
3752 #sound-dai-cells = <0>;
3757 #address-cells = <1>;
3758 #size-cells = <0>;
3763 remote-endpoint = <&mdss0_intf6_out>;
3772 mdss0_dp2_opp_table: opp-table {
3773 compatible = "operating-points-v2";
3775 opp-160000000 {
3776 opp-hz = /bits/ 64 <160000000>;
3777 required-opps = <&rpmhpd_opp_low_svs>;
3780 opp-270000000 {
3781 opp-hz = /bits/ 64 <270000000>;
3782 required-opps = <&rpmhpd_opp_svs>;
3785 opp-540000000 {
3786 opp-hz = /bits/ 64 <540000000>;
3787 required-opps = <&rpmhpd_opp_svs_l1>;
3790 opp-810000000 {
3791 opp-hz = /bits/ 64 <810000000>;
3792 required-opps = <&rpmhpd_opp_nom>;
3797 mdss0_dp3: displayport-controller@aea0000 {
3798 compatible = "qcom,sc8280xp-dp";
3810 clock-names = "core_iface", "core_aux",
3813 interrupt-parent = <&mdss0>;
3816 phy-names = "dp";
3817 power-domains = <&rpmhpd SC8280XP_MMCX>;
3819 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
3821 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3822 operating-points-v2 = <&mdss0_dp3_opp_table>;
3824 #sound-dai-cells = <0>;
3829 #address-cells = <1>;
3830 #size-cells = <0>;
3835 remote-endpoint = <&mdss0_intf5_out>;
3844 mdss0_dp3_opp_table: opp-table {
3845 compatible = "operating-points-v2";
3847 opp-160000000 {
3848 opp-hz = /bits/ 64 <160000000>;
3849 required-opps = <&rpmhpd_opp_low_svs>;
3852 opp-270000000 {
3853 opp-hz = /bits/ 64 <270000000>;
3854 required-opps = <&rpmhpd_opp_svs>;
3857 opp-540000000 {
3858 opp-hz = /bits/ 64 <540000000>;
3859 required-opps = <&rpmhpd_opp_svs_l1>;
3862 opp-810000000 {
3863 opp-hz = /bits/ 64 <810000000>;
3864 required-opps = <&rpmhpd_opp_nom>;
3871 compatible = "qcom,sc8280xp-dp-phy";
3879 clock-names = "aux", "cfg_ahb";
3880 power-domains = <&rpmhpd SC8280XP_MX>;
3882 #clock-cells = <1>;
3883 #phy-cells = <0>;
3889 compatible = "qcom,sc8280xp-dp-phy";
3897 clock-names = "aux", "cfg_ahb";
3898 power-domains = <&rpmhpd SC8280XP_MX>;
3900 #clock-cells = <1>;
3901 #phy-cells = <0>;
3906 dispcc0: clock-controller@af00000 {
3907 compatible = "qcom,sc8280xp-dispcc0";
3925 power-domains = <&rpmhpd SC8280XP_MMCX>;
3927 #clock-cells = <1>;
3928 #power-domain-cells = <1>;
3929 #reset-cells = <1>;
3934 pdc: interrupt-controller@b220000 {
3935 compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
3937 qcom,pdc-ranges = <0 480 40>,
3994 #interrupt-cells = <2>;
3995 interrupt-parent = <&intc>;
3996 interrupt-controller;
3999 tsens0: thermal-sensor@c263000 {
4000 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4003 #qcom,sensors = <14>;
4004 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4006 interrupt-names = "uplow", "critical";
4007 #thermal-sensor-cells = <1>;
4010 tsens1: thermal-sensor@c265000 {
4011 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4014 #qcom,sensors = <16>;
4015 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4017 interrupt-names = "uplow", "critical";
4018 #thermal-sensor-cells = <1>;
4021 aoss_qmp: power-management@c300000 {
4022 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4024 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4025 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4027 #clock-cells = <0>;
4031 compatible = "qcom,rpmh-stats";
4036 compatible = "qcom,spmi-pmic-arb";
4042 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4043 interrupt-names = "periph_irq";
4044 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4045 qcom,ee = <0>;
4046 qcom,channel = <0>;
4047 #address-cells = <2>;
4048 #size-cells = <0>;
4049 interrupt-controller;
4050 #interrupt-cells = <4>;
4054 compatible = "qcom,sc8280xp-tlmm";
4057 gpio-controller;
4058 #gpio-cells = <2>;
4059 interrupt-controller;
4060 #interrupt-cells = <2>;
4061 gpio-ranges = <&tlmm 0 0 230>;
4062 wakeup-parent = <&pdc>;
4066 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4068 #iommu-cells = <2>;
4069 #global-interrupts = <2>;
4202 intc: interrupt-controller@17a00000 {
4203 compatible = "arm,gic-v3";
4204 interrupt-controller;
4205 #interrupt-cells = <3>;
4209 #redistributor-regions = <1>;
4210 redistributor-stride = <0 0x20000>;
4212 #address-cells = <2>;
4213 #size-cells = <2>;
4216 msi-controller@17a40000 {
4217 compatible = "arm,gic-v3-its";
4219 msi-controller;
4220 #msi-cells = <1>;
4225 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
4232 compatible = "arm,armv7-timer-mem";
4234 #address-cells = <1>;
4235 #size-cells = <1>;
4239 frame-number = <0>;
4247 frame-number = <1>;
4254 frame-number = <2>;
4261 frame-number = <3>;
4268 frame-number = <4>;
4275 frame-number = <5>;
4282 frame-number = <6>;
4290 compatible = "qcom,rpmh-rsc";
4294 reg-names = "drv-0", "drv-1", "drv-2";
4298 qcom,tcs-offset = <0xd00>;
4299 qcom,drv-id = <2>;
4300 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
4303 power-domains = <&CLUSTER_PD>;
4305 apps_bcm_voter: bcm-voter {
4306 compatible = "qcom,bcm-voter";
4309 rpmhcc: clock-controller {
4310 compatible = "qcom,sc8280xp-rpmh-clk";
4311 #clock-cells = <1>;
4312 clock-names = "xo";
4316 rpmhpd: power-controller {
4317 compatible = "qcom,sc8280xp-rpmhpd";
4318 #power-domain-cells = <1>;
4319 operating-points-v2 = <&rpmhpd_opp_table>;
4321 rpmhpd_opp_table: opp-table {
4322 compatible = "operating-points-v2";
4325 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4329 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4333 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4337 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4341 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4345 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4349 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4353 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4357 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4361 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4368 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
4372 clock-names = "xo", "alternate";
4374 #interconnect-cells = <1>;
4378 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
4381 reg-names = "freq-domain0", "freq-domain1";
4384 clock-names = "xo", "alternate";
4386 #freq-domain-cells = <1>;
4387 #clock-cells = <1>;
4391 compatible = "qcom,sc8280xp-nsp0-pas";
4394 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4399 interrupt-names = "wdog", "fatal", "ready",
4400 "handover", "stop-ack";
4403 clock-names = "xo";
4405 power-domains = <&rpmhpd SC8280XP_NSP>;
4406 power-domain-names = "nsp";
4408 memory-region = <&pil_nsp0_mem>;
4410 qcom,smem-states = <&smp2p_nsp0_out 0>;
4411 qcom,smem-state-names = "stop";
4417 glink-edge {
4418 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4421 mboxes = <&ipcc IPCC_CLIENT_CDSP
4425 qcom,remote-pid = <5>;
4428 compatible = "qcom,fastrpc";
4429 qcom,glink-channels = "fastrpcglink-apps-dsp";
4431 #address-cells = <1>;
4432 #size-cells = <0>;
4434 compute-cb@1 {
4435 compatible = "qcom,fastrpc-compute-cb";
4440 compute-cb@2 {
4441 compatible = "qcom,fastrpc-compute-cb";
4446 compute-cb@3 {
4447 compatible = "qcom,fastrpc-compute-cb";
4452 compute-cb@4 {
4453 compatible = "qcom,fastrpc-compute-cb";
4458 compute-cb@5 {
4459 compatible = "qcom,fastrpc-compute-cb";
4464 compute-cb@6 {
4465 compatible = "qcom,fastrpc-compute-cb";
4470 compute-cb@7 {
4471 compatible = "qcom,fastrpc-compute-cb";
4476 compute-cb@8 {
4477 compatible = "qcom,fastrpc-compute-cb";
4482 compute-cb@9 {
4483 compatible = "qcom,fastrpc-compute-cb";
4488 compute-cb@10 {
4489 compatible = "qcom,fastrpc-compute-cb";
4494 compute-cb@11 {
4495 compatible = "qcom,fastrpc-compute-cb";
4500 compute-cb@12 {
4501 compatible = "qcom,fastrpc-compute-cb";
4506 compute-cb@13 {
4507 compatible = "qcom,fastrpc-compute-cb";
4512 compute-cb@14 {
4513 compatible = "qcom,fastrpc-compute-cb";
4522 compatible = "qcom,sc8280xp-nsp1-pas";
4525 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
4530 interrupt-names = "wdog", "fatal", "ready",
4531 "handover", "stop-ack";
4534 clock-names = "xo";
4536 power-domains = <&rpmhpd SC8280XP_NSP>;
4537 power-domain-names = "nsp";
4539 memory-region = <&pil_nsp1_mem>;
4541 qcom,smem-states = <&smp2p_nsp1_out 0>;
4542 qcom,smem-state-names = "stop";
4548 glink-edge {
4549 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
4552 mboxes = <&ipcc IPCC_CLIENT_NSP1
4556 qcom,remote-pid = <12>;
4560 mdss1: display-subsystem@22000000 {
4561 compatible = "qcom,sc8280xp-mdss";
4563 reg-names = "mdss";
4568 clock-names = "iface",
4573 interconnect-names = "mdp0-mem", "mdp1-mem";
4577 power-domains = <&dispcc1 MDSS_GDSC>;
4580 interrupt-controller;
4581 #interrupt-cells = <1>;
4582 #address-cells = <2>;
4583 #size-cells = <2>;
4588 mdss1_mdp: display-controller@22001000 {
4589 compatible = "qcom,sc8280xp-dpu";
4592 reg-names = "mdp", "vbif";
4600 clock-names = "bus",
4606 interrupt-parent = <&mdss1>;
4608 power-domains = <&rpmhpd SC8280XP_MMCX>;
4610 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
4611 assigned-clock-rates = <19200000>;
4612 operating-points-v2 = <&mdss1_mdp_opp_table>;
4615 #address-cells = <1>;
4616 #size-cells = <0>;
4621 remote-endpoint = <&mdss1_dp0_in>;
4628 remote-endpoint = <&mdss1_dp1_in>;
4635 remote-endpoint = <&mdss1_dp3_in>;
4642 remote-endpoint = <&mdss1_dp2_in>;
4647 mdss1_mdp_opp_table: opp-table {
4648 compatible = "operating-points-v2";
4650 opp-200000000 {
4651 opp-hz = /bits/ 64 <200000000>;
4652 required-opps = <&rpmhpd_opp_low_svs>;
4655 opp-300000000 {
4656 opp-hz = /bits/ 64 <300000000>;
4657 required-opps = <&rpmhpd_opp_svs>;
4660 opp-375000000 {
4661 opp-hz = /bits/ 64 <375000000>;
4662 required-opps = <&rpmhpd_opp_svs_l1>;
4665 opp-500000000 {
4666 opp-hz = /bits/ 64 <500000000>;
4667 required-opps = <&rpmhpd_opp_nom>;
4669 opp-600000000 {
4670 opp-hz = /bits/ 64 <600000000>;
4671 required-opps = <&rpmhpd_opp_turbo_l1>;
4676 mdss1_dp0: displayport-controller@22090000 {
4677 compatible = "qcom,sc8280xp-dp";
4689 clock-names = "core_iface", "core_aux",
4692 interrupt-parent = <&mdss1>;
4695 phy-names = "dp";
4696 power-domains = <&rpmhpd SC8280XP_MMCX>;
4698 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4700 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4701 operating-points-v2 = <&mdss1_dp0_opp_table>;
4703 #sound-dai-cells = <0>;
4708 #address-cells = <1>;
4709 #size-cells = <0>;
4714 remote-endpoint = <&mdss1_intf0_out>;
4723 mdss1_dp0_opp_table: opp-table {
4724 compatible = "operating-points-v2";
4726 opp-160000000 {
4727 opp-hz = /bits/ 64 <160000000>;
4728 required-opps = <&rpmhpd_opp_low_svs>;
4731 opp-270000000 {
4732 opp-hz = /bits/ 64 <270000000>;
4733 required-opps = <&rpmhpd_opp_svs>;
4736 opp-540000000 {
4737 opp-hz = /bits/ 64 <540000000>;
4738 required-opps = <&rpmhpd_opp_svs_l1>;
4741 opp-810000000 {
4742 opp-hz = /bits/ 64 <810000000>;
4743 required-opps = <&rpmhpd_opp_nom>;
4748 mdss1_dp1: displayport-controller@22098000 {
4749 compatible = "qcom,sc8280xp-dp";
4761 clock-names = "core_iface", "core_aux",
4764 interrupt-parent = <&mdss1>;
4767 phy-names = "dp";
4768 power-domains = <&rpmhpd SC8280XP_MMCX>;
4770 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4772 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4773 operating-points-v2 = <&mdss1_dp1_opp_table>;
4775 #sound-dai-cells = <0>;
4780 #address-cells = <1>;
4781 #size-cells = <0>;
4786 remote-endpoint = <&mdss1_intf4_out>;
4795 mdss1_dp1_opp_table: opp-table {
4796 compatible = "operating-points-v2";
4798 opp-160000000 {
4799 opp-hz = /bits/ 64 <160000000>;
4800 required-opps = <&rpmhpd_opp_low_svs>;
4803 opp-270000000 {
4804 opp-hz = /bits/ 64 <270000000>;
4805 required-opps = <&rpmhpd_opp_svs>;
4808 opp-540000000 {
4809 opp-hz = /bits/ 64 <540000000>;
4810 required-opps = <&rpmhpd_opp_svs_l1>;
4813 opp-810000000 {
4814 opp-hz = /bits/ 64 <810000000>;
4815 required-opps = <&rpmhpd_opp_nom>;
4820 mdss1_dp2: displayport-controller@2209a000 {
4821 compatible = "qcom,sc8280xp-dp";
4833 clock-names = "core_iface", "core_aux",
4836 interrupt-parent = <&mdss1>;
4839 phy-names = "dp";
4840 power-domains = <&rpmhpd SC8280XP_MMCX>;
4842 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4844 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4845 operating-points-v2 = <&mdss1_dp2_opp_table>;
4847 #sound-dai-cells = <0>;
4852 #address-cells = <1>;
4853 #size-cells = <0>;
4858 remote-endpoint = <&mdss1_intf6_out>;
4867 mdss1_dp2_opp_table: opp-table {
4868 compatible = "operating-points-v2";
4870 opp-160000000 {
4871 opp-hz = /bits/ 64 <160000000>;
4872 required-opps = <&rpmhpd_opp_low_svs>;
4875 opp-270000000 {
4876 opp-hz = /bits/ 64 <270000000>;
4877 required-opps = <&rpmhpd_opp_svs>;
4880 opp-540000000 {
4881 opp-hz = /bits/ 64 <540000000>;
4882 required-opps = <&rpmhpd_opp_svs_l1>;
4885 opp-810000000 {
4886 opp-hz = /bits/ 64 <810000000>;
4887 required-opps = <&rpmhpd_opp_nom>;
4892 mdss1_dp3: displayport-controller@220a0000 {
4893 compatible = "qcom,sc8280xp-dp";
4905 clock-names = "core_iface", "core_aux",
4908 interrupt-parent = <&mdss1>;
4911 phy-names = "dp";
4912 power-domains = <&rpmhpd SC8280XP_MMCX>;
4914 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4916 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4917 operating-points-v2 = <&mdss1_dp3_opp_table>;
4919 #sound-dai-cells = <0>;
4924 #address-cells = <1>;
4925 #size-cells = <0>;
4930 remote-endpoint = <&mdss1_intf5_out>;
4939 mdss1_dp3_opp_table: opp-table {
4940 compatible = "operating-points-v2";
4942 opp-160000000 {
4943 opp-hz = /bits/ 64 <160000000>;
4944 required-opps = <&rpmhpd_opp_low_svs>;
4947 opp-270000000 {
4948 opp-hz = /bits/ 64 <270000000>;
4949 required-opps = <&rpmhpd_opp_svs>;
4952 opp-540000000 {
4953 opp-hz = /bits/ 64 <540000000>;
4954 required-opps = <&rpmhpd_opp_svs_l1>;
4957 opp-810000000 {
4958 opp-hz = /bits/ 64 <810000000>;
4959 required-opps = <&rpmhpd_opp_nom>;
4966 compatible = "qcom,sc8280xp-dp-phy";
4974 clock-names = "aux", "cfg_ahb";
4975 power-domains = <&rpmhpd SC8280XP_MX>;
4977 #clock-cells = <1>;
4978 #phy-cells = <0>;
4984 compatible = "qcom,sc8280xp-dp-phy";
4992 clock-names = "aux", "cfg_ahb";
4993 power-domains = <&rpmhpd SC8280XP_MX>;
4995 #clock-cells = <1>;
4996 #phy-cells = <0>;
5001 dispcc1: clock-controller@22100000 {
5002 compatible = "qcom,sc8280xp-dispcc1";
5020 power-domains = <&rpmhpd SC8280XP_MMCX>;
5022 #clock-cells = <1>;
5023 #power-domain-cells = <1>;
5024 #reset-cells = <1>;
5030 compatible = "qcom,sc8280xp-ethqos";
5033 reg-names = "stmmaceth", "rgmii";
5039 clock-names = "stmmaceth",
5046 interrupt-names = "macirq", "eth_lpi";
5049 power-domains = <&gcc EMAC_1_GDSC>;
5053 rx-fifo-depth = <4096>;
5054 tx-fifo-depth = <4096>;
5063 thermal-zones {
5064 cpu0-thermal {
5065 polling-delay-passive = <250>;
5066 polling-delay = <1000>;
5068 thermal-sensors = <&tsens0 1>;
5071 cpu-crit {
5079 cpu1-thermal {
5080 polling-delay-passive = <250>;
5081 polling-delay = <1000>;
5083 thermal-sensors = <&tsens0 2>;
5086 cpu-crit {
5094 cpu2-thermal {
5095 polling-delay-passive = <250>;
5096 polling-delay = <1000>;
5098 thermal-sensors = <&tsens0 3>;
5101 cpu-crit {
5109 cpu3-thermal {
5110 polling-delay-passive = <250>;
5111 polling-delay = <1000>;
5113 thermal-sensors = <&tsens0 4>;
5116 cpu-crit {
5124 cpu4-thermal {
5125 polling-delay-passive = <250>;
5126 polling-delay = <1000>;
5128 thermal-sensors = <&tsens0 5>;
5131 cpu-crit {
5139 cpu5-thermal {
5140 polling-delay-passive = <250>;
5141 polling-delay = <1000>;
5143 thermal-sensors = <&tsens0 6>;
5146 cpu-crit {
5154 cpu6-thermal {
5155 polling-delay-passive = <250>;
5156 polling-delay = <1000>;
5158 thermal-sensors = <&tsens0 7>;
5161 cpu-crit {
5169 cpu7-thermal {
5170 polling-delay-passive = <250>;
5171 polling-delay = <1000>;
5173 thermal-sensors = <&tsens0 8>;
5176 cpu-crit {
5184 cluster0-thermal {
5185 polling-delay-passive = <250>;
5186 polling-delay = <1000>;
5188 thermal-sensors = <&tsens0 9>;
5191 cpu-crit {
5199 mem-thermal {
5200 polling-delay-passive = <250>;
5201 polling-delay = <1000>;
5203 thermal-sensors = <&tsens1 15>;
5206 trip-point0 {
5216 compatible = "arm,armv8-timer";