Lines Matching full:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
789 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
790 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
791 <&gcc GCC_EMAC0_PTP_CLK>,
792 <&gcc GCC_EMAC0_RGMII_CLK>;
803 power-domains = <&gcc EMAC_0_GDSC>;
813 gcc: clock-controller@100000 { label
814 compatible = "qcom,gcc-sc8280xp";
867 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
868 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
883 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
899 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
915 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
931 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
945 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
961 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
977 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
993 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1009 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1025 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1041 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1056 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1073 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1090 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1105 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1122 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1137 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1152 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1153 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1169 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1184 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1216 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1233 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1248 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1262 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1279 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1294 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1309 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1326 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1343 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1358 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1375 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1390 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1422 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1437 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1438 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1453 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1469 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1485 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1501 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1549 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1565 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1581 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1597 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1613 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1645 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1661 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1677 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1746 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1747 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1748 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1749 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1750 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1751 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1752 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1753 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1754 <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1765 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1772 resets = <&gcc GCC_PCIE_4_BCR>;
1775 power-domains = <&gcc PCIE_4_GDSC>;
1787 clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1788 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1789 <&gcc GCC_PCIE_4_CLKREF_CLK>,
1790 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1791 <&gcc GCC_PCIE_4_PIPE_CLK>,
1792 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1796 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1799 power-domains = <&gcc PCIE_4_GDSC>;
1801 resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1846 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1847 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1848 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1849 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1850 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1851 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1852 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1853 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1863 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1870 resets = <&gcc GCC_PCIE_3B_BCR>;
1873 power-domains = <&gcc PCIE_3B_GDSC>;
1885 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1886 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1887 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1888 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1889 <&gcc GCC_PCIE_3B_PIPE_CLK>,
1890 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1894 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1897 power-domains = <&gcc PCIE_3B_GDSC>;
1899 resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1944 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1945 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1946 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1947 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1948 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1949 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1950 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1951 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1961 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1968 resets = <&gcc GCC_PCIE_3A_BCR>;
1971 power-domains = <&gcc PCIE_3A_GDSC>;
1984 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1985 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1986 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1987 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1988 <&gcc GCC_PCIE_3A_PIPE_CLK>,
1989 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1993 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1996 power-domains = <&gcc PCIE_3A_GDSC>;
1998 resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2045 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2046 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2047 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2048 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2049 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2050 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2051 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2052 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2062 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2069 resets = <&gcc GCC_PCIE_2B_BCR>;
2072 power-domains = <&gcc PCIE_2B_GDSC>;
2084 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2085 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2086 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2087 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2088 <&gcc GCC_PCIE_2B_PIPE_CLK>,
2089 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2093 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2096 power-domains = <&gcc PCIE_2B_GDSC>;
2098 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2143 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2144 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2145 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2146 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2147 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2148 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2149 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2150 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2160 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2167 resets = <&gcc GCC_PCIE_2A_BCR>;
2170 power-domains = <&gcc PCIE_2A_GDSC>;
2183 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2184 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2185 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2186 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2187 <&gcc GCC_PCIE_2A_PIPE_CLK>,
2188 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2192 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2195 power-domains = <&gcc PCIE_2A_GDSC>;
2197 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2219 resets = <&gcc GCC_UFS_PHY_BCR>;
2222 power-domains = <&gcc UFS_PHY_GDSC>;
2228 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2229 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2230 <&gcc GCC_UFS_PHY_AHB_CLK>,
2231 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2232 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2233 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2234 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2235 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2259 clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2260 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2263 power-domains = <&gcc UFS_PHY_GDSC>;
2282 resets = <&gcc GCC_UFS_CARD_BCR>;
2285 power-domains = <&gcc UFS_CARD_GDSC>;
2290 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2291 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2292 <&gcc GCC_UFS_CARD_AHB_CLK>,
2293 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2294 <&gcc GCC_UFS_REF_CLKREF_CLK>,
2295 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2296 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2297 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2321 clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2322 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2325 power-domains = <&gcc UFS_CARD_GDSC>;
2430 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2431 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2468 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2469 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2501 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2502 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2526 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2537 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2539 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2550 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2552 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2563 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2565 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2576 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2578 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2589 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2590 <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2591 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2592 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2595 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2596 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2599 power-domains = <&gcc USB30_MP_GDSC>;
2613 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2614 <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2615 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2616 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2619 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2620 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2623 power-domains = <&gcc USB30_MP_GDSC>;
3066 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3067 <&gcc GCC_SDCC2_APPS_CLK>,
3070 resets = <&gcc GCC_SDCC2_BCR>;
3105 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3106 <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3107 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3108 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3111 power-domains = <&gcc USB30_PRIM_GDSC>;
3113 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3114 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3149 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3158 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3159 <&gcc GCC_USB4_CLKREF_CLK>,
3160 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3161 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3164 power-domains = <&gcc USB30_SEC_GDSC>;
3166 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3167 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3340 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3341 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3342 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3343 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3344 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3345 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3346 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3347 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3348 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3352 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3353 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3365 power-domains = <&gcc USB30_PRIM_GDSC>;
3368 resets = <&gcc GCC_USB30_PRIM_BCR>;
3400 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3401 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3402 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3403 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3404 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3405 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3406 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3407 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3408 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3412 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3413 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3425 power-domains = <&gcc USB30_SEC_GDSC>;
3428 resets = <&gcc GCC_USB30_SEC_BCR>;
3458 clocks = <&gcc GCC_DISP_AHB_CLK>,
3486 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3487 <&gcc GCC_DISP_SF_AXI_CLK>,
3910 clocks = <&gcc GCC_DISP_AHB_CLK>,
4371 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4383 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4565 clocks = <&gcc GCC_DISP_AHB_CLK>,
4594 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4595 <&gcc GCC_DISP_SF_AXI_CLK>,
5005 clocks = <&gcc GCC_DISP_AHB_CLK>,
5035 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5036 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5037 <&gcc GCC_EMAC1_PTP_CLK>,
5038 <&gcc GCC_EMAC1_RGMII_CLK>;
5049 power-domains = <&gcc EMAC_1_GDSC>;