Lines Matching refs:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
772 gcc: clock-controller@100000 { label
773 compatible = "qcom,gcc-sc8180x";
789 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
790 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
801 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
816 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
842 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
898 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
912 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
924 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1006 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1047 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1062 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1076 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1088 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1103 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1117 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1130 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1131 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1171 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1198 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1212 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1224 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1239 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1265 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1280 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1294 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1321 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1335 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1347 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1376 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1389 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1390 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1401 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1416 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1430 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1442 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1457 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1471 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1483 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1498 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1512 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1524 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1539 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1553 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1565 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1580 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1594 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1606 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1621 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1635 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1719 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1720 <&gcc GCC_PCIE_0_AUX_CLK>,
1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1722 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1723 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1724 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1725 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1726 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1736 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1743 resets = <&gcc GCC_PCIE_0_BCR>;
1746 power-domains = <&gcc PCIE_0_GDSC>;
1764 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1765 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1766 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1767 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1770 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1773 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1785 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1826 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1827 <&gcc GCC_PCIE_3_AUX_CLK>,
1828 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1829 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1830 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1831 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1832 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1833 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1843 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1850 resets = <&gcc GCC_PCIE_3_BCR>;
1853 power-domains = <&gcc PCIE_3_GDSC>;
1871 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1872 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1873 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1874 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1877 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1880 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1892 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
1933 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1934 <&gcc GCC_PCIE_1_AUX_CLK>,
1935 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1936 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1937 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1938 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1939 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1940 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1950 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1957 resets = <&gcc GCC_PCIE_1_BCR>;
1960 power-domains = <&gcc PCIE_1_GDSC>;
1978 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1979 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1981 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1984 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1987 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1999 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2040 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2041 <&gcc GCC_PCIE_2_AUX_CLK>,
2042 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2043 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2044 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2045 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2046 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2057 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2064 resets = <&gcc GCC_PCIE_2_BCR>;
2067 power-domains = <&gcc PCIE_2_GDSC>;
2085 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2086 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2087 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2088 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2091 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2094 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2106 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2125 resets = <&gcc GCC_UFS_PHY_BCR>;
2130 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2131 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2132 <&gcc GCC_UFS_PHY_AHB_CLK>,
2133 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2135 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2136 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2137 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2165 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2272 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2273 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2303 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2304 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2329 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2330 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2423 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2436 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2449 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2451 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2452 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2457 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2458 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2493 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2515 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2517 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2518 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2523 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2524 <&gcc GCC_USB3_PHY_SEC_BCR>;
2559 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2606 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2607 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2608 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2609 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2610 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2611 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2618 resets = <&gcc GCC_USB30_PRIM_BCR>;
2619 power-domains = <&gcc USB30_PRIM_GDSC>;
2625 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2626 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2657 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2658 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2659 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2660 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2661 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2662 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2669 resets = <&gcc GCC_USB30_SEC_BCR>;
2670 power-domains = <&gcc USB30_SEC_GDSC>;
2678 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2679 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2718 <&gcc GCC_DISP_HF_AXI_CLK>,
2719 <&gcc GCC_DISP_SF_AXI_CLK>,
2751 <&gcc GCC_DISP_HF_AXI_CLK>,
2848 <&gcc GCC_DISP_HF_AXI_CLK>;
2934 <&gcc GCC_DISP_HF_AXI_CLK>;
3619 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3654 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;