Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interconnect/qcom,sc8180x.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
21 #address-cells = <2>;
22 #size-cells = <2>;
25 xo_board_clk: xo-board {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <38400000>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <32764>;
35 clock-output-names = "sleep_clk";
40 #address-cells = <2>;
41 #size-cells = <0>;
47 enable-method = "psci";
48 capacity-dmips-mhz = <602>;
49 next-level-cache = <&L2_0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
51 operating-points-v2 = <&cpu0_opp_table>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
56 #cooling-cells = <2>;
59 L2_0: l2-cache {
61 cache-level = <2>;
62 cache-unified;
63 next-level-cache = <&L3_0>;
64 L3_0: l3-cache {
66 cache-level = <3>;
67 cache-unified;
76 enable-method = "psci";
77 capacity-dmips-mhz = <602>;
78 next-level-cache = <&L2_100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 operating-points-v2 = <&cpu0_opp_table>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
85 #cooling-cells = <2>;
88 L2_100: l2-cache {
90 cache-level = <2>;
91 cache-unified;
92 next-level-cache = <&L3_0>;
101 enable-method = "psci";
102 capacity-dmips-mhz = <602>;
103 next-level-cache = <&L2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 operating-points-v2 = <&cpu0_opp_table>;
108 power-domains = <&CPU_PD2>;
109 power-domain-names = "psci";
110 #cooling-cells = <2>;
113 L2_200: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&L3_0>;
125 enable-method = "psci";
126 capacity-dmips-mhz = <602>;
127 next-level-cache = <&L2_300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 operating-points-v2 = <&cpu0_opp_table>;
132 power-domains = <&CPU_PD3>;
133 power-domain-names = "psci";
134 #cooling-cells = <2>;
137 L2_300: l2-cache {
139 cache-unified;
140 cache-level = <2>;
141 next-level-cache = <&L3_0>;
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 operating-points-v2 = <&cpu4_opp_table>;
156 power-domains = <&CPU_PD4>;
157 power-domain-names = "psci";
158 #cooling-cells = <2>;
161 L2_400: l2-cache {
163 cache-unified;
164 cache-level = <2>;
165 next-level-cache = <&L3_0>;
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
175 next-level-cache = <&L2_500>;
176 qcom,freq-domain = <&cpufreq_hw 1>;
177 operating-points-v2 = <&cpu4_opp_table>;
180 power-domains = <&CPU_PD5>;
181 power-domain-names = "psci";
182 #cooling-cells = <2>;
185 L2_500: l2-cache {
187 cache-unified;
188 cache-level = <2>;
189 next-level-cache = <&L3_0>;
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 next-level-cache = <&L2_600>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu4_opp_table>;
204 power-domains = <&CPU_PD6>;
205 power-domain-names = "psci";
206 #cooling-cells = <2>;
209 L2_600: l2-cache {
211 cache-unified;
212 cache-level = <2>;
213 next-level-cache = <&L3_0>;
221 enable-method = "psci";
222 capacity-dmips-mhz = <1024>;
223 next-level-cache = <&L2_700>;
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
228 power-domains = <&CPU_PD7>;
229 power-domain-names = "psci";
230 #cooling-cells = <2>;
233 L2_700: l2-cache {
235 cache-unified;
236 cache-level = <2>;
237 next-level-cache = <&L3_0>;
241 cpu-map {
277 idle-states {
278 entry-method = "psci";
280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
281 compatible = "arm,idle-state";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <355>;
284 exit-latency-us = <909>;
285 min-residency-us = <3934>;
286 local-timer-stop;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 arm,psci-suspend-param = <0x40000004>;
292 entry-latency-us = <241>;
293 exit-latency-us = <1461>;
294 min-residency-us = <4488>;
295 local-timer-stop;
299 domain-idle-states {
300 CLUSTER_SLEEP_0: cluster-sleep-0 {
301 compatible = "domain-idle-state";
302 arm,psci-suspend-param = <0x4100a344>;
303 entry-latency-us = <3263>;
304 exit-latency-us = <6562>;
305 min-residency-us = <9987>;
310 cpu0_opp_table: opp-table-cpu0 {
311 compatible = "operating-points-v2";
312 opp-shared;
314 opp-300000000 {
315 opp-hz = /bits/ 64 <300000000>;
316 opp-peak-kBps = <800000 9600000>;
319 opp-422400000 {
320 opp-hz = /bits/ 64 <422400000>;
321 opp-peak-kBps = <800000 9600000>;
324 opp-537600000 {
325 opp-hz = /bits/ 64 <537600000>;
326 opp-peak-kBps = <800000 12902400>;
329 opp-652800000 {
330 opp-hz = /bits/ 64 <652800000>;
331 opp-peak-kBps = <800000 12902400>;
334 opp-768000000 {
335 opp-hz = /bits/ 64 <768000000>;
336 opp-peak-kBps = <800000 15974400>;
339 opp-883200000 {
340 opp-hz = /bits/ 64 <883200000>;
341 opp-peak-kBps = <1804000 19660800>;
344 opp-998400000 {
345 opp-hz = /bits/ 64 <998400000>;
346 opp-peak-kBps = <1804000 19660800>;
349 opp-1113600000 {
350 opp-hz = /bits/ 64 <1113600000>;
351 opp-peak-kBps = <1804000 22732800>;
354 opp-1228800000 {
355 opp-hz = /bits/ 64 <1228800000>;
356 opp-peak-kBps = <1804000 22732800>;
359 opp-1363200000 {
360 opp-hz = /bits/ 64 <1363200000>;
361 opp-peak-kBps = <2188000 25804800>;
364 opp-1478400000 {
365 opp-hz = /bits/ 64 <1478400000>;
366 opp-peak-kBps = <2188000 31948800>;
369 opp-1574400000 {
370 opp-hz = /bits/ 64 <1574400000>;
371 opp-peak-kBps = <3072000 31948800>;
374 opp-1670400000 {
375 opp-hz = /bits/ 64 <1670400000>;
376 opp-peak-kBps = <3072000 31948800>;
379 opp-1766400000 {
380 opp-hz = /bits/ 64 <1766400000>;
381 opp-peak-kBps = <3072000 31948800>;
385 cpu4_opp_table: opp-table-cpu4 {
386 compatible = "operating-points-v2";
387 opp-shared;
389 opp-825600000 {
390 opp-hz = /bits/ 64 <825600000>;
391 opp-peak-kBps = <1804000 15974400>;
394 opp-940800000 {
395 opp-hz = /bits/ 64 <940800000>;
396 opp-peak-kBps = <2188000 19660800>;
399 opp-1056000000 {
400 opp-hz = /bits/ 64 <1056000000>;
401 opp-peak-kBps = <2188000 22732800>;
404 opp-1171200000 {
405 opp-hz = /bits/ 64 <1171200000>;
406 opp-peak-kBps = <3072000 25804800>;
409 opp-1286400000 {
410 opp-hz = /bits/ 64 <1286400000>;
411 opp-peak-kBps = <3072000 31948800>;
414 opp-1420800000 {
415 opp-hz = /bits/ 64 <1420800000>;
416 opp-peak-kBps = <4068000 31948800>;
419 opp-1536000000 {
420 opp-hz = /bits/ 64 <1536000000>;
421 opp-peak-kBps = <4068000 31948800>;
424 opp-1651200000 {
425 opp-hz = /bits/ 64 <1651200000>;
426 opp-peak-kBps = <4068000 40550400>;
429 opp-1766400000 {
430 opp-hz = /bits/ 64 <1766400000>;
431 opp-peak-kBps = <4068000 40550400>;
434 opp-1881600000 {
435 opp-hz = /bits/ 64 <1881600000>;
436 opp-peak-kBps = <4068000 43008000>;
439 opp-1996800000 {
440 opp-hz = /bits/ 64 <1996800000>;
441 opp-peak-kBps = <6220000 43008000>;
444 opp-2131200000 {
445 opp-hz = /bits/ 64 <2131200000>;
446 opp-peak-kBps = <6220000 49152000>;
449 opp-2246400000 {
450 opp-hz = /bits/ 64 <2246400000>;
451 opp-peak-kBps = <7216000 49152000>;
454 opp-2361600000 {
455 opp-hz = /bits/ 64 <2361600000>;
456 opp-peak-kBps = <8368000 49152000>;
459 opp-2457600000 {
460 opp-hz = /bits/ 64 <2457600000>;
461 opp-peak-kBps = <8368000 51609600>;
464 opp-2553600000 {
465 opp-hz = /bits/ 64 <2553600000>;
466 opp-peak-kBps = <8368000 51609600>;
469 opp-2649600000 {
470 opp-hz = /bits/ 64 <2649600000>;
471 opp-peak-kBps = <8368000 51609600>;
474 opp-2745600000 {
475 opp-hz = /bits/ 64 <2745600000>;
476 opp-peak-kBps = <8368000 51609600>;
479 opp-2841600000 {
480 opp-hz = /bits/ 64 <2841600000>;
481 opp-peak-kBps = <8368000 51609600>;
484 opp-2918400000 {
485 opp-hz = /bits/ 64 <2918400000>;
486 opp-peak-kBps = <8368000 51609600>;
489 opp-2995200000 {
490 opp-hz = /bits/ 64 <2995200000>;
491 opp-peak-kBps = <8368000 51609600>;
497 compatible = "qcom,scm-sc8180x", "qcom,scm";
501 camnoc_virt: interconnect-camnoc-virt {
502 compatible = "qcom,sc8180x-camnoc-virt";
503 #interconnect-cells = <2>;
504 qcom,bcm-voters = <&apps_bcm_voter>;
507 mc_virt: interconnect-mc-virt {
508 compatible = "qcom,sc8180x-mc-virt";
509 #interconnect-cells = <2>;
510 qcom,bcm-voters = <&apps_bcm_voter>;
513 qup_virt: interconnect-qup-virt {
514 compatible = "qcom,sc8180x-qup-virt";
515 #interconnect-cells = <2>;
516 qcom,bcm-voters = <&apps_bcm_voter>;
526 compatible = "arm,armv8-pmuv3";
531 compatible = "arm,psci-1.0";
534 CPU_PD0: power-domain-cpu0 {
535 #power-domain-cells = <0>;
536 power-domains = <&CLUSTER_PD>;
537 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
540 CPU_PD1: power-domain-cpu1 {
541 #power-domain-cells = <0>;
542 power-domains = <&CLUSTER_PD>;
543 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
546 CPU_PD2: power-domain-cpu2 {
547 #power-domain-cells = <0>;
548 power-domains = <&CLUSTER_PD>;
549 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
552 CPU_PD3: power-domain-cpu3 {
553 #power-domain-cells = <0>;
554 power-domains = <&CLUSTER_PD>;
555 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
558 CPU_PD4: power-domain-cpu4 {
559 #power-domain-cells = <0>;
560 power-domains = <&CLUSTER_PD>;
561 domain-idle-states = <&BIG_CPU_SLEEP_0>;
564 CPU_PD5: power-domain-cpu5 {
565 #power-domain-cells = <0>;
566 power-domains = <&CLUSTER_PD>;
567 domain-idle-states = <&BIG_CPU_SLEEP_0>;
570 CPU_PD6: power-domain-cpu6 {
571 #power-domain-cells = <0>;
572 power-domains = <&CLUSTER_PD>;
573 domain-idle-states = <&BIG_CPU_SLEEP_0>;
576 CPU_PD7: power-domain-cpu7 {
577 #power-domain-cells = <0>;
578 power-domains = <&CLUSTER_PD>;
579 domain-idle-states = <&BIG_CPU_SLEEP_0>;
582 CLUSTER_PD: power-domain-cpu-cluster0 {
583 #power-domain-cells = <0>;
584 domain-idle-states = <&CLUSTER_SLEEP_0>;
588 reserved-memory {
589 #address-cells = <2>;
590 #size-cells = <2>;
595 no-map;
600 no-map;
605 no-map;
608 aop_cmd_db: cmd-db@85f20000 {
609 compatible = "qcom,cmd-db";
611 no-map;
616 no-map;
622 no-map;
628 no-map;
633 no-map;
638 no-map;
643 no-map;
648 no-map;
652 smp2p-cdsp {
660 qcom,local-pid = <0>;
661 qcom,remote-pid = <5>;
663 cdsp_smp2p_out: master-kernel {
664 qcom,entry-name = "master-kernel";
665 #qcom,smem-state-cells = <1>;
668 cdsp_smp2p_in: slave-kernel {
669 qcom,entry-name = "slave-kernel";
671 interrupt-controller;
672 #interrupt-cells = <2>;
676 smp2p-lpass {
684 qcom,local-pid = <0>;
685 qcom,remote-pid = <2>;
687 adsp_smp2p_out: master-kernel {
688 qcom,entry-name = "master-kernel";
689 #qcom,smem-state-cells = <1>;
692 adsp_smp2p_in: slave-kernel {
693 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
700 smp2p-mpss {
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <1>;
711 modem_smp2p_out: master-kernel {
712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells = <1>;
716 modem_smp2p_in: slave-kernel {
717 qcom,entry-name = "slave-kernel";
719 interrupt-controller;
720 #interrupt-cells = <2>;
723 modem_smp2p_ipa_out: ipa-ap-to-modem {
724 qcom,entry-name = "ipa";
725 #qcom,smem-state-cells = <1>;
728 modem_smp2p_ipa_in: ipa-modem-to-ap {
729 qcom,entry-name = "ipa";
730 interrupt-controller;
731 #interrupt-cells = <2>;
734 modem_smp2p_wlan_in: wlan-wpss-to-ap {
735 qcom,entry-name = "wlan";
736 interrupt-controller;
737 #interrupt-cells = <2>;
741 smp2p-slpi {
749 qcom,local-pid = <0>;
750 qcom,remote-pid = <3>;
752 slpi_smp2p_out: master-kernel {
753 qcom,entry-name = "master-kernel";
754 #qcom,smem-state-cells = <1>;
757 slpi_smp2p_in: slave-kernel {
758 qcom,entry-name = "slave-kernel";
760 interrupt-controller;
761 #interrupt-cells = <2>;
766 compatible = "simple-bus";
767 #address-cells = <2>;
768 #size-cells = <2>;
770 dma-ranges = <0 0 0 0 0x10 0>;
772 gcc: clock-controller@100000 {
773 compatible = "qcom,gcc-sc8180x";
775 #clock-cells = <1>;
776 #reset-cells = <1>;
777 #power-domain-cells = <1>;
781 clock-names = "bi_tcxo",
787 compatible = "qcom,geni-se-qup";
791 clock-names = "m-ahb", "s-ahb";
792 #address-cells = <2>;
793 #size-cells = <2>;
799 compatible = "qcom,geni-i2c";
802 clock-names = "se";
807 interconnect-names = "qup-core", "qup-config", "qup-memory";
808 #address-cells = <1>;
809 #size-cells = <0>;
814 compatible = "qcom,geni-spi";
817 clock-names = "se";
821 interconnect-names = "qup-core", "qup-config";
822 #address-cells = <1>;
823 #size-cells = <0>;
828 compatible = "qcom,geni-uart";
831 clock-names = "se";
835 interconnect-names = "qup-core", "qup-config";
840 compatible = "qcom,geni-i2c";
843 clock-names = "se";
848 interconnect-names = "qup-core", "qup-config", "qup-memory";
849 #address-cells = <1>;
850 #size-cells = <0>;
855 compatible = "qcom,geni-spi";
858 clock-names = "se";
862 interconnect-names = "qup-core", "qup-config";
863 #address-cells = <1>;
864 #size-cells = <0>;
869 compatible = "qcom,geni-uart";
872 clock-names = "se";
876 interconnect-names = "qup-core", "qup-config";
881 compatible = "qcom,geni-i2c";
884 clock-names = "se";
889 interconnect-names = "qup-core", "qup-config", "qup-memory";
890 #address-cells = <1>;
891 #size-cells = <0>;
896 compatible = "qcom,geni-spi";
899 clock-names = "se";
903 interconnect-names = "qup-core", "qup-config";
904 #address-cells = <1>;
905 #size-cells = <0>;
910 compatible = "qcom,geni-uart";
913 clock-names = "se";
917 interconnect-names = "qup-core", "qup-config";
922 compatible = "qcom,geni-i2c";
925 clock-names = "se";
930 interconnect-names = "qup-core", "qup-config", "qup-memory";
931 #address-cells = <1>;
932 #size-cells = <0>;
937 compatible = "qcom,geni-spi";
940 clock-names = "se";
944 interconnect-names = "qup-core", "qup-config";
945 #address-cells = <1>;
946 #size-cells = <0>;
951 compatible = "qcom,geni-uart";
954 clock-names = "se";
958 interconnect-names = "qup-core", "qup-config";
963 compatible = "qcom,geni-i2c";
966 clock-names = "se";
971 interconnect-names = "qup-core", "qup-config", "qup-memory";
972 #address-cells = <1>;
973 #size-cells = <0>;
978 compatible = "qcom,geni-spi";
981 clock-names = "se";
985 interconnect-names = "qup-core", "qup-config";
986 #address-cells = <1>;
987 #size-cells = <0>;
992 compatible = "qcom,geni-uart";
995 clock-names = "se";
999 interconnect-names = "qup-core", "qup-config";
1004 compatible = "qcom,geni-i2c";
1007 clock-names = "se";
1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1013 #address-cells = <1>;
1014 #size-cells = <0>;
1019 compatible = "qcom,geni-spi";
1022 clock-names = "se";
1026 interconnect-names = "qup-core", "qup-config";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1033 compatible = "qcom,geni-uart";
1036 clock-names = "se";
1040 interconnect-names = "qup-core", "qup-config";
1045 compatible = "qcom,geni-i2c";
1048 clock-names = "se";
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1060 compatible = "qcom,geni-spi";
1063 clock-names = "se";
1067 interconnect-names = "qup-core", "qup-config";
1068 #address-cells = <1>;
1069 #size-cells = <0>;
1074 compatible = "qcom,geni-uart";
1077 clock-names = "se";
1081 interconnect-names = "qup-core", "qup-config";
1086 compatible = "qcom,geni-i2c";
1089 clock-names = "se";
1094 interconnect-names = "qup-core", "qup-config", "qup-memory";
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1101 compatible = "qcom,geni-spi";
1104 clock-names = "se";
1108 interconnect-names = "qup-core", "qup-config";
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1115 compatible = "qcom,geni-uart";
1118 clock-names = "se";
1122 interconnect-names = "qup-core", "qup-config";
1128 compatible = "qcom,geni-se-qup";
1132 clock-names = "m-ahb", "s-ahb";
1133 #address-cells = <2>;
1134 #size-cells = <2>;
1140 compatible = "qcom,geni-i2c";
1143 clock-names = "se";
1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 #address-cells = <1>;
1150 #size-cells = <0>;
1155 compatible = "qcom,geni-spi";
1158 clock-names = "se";
1162 interconnect-names = "qup-core", "qup-config";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1169 compatible = "qcom,geni-uart";
1172 clock-names = "se";
1176 interconnect-names = "qup-core", "qup-config";
1181 compatible = "qcom,geni-i2c";
1184 clock-names = "se";
1189 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1196 compatible = "qcom,geni-spi";
1199 clock-names = "se";
1203 interconnect-names = "qup-core", "qup-config";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1210 compatible = "qcom,geni-debug-uart";
1213 clock-names = "se";
1217 interconnect-names = "qup-core", "qup-config";
1222 compatible = "qcom,geni-i2c";
1225 clock-names = "se";
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1237 compatible = "qcom,geni-spi";
1240 clock-names = "se";
1244 interconnect-names = "qup-core", "qup-config";
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1251 compatible = "qcom,geni-uart";
1254 clock-names = "se";
1258 interconnect-names = "qup-core", "qup-config";
1263 compatible = "qcom,geni-i2c";
1266 clock-names = "se";
1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "qcom,geni-spi";
1281 clock-names = "se";
1285 interconnect-names = "qup-core", "qup-config";
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 compatible = "qcom,geni-uart";
1295 clock-names = "se";
1299 interconnect-names = "qup-core", "qup-config";
1304 compatible = "qcom,geni-i2c";
1307 clock-names = "se";
1312 interconnect-names = "qup-core", "qup-config", "qup-memory";
1313 #address-cells = <1>;
1314 #size-cells = <0>;
1319 compatible = "qcom,geni-spi";
1322 clock-names = "se";
1326 interconnect-names = "qup-core", "qup-config";
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1333 compatible = "qcom,geni-uart";
1336 clock-names = "se";
1340 interconnect-names = "qup-core", "qup-config";
1345 compatible = "qcom,geni-i2c";
1348 clock-names = "se";
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 #address-cells = <1>;
1355 #size-cells = <0>;
1360 compatible = "qcom,geni-spi";
1363 clock-names = "se";
1367 interconnect-names = "qup-core", "qup-config";
1368 #address-cells = <1>;
1369 #size-cells = <0>;
1374 compatible = "qcom,geni-uart";
1377 clock-names = "se";
1381 interconnect-names = "qup-core", "qup-config";
1387 compatible = "qcom,geni-se-qup";
1391 clock-names = "m-ahb", "s-ahb";
1392 #address-cells = <2>;
1393 #size-cells = <2>;
1399 compatible = "qcom,geni-i2c";
1402 clock-names = "se";
1407 interconnect-names = "qup-core", "qup-config", "qup-memory";
1408 #address-cells = <1>;
1409 #size-cells = <0>;
1414 compatible = "qcom,geni-spi";
1417 clock-names = "se";
1421 interconnect-names = "qup-core", "qup-config";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1428 compatible = "qcom,geni-uart";
1431 clock-names = "se";
1435 interconnect-names = "qup-core", "qup-config";
1440 compatible = "qcom,geni-i2c";
1443 clock-names = "se";
1448 interconnect-names = "qup-core", "qup-config", "qup-memory";
1449 #address-cells = <1>;
1450 #size-cells = <0>;
1455 compatible = "qcom,geni-spi";
1458 clock-names = "se";
1462 interconnect-names = "qup-core", "qup-config";
1463 #address-cells = <1>;
1464 #size-cells = <0>;
1469 compatible = "qcom,geni-uart";
1472 clock-names = "se";
1476 interconnect-names = "qup-core", "qup-config";
1481 compatible = "qcom,geni-i2c";
1484 clock-names = "se";
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1490 #address-cells = <1>;
1491 #size-cells = <0>;
1496 compatible = "qcom,geni-spi";
1499 clock-names = "se";
1503 interconnect-names = "qup-core", "qup-config";
1504 #address-cells = <1>;
1505 #size-cells = <0>;
1510 compatible = "qcom,geni-uart";
1513 clock-names = "se";
1517 interconnect-names = "qup-core", "qup-config";
1522 compatible = "qcom,geni-i2c";
1525 clock-names = "se";
1530 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1537 compatible = "qcom,geni-spi";
1540 clock-names = "se";
1544 interconnect-names = "qup-core", "qup-config";
1545 #address-cells = <1>;
1546 #size-cells = <0>;
1551 compatible = "qcom,geni-uart";
1554 clock-names = "se";
1558 interconnect-names = "qup-core", "qup-config";
1563 compatible = "qcom,geni-i2c";
1566 clock-names = "se";
1571 interconnect-names = "qup-core", "qup-config", "qup-memory";
1572 #address-cells = <1>;
1573 #size-cells = <0>;
1578 compatible = "qcom,geni-spi";
1581 clock-names = "se";
1585 interconnect-names = "qup-core", "qup-config";
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1592 compatible = "qcom,geni-uart";
1595 clock-names = "se";
1599 interconnect-names = "qup-core", "qup-config";
1604 compatible = "qcom,geni-i2c";
1607 clock-names = "se";
1612 interconnect-names = "qup-core", "qup-config", "qup-memory";
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1619 compatible = "qcom,geni-spi";
1622 clock-names = "se";
1626 interconnect-names = "qup-core", "qup-config";
1627 #address-cells = <1>;
1628 #size-cells = <0>;
1633 compatible = "qcom,geni-uart";
1636 clock-names = "se";
1640 interconnect-names = "qup-core", "qup-config";
1646 compatible = "qcom,sc8180x-config-noc";
1648 #interconnect-cells = <2>;
1649 qcom,bcm-voters = <&apps_bcm_voter>;
1653 compatible = "qcom,sc8180x-system-noc";
1655 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1660 compatible = "qcom,sc8180x-aggre1-noc";
1662 #interconnect-cells = <2>;
1663 qcom,bcm-voters = <&apps_bcm_voter>;
1667 compatible = "qcom,sc8180x-aggre2-noc";
1669 #interconnect-cells = <2>;
1670 qcom,bcm-voters = <&apps_bcm_voter>;
1674 compatible = "qcom,sc8180x-compute-noc";
1676 #interconnect-cells = <2>;
1677 qcom,bcm-voters = <&apps_bcm_voter>;
1681 compatible = "qcom,sc8180x-mmss-noc";
1683 #interconnect-cells = <2>;
1684 qcom,bcm-voters = <&apps_bcm_voter>;
1688 compatible = "qcom,pcie-sc8180x";
1694 reg-names = "parf",
1700 linux,pci-domain = <0>;
1701 bus-range = <0x00 0xff>;
1702 num-lanes = <2>;
1704 #address-cells = <3>;
1705 #size-cells = <2>;
1711 interrupt-names = "msi";
1712 #interrupt-cells = <1>;
1713 interrupt-map-mask = <0 0 0 0x7>;
1714 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1727 clock-names = "pipe",
1736 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1737 assigned-clock-rates = <19200000>;
1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1744 reset-names = "pci";
1746 power-domains = <&gcc PCIE_0_GDSC>;
1750 interconnect-names = "pcie-mem", "cpu-pcie";
1753 phy-names = "pciephy";
1758 pcie0_phy: phy-wrapper@1c06000 {
1759 compatible = "qcom,sc8180x-qmp-pcie-phy";
1761 #address-cells = <2>;
1762 #size-cells = <2>;
1768 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1771 reset-names = "phy";
1773 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1774 assigned-clock-rates = <100000000>;
1786 clock-names = "pipe0";
1788 #clock-cells = <0>;
1789 clock-output-names = "pcie_0_pipe_clk";
1790 #phy-cells = <0>;
1795 compatible = "qcom,pcie-sc8180x";
1801 reg-names = "parf",
1807 linux,pci-domain = <3>;
1808 bus-range = <0x00 0xff>;
1809 num-lanes = <2>;
1811 #address-cells = <3>;
1812 #size-cells = <2>;
1818 interrupt-names = "msi";
1819 #interrupt-cells = <1>;
1820 interrupt-map-mask = <0 0 0 0x7>;
1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1834 clock-names = "pipe",
1843 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1844 assigned-clock-rates = <19200000>;
1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1851 reset-names = "pci";
1853 power-domains = <&gcc PCIE_3_GDSC>;
1857 interconnect-names = "pcie-mem", "cpu-pcie";
1860 phy-names = "pciephy";
1865 pcie3_phy: phy-wrapper@1c0c000 {
1866 compatible = "qcom,sc8180x-qmp-pcie-phy";
1868 #address-cells = <2>;
1869 #size-cells = <2>;
1875 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1878 reset-names = "phy";
1880 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1881 assigned-clock-rates = <100000000>;
1893 clock-names = "pipe0";
1895 #clock-cells = <0>;
1896 clock-output-names = "pcie_3_pipe_clk";
1897 #phy-cells = <0>;
1902 compatible = "qcom,pcie-sc8180x";
1908 reg-names = "parf",
1914 linux,pci-domain = <1>;
1915 bus-range = <0x00 0xff>;
1916 num-lanes = <2>;
1918 #address-cells = <3>;
1919 #size-cells = <2>;
1925 interrupt-names = "msi";
1926 #interrupt-cells = <1>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1941 clock-names = "pipe",
1950 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1951 assigned-clock-rates = <19200000>;
1954 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1958 reset-names = "pci";
1960 power-domains = <&gcc PCIE_1_GDSC>;
1964 interconnect-names = "pcie-mem", "cpu-pcie";
1967 phy-names = "pciephy";
1972 pcie1_phy: phy-wrapper@1c16000 {
1973 compatible = "qcom,sc8180x-qmp-pcie-phy";
1975 #address-cells = <2>;
1976 #size-cells = <2>;
1982 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1985 reset-names = "phy";
1987 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1988 assigned-clock-rates = <100000000>;
2000 clock-names = "pipe0";
2001 #clock-cells = <0>;
2002 clock-output-names = "pcie_1_pipe_clk";
2004 #phy-cells = <0>;
2009 compatible = "qcom,pcie-sc8180x";
2015 reg-names = "parf",
2021 linux,pci-domain = <2>;
2022 bus-range = <0x00 0xff>;
2023 num-lanes = <4>;
2025 #address-cells = <3>;
2026 #size-cells = <2>;
2032 interrupt-names = "msi";
2033 #interrupt-cells = <1>;
2034 interrupt-map-mask = <0 0 0 0x7>;
2035 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2048 clock-names = "pipe",
2057 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2058 assigned-clock-rates = <19200000>;
2061 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2065 reset-names = "pci";
2067 power-domains = <&gcc PCIE_2_GDSC>;
2071 interconnect-names = "pcie-mem", "cpu-pcie";
2074 phy-names = "pciephy";
2079 pcie2_phy: phy-wrapper@1c1c000 {
2080 compatible = "qcom,sc8180x-qmp-pcie-phy";
2082 #address-cells = <2>;
2083 #size-cells = <2>;
2089 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2092 reset-names = "phy";
2094 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2095 assigned-clock-rates = <100000000>;
2107 clock-names = "pipe0";
2109 #clock-cells = <0>;
2110 clock-output-names = "pcie_2_pipe_clk";
2112 #phy-cells = <0>;
2117 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2118 "jedec,ufs-2.0";
2122 phy-names = "ufsphy";
2123 lanes-per-direction = <2>;
2124 #reset-cells = <1>;
2126 reset-names = "rst";
2138 clock-names = "core_clk",
2146 freq-table-hz = <37500000 300000000>,
2158 ufs_mem_phy: phy-wrapper@1d87000 {
2159 compatible = "qcom,sc8180x-qmp-ufs-phy";
2161 #address-cells = <2>;
2162 #size-cells = <2>;
2166 clock-names = "ref",
2170 reset-names = "ufsphy";
2179 #phy-cells = <0>;
2184 compatible = "qcom,sc8180x-ipa-virt";
2186 #interconnect-cells = <2>;
2187 qcom,bcm-voters = <&apps_bcm_voter>;
2191 compatible = "qcom,tcsr-mutex";
2193 #hwlock-cells = <1>;
2197 compatible = "qcom,adreno-680.1", "qcom,adreno";
2198 #stream-id-cells = <16>;
2201 reg-names = "kgsl_3d0_reg_memory";
2207 operating-points-v2 = <&gpu_opp_table>;
2210 interconnect-names = "gfx-mem";
2215 gpu_opp_table: opp-table {
2216 compatible = "operating-points-v2";
2218 opp-514000000 {
2219 opp-hz = /bits/ 64 <514000000>;
2220 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2223 opp-500000000 {
2224 opp-hz = /bits/ 64 <500000000>;
2225 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2228 opp-461000000 {
2229 opp-hz = /bits/ 64 <461000000>;
2230 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2233 opp-405000000 {
2234 opp-hz = /bits/ 64 <405000000>;
2235 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2238 opp-315000000 {
2239 opp-hz = /bits/ 64 <315000000>;
2240 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2243 opp-256000000 {
2244 opp-hz = /bits/ 64 <256000000>;
2245 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2248 opp-177000000 {
2249 opp-hz = /bits/ 64 <177000000>;
2250 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2256 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2261 reg-names = "gmu",
2267 interrupt-names = "hfi", "gmu";
2274 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2276 power-domains = <&gpucc GPU_CX_GDSC>,
2278 power-domain-names = "cx", "gx";
2282 operating-points-v2 = <&gmu_opp_table>;
2284 gmu_opp_table: opp-table {
2285 compatible = "operating-points-v2";
2287 opp-200000000 {
2288 opp-hz = /bits/ 64 <200000000>;
2289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2292 opp-500000000 {
2293 opp-hz = /bits/ 64 <500000000>;
2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2299 gpucc: clock-controller@2c90000 {
2300 compatible = "qcom,sc8180x-gpucc";
2305 clock-names = "bi_tcxo",
2308 #clock-cells = <1>;
2309 #reset-cells = <1>;
2310 #power-domain-cells = <1>;
2314 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2315 "qcom,smmu-500", "arm,mmu-500";
2317 #iommu-cells = <2>;
2318 #global-interrupts = <1>;
2331 clock-names = "ahb", "bus", "iface";
2333 power-domains = <&gpucc GPU_CX_GDSC>;
2337 compatible = "qcom,sc8180x-tlmm";
2341 reg-names = "west", "east", "south";
2343 gpio-controller;
2344 #gpio-cells = <2>;
2345 interrupt-controller;
2346 #interrupt-cells = <2>;
2347 gpio-ranges = <&tlmm 0 0 191>;
2348 wakeup-parent = <&pdc>;
2352 compatible = "qcom,sc8180x-mpss-pas";
2355 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2361 interrupt-names = "wdog", "fatal", "ready", "handover",
2362 "stop-ack", "shutdown-ack";
2365 clock-names = "xo";
2367 power-domains = <&rpmhpd SC8180X_CX>,
2369 power-domain-names = "cx", "mss";
2373 qcom,smem-states = <&modem_smp2p_out 0>;
2374 qcom,smem-state-names = "stop";
2376 glink-edge {
2379 qcom,remote-pid = <1>;
2385 compatible = "qcom,sc8180x-cdsp-pas";
2388 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2393 interrupt-names = "wdog", "fatal", "ready",
2394 "handover", "stop-ack";
2397 clock-names = "xo";
2399 power-domains = <&rpmhpd SC8180X_CX>;
2400 power-domain-names = "cx";
2404 qcom,smem-states = <&cdsp_smp2p_out 0>;
2405 qcom,smem-state-names = "stop";
2409 glink-edge {
2412 qcom,remote-pid = <5>;
2418 compatible = "qcom,sc8180x-usb-hs-phy",
2419 "qcom,usb-snps-hs-7nm-phy";
2422 clock-names = "ref";
2425 #phy-cells = <0>;
2431 compatible = "qcom,sc8180x-usb-hs-phy",
2432 "qcom,usb-snps-hs-7nm-phy";
2435 clock-names = "ref";
2438 #phy-cells = <0>;
2444 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2448 reg-names = "reg-base", "dp_com";
2453 clock-names = "aux",
2459 reset-names = "phy", "common";
2461 #clock-cells = <1>;
2462 #address-cells = <2>;
2463 #size-cells = <2>;
2469 #address-cells = <1>;
2470 #size-cells = <0>;
2485 usb_prim_ssphy: usb3-phy@88e9200 {
2492 #phy-cells = <0>;
2494 clock-names = "pipe0";
2495 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2498 usb_prim_dpphy: dp-phy@88ea200 {
2504 #clock-cells = <1>;
2505 #phy-cells = <0>;
2510 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2514 reg-names = "reg-base", "dp_com";
2519 clock-names = "aux",
2525 reset-names = "phy", "common";
2527 #clock-cells = <1>;
2528 #address-cells = <2>;
2529 #size-cells = <2>;
2535 #address-cells = <1>;
2536 #size-cells = <0>;
2551 usb_sec_ssphy: usb3-phy@88e9200 {
2558 #phy-cells = <0>;
2560 clock-names = "pipe0";
2561 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2564 usb_sec_dpphy: dp-phy@88ef200 {
2570 #clock-cells = <1>;
2571 #phy-cells = <0>;
2572 clock-output-names = "qmp_dptx1_phy_pll_link_clk",
2577 system-cache-controller@9200000 {
2578 compatible = "qcom,sc8180x-llcc";
2582 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2588 compatible = "qcom,sc8180x-gem-noc";
2590 #interconnect-cells = <2>;
2591 qcom,bcm-voters = <&apps_bcm_voter>;
2595 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2601 interrupt-names = "hs_phy_irq",
2612 clock-names = "cfg_noc",
2619 power-domains = <&gcc USB30_PRIM_GDSC>;
2623 interconnect-names = "usb-ddr", "apps-usb";
2625 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2627 assigned-clock-rates = <19200000>, <200000000>;
2629 #address-cells = <2>;
2630 #size-cells = <2>;
2632 dma-ranges;
2644 phy-names = "usb2-phy", "usb3-phy";
2654 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2663 clock-names = "cfg_noc",
2670 power-domains = <&gcc USB30_SEC_GDSC>;
2675 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2678 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2680 assigned-clock-rates = <19200000>, <200000000>;
2684 interconnect-names = "usb-ddr", "apps-usb";
2686 #address-cells = <2>;
2687 #size-cells = <2>;
2689 dma-ranges;
2701 phy-names = "usb2-phy", "usb3-phy";
2711 compatible = "qcom,sc8180x-mdss";
2713 reg-names = "mdss";
2715 power-domains = <&dispcc MDSS_GDSC>;
2721 clock-names = "iface",
2729 interrupt-controller;
2730 #interrupt-cells = <1>;
2734 interconnect-names = "mdp0-mem", "mdp1-mem";
2738 #address-cells = <2>;
2739 #size-cells = <2>;
2745 compatible = "qcom,sc8180x-dpu";
2748 reg-names = "mdp", "vbif";
2754 clock-names = "iface",
2759 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2761 assigned-clock-rates = <460000000>,
2764 operating-points-v2 = <&mdp_opp_table>;
2765 power-domains = <&rpmhpd SC8180X_MMCX>;
2767 interrupt-parent = <&mdss>;
2771 #address-cells = <1>;
2772 #size-cells = <0>;
2777 remote-endpoint = <&dp0_in>;
2784 remote-endpoint = <&mdss_dsi0_in>;
2791 remote-endpoint = <&mdss_dsi1_in>;
2798 remote-endpoint = <&dp1_in>;
2805 remote-endpoint = <&edp_in>;
2810 mdp_opp_table: opp-table {
2811 compatible = "operating-points-v2";
2813 opp-200000000 {
2814 opp-hz = /bits/ 64 <200000000>;
2815 required-opps = <&rpmhpd_opp_low_svs>;
2818 opp-300000000 {
2819 opp-hz = /bits/ 64 <300000000>;
2820 required-opps = <&rpmhpd_opp_svs>;
2823 opp-345000000 {
2824 opp-hz = /bits/ 64 <345000000>;
2825 required-opps = <&rpmhpd_opp_svs_l1>;
2828 opp-460000000 {
2829 opp-hz = /bits/ 64 <460000000>;
2830 required-opps = <&rpmhpd_opp_nom>;
2836 compatible = "qcom,mdss-dsi-ctrl";
2838 reg-names = "dsi_ctrl";
2840 interrupt-parent = <&mdss>;
2849 clock-names = "byte",
2856 operating-points-v2 = <&dsi_opp_table>;
2857 power-domains = <&rpmhpd SC8180X_MMCX>;
2860 phy-names = "dsi";
2865 #address-cells = <1>;
2866 #size-cells = <0>;
2871 remote-endpoint = <&dpu_intf1_out>;
2882 dsi_opp_table: opp-table {
2883 compatible = "operating-points-v2";
2885 opp-187500000 {
2886 opp-hz = /bits/ 64 <187500000>;
2887 required-opps = <&rpmhpd_opp_low_svs>;
2890 opp-300000000 {
2891 opp-hz = /bits/ 64 <300000000>;
2892 required-opps = <&rpmhpd_opp_svs>;
2895 opp-358000000 {
2896 opp-hz = /bits/ 64 <358000000>;
2897 required-opps = <&rpmhpd_opp_svs_l1>;
2902 mdss_dsi0_phy: dsi-phy@ae94400 {
2903 compatible = "qcom,dsi-phy-7nm";
2907 reg-names = "dsi_phy",
2911 #clock-cells = <1>;
2912 #phy-cells = <0>;
2916 clock-names = "iface", "ref";
2922 compatible = "qcom,mdss-dsi-ctrl";
2924 reg-names = "dsi_ctrl";
2926 interrupt-parent = <&mdss>;
2935 clock-names = "byte",
2942 operating-points-v2 = <&dsi_opp_table>;
2943 power-domains = <&rpmhpd SC8180X_MMCX>;
2946 phy-names = "dsi";
2951 #address-cells = <1>;
2952 #size-cells = <0>;
2957 remote-endpoint = <&dpu_intf2_out>;
2969 mdss_dsi1_phy: dsi-phy@ae96400 {
2970 compatible = "qcom,dsi-phy-7nm";
2974 reg-names = "dsi_phy",
2978 #clock-cells = <1>;
2979 #phy-cells = <0>;
2983 clock-names = "iface", "ref";
2988 mdss_dp0: displayport-controller@ae90000 {
2989 compatible = "qcom,sc8180x-dp";
2994 interrupt-parent = <&mdss>;
3001 clock-names = "core_iface",
3007 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3009 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
3012 phy-names = "dp";
3014 #sound-dai-cells = <0>;
3016 operating-points-v2 = <&dp0_opp_table>;
3017 power-domains = <&rpmhpd SC8180X_MMCX>;
3022 #address-cells = <1>;
3023 #size-cells = <0>;
3028 remote-endpoint = <&dpu_intf0_out>;
3039 dp0_opp_table: opp-table {
3040 compatible = "operating-points-v2";
3042 opp-160000000 {
3043 opp-hz = /bits/ 64 <160000000>;
3044 required-opps = <&rpmhpd_opp_low_svs>;
3047 opp-270000000 {
3048 opp-hz = /bits/ 64 <270000000>;
3049 required-opps = <&rpmhpd_opp_svs>;
3052 opp-540000000 {
3053 opp-hz = /bits/ 64 <540000000>;
3054 required-opps = <&rpmhpd_opp_svs_l1>;
3057 opp-810000000 {
3058 opp-hz = /bits/ 64 <810000000>;
3059 required-opps = <&rpmhpd_opp_nom>;
3064 mdss_dp1: displayport-controller@ae98000 {
3065 compatible = "qcom,sc8180x-dp";
3070 interrupt-parent = <&mdss>;
3077 clock-names = "core_iface",
3083 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3085 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3088 phy-names = "dp";
3090 #sound-dai-cells = <0>;
3092 operating-points-v2 = <&dp0_opp_table>;
3093 power-domains = <&rpmhpd SC8180X_MMCX>;
3098 #address-cells = <1>;
3099 #size-cells = <0>;
3104 remote-endpoint = <&dpu_intf4_out>;
3115 dp1_opp_table: opp-table {
3116 compatible = "operating-points-v2";
3118 opp-160000000 {
3119 opp-hz = /bits/ 64 <160000000>;
3120 required-opps = <&rpmhpd_opp_low_svs>;
3123 opp-270000000 {
3124 opp-hz = /bits/ 64 <270000000>;
3125 required-opps = <&rpmhpd_opp_svs>;
3128 opp-540000000 {
3129 opp-hz = /bits/ 64 <540000000>;
3130 required-opps = <&rpmhpd_opp_svs_l1>;
3133 opp-810000000 {
3134 opp-hz = /bits/ 64 <810000000>;
3135 required-opps = <&rpmhpd_opp_nom>;
3140 mdss_edp: displayport-controller@ae9a000 {
3141 compatible = "qcom,sc8180x-edp";
3146 interrupt-parent = <&mdss>;
3153 clock-names = "core_iface",
3159 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3161 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3164 phy-names = "dp";
3166 #sound-dai-cells = <0>;
3168 operating-points-v2 = <&edp_opp_table>;
3169 power-domains = <&rpmhpd SC8180X_MMCX>;
3174 #address-cells = <1>;
3175 #size-cells = <0>;
3180 remote-endpoint = <&dpu_intf5_out>;
3185 edp_opp_table: opp-table {
3186 compatible = "operating-points-v2";
3188 opp-160000000 {
3189 opp-hz = /bits/ 64 <160000000>;
3190 required-opps = <&rpmhpd_opp_low_svs>;
3193 opp-270000000 {
3194 opp-hz = /bits/ 64 <270000000>;
3195 required-opps = <&rpmhpd_opp_svs>;
3198 opp-540000000 {
3199 opp-hz = /bits/ 64 <540000000>;
3200 required-opps = <&rpmhpd_opp_svs_l1>;
3203 opp-810000000 {
3204 opp-hz = /bits/ 64 <810000000>;
3205 required-opps = <&rpmhpd_opp_nom>;
3212 compatible = "qcom,sc8180x-edp-phy";
3220 clock-names = "aux", "cfg_ahb";
3222 power-domains = <&dispcc MDSS_GDSC>;
3224 #clock-cells = <1>;
3225 #phy-cells = <0>;
3228 dispcc: clock-controller@af00000 {
3229 compatible = "qcom,sc8180x-dispcc";
3239 clock-names = "bi_tcxo",
3247 power-domains = <&rpmhpd SC8180X_MMCX>;
3248 #clock-cells = <1>;
3249 #reset-cells = <1>;
3250 #power-domain-cells = <1>;
3253 pdc: interrupt-controller@b220000 {
3254 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3256 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3257 #interrupt-cells = <2>;
3258 interrupt-parent = <&intc>;
3259 interrupt-controller;
3262 tsens0: thermal-sensor@c263000 {
3263 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3269 interrupt-names = "uplow", "critical";
3270 #thermal-sensor-cells = <1>;
3273 tsens1: thermal-sensor@c265000 {
3274 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3280 interrupt-names = "uplow", "critical";
3281 #thermal-sensor-cells = <1>;
3284 aoss_qmp: power-controller@c300000 {
3285 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3290 #clock-cells = <0>;
3291 #power-domain-cells = <1>;
3295 compatible = "qcom,spmi-pmic-arb";
3301 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3302 interrupt-names = "periph_irq";
3306 #address-cells = <2>;
3307 #size-cells = <0>;
3308 interrupt-controller;
3309 #interrupt-cells = <4>;
3310 cell-index = <0>;
3314 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3316 #iommu-cells = <2>;
3317 #global-interrupts = <1>;
3429 compatible = "qcom,sc8180x-adsp-pas";
3432 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3437 interrupt-names = "wdog", "fatal", "ready",
3438 "handover", "stop-ack";
3441 clock-names = "xo";
3443 power-domains = <&rpmhpd SC8180X_CX>;
3444 power-domain-names = "cx";
3448 qcom,smem-states = <&adsp_smp2p_out 0>;
3449 qcom,smem-state-names = "stop";
3453 remoteproc_adsp_glink: glink-edge {
3456 qcom,remote-pid = <2>;
3461 intc: interrupt-controller@17a00000 {
3462 compatible = "arm,gic-v3";
3463 interrupt-controller;
3464 #interrupt-cells = <3>;
3471 compatible = "qcom,sc8180x-apss-shared";
3473 #mbox-cells = <1>;
3477 compatible = "arm,armv7-timer-mem";
3480 #address-cells = <1>;
3481 #size-cells = <1>;
3487 frame-number = <0>;
3494 frame-number = <1>;
3501 frame-number = <2>;
3508 frame-number = <3>;
3515 frame-number = <4>;
3522 frame-number = <5>;
3529 frame-number = <6>;
3536 compatible = "qcom,rpmh-rsc";
3540 reg-names = "drv-0", "drv-1", "drv-2";
3544 qcom,tcs-offset = <0xd00>;
3545 qcom,drv-id = <2>;
3546 qcom,tcs-config = <ACTIVE_TCS 2>,
3551 power-domains = <&CLUSTER_PD>;
3553 apps_bcm_voter: bcm-voter {
3554 compatible = "qcom,bcm-voter";
3557 rpmhcc: clock-controller {
3558 compatible = "qcom,sc8180x-rpmh-clk";
3559 #clock-cells = <1>;
3560 clock-names = "xo";
3564 rpmhpd: power-controller {
3565 compatible = "qcom,sc8180x-rpmhpd";
3566 #power-domain-cells = <1>;
3567 operating-points-v2 = <&rpmhpd_opp_table>;
3569 rpmhpd_opp_table: opp-table {
3570 compatible = "operating-points-v2";
3573 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3577 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3581 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3585 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3589 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3593 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3597 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3601 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3605 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3609 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3616 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3620 clock-names = "xo", "alternate";
3622 #interconnect-cells = <1>;
3626 compatible = "qcom,sc8180x-lmh";
3630 qcom,lmh-temp-arm-millicelsius = <65000>;
3631 qcom,lmh-temp-low-millicelsius = <94500>;
3632 qcom,lmh-temp-high-millicelsius = <95000>;
3633 interrupt-controller;
3634 #interrupt-cells = <1>;
3638 compatible = "qcom,sc8180x-lmh";
3642 qcom,lmh-temp-arm-millicelsius = <65000>;
3643 qcom,lmh-temp-low-millicelsius = <94500>;
3644 qcom,lmh-temp-high-millicelsius = <95000>;
3645 interrupt-controller;
3646 #interrupt-cells = <1>;
3650 compatible = "qcom,cpufreq-hw";
3652 reg-names = "freq-domain0", "freq-domain1";
3655 clock-names = "xo", "alternate";
3657 #freq-domain-cells = <1>;
3658 #clock-cells = <1>;
3662 compatible = "qcom,wcn3990-wifi";
3664 reg-names = "membase";
3665 clock-names = "cxo_ref_clk_pin";
3680 qcom,msa-fixed-perm;
3685 thermal-zones {
3686 cpu0-thermal {
3687 polling-delay-passive = <250>;
3688 polling-delay = <1000>;
3690 thermal-sensors = <&tsens0 1>;
3693 cpu-crit {
3701 cpu1-thermal {
3702 polling-delay-passive = <250>;
3703 polling-delay = <1000>;
3705 thermal-sensors = <&tsens0 2>;
3708 cpu-crit {
3716 cpu2-thermal {
3717 polling-delay-passive = <250>;
3718 polling-delay = <1000>;
3720 thermal-sensors = <&tsens0 3>;
3723 cpu-crit {
3731 cpu3-thermal {
3732 polling-delay-passive = <250>;
3733 polling-delay = <1000>;
3735 thermal-sensors = <&tsens0 4>;
3738 cpu-crit {
3746 cpu4-top-thermal {
3747 polling-delay-passive = <250>;
3748 polling-delay = <1000>;
3750 thermal-sensors = <&tsens0 7>;
3753 cpu-crit {
3761 cpu5-top-thermal {
3762 polling-delay-passive = <250>;
3763 polling-delay = <1000>;
3765 thermal-sensors = <&tsens0 8>;
3768 cpu-crit {
3776 cpu6-top-thermal {
3777 polling-delay-passive = <250>;
3778 polling-delay = <1000>;
3780 thermal-sensors = <&tsens0 9>;
3783 cpu-crit {
3791 cpu7-top-thermal {
3792 polling-delay-passive = <250>;
3793 polling-delay = <1000>;
3795 thermal-sensors = <&tsens0 10>;
3798 cpu-crit {
3806 cpu4-bottom-thermal {
3807 polling-delay-passive = <250>;
3808 polling-delay = <1000>;
3810 thermal-sensors = <&tsens0 11>;
3813 cpu-crit {
3821 cpu5-bottom-thermal {
3822 polling-delay-passive = <250>;
3823 polling-delay = <1000>;
3825 thermal-sensors = <&tsens0 12>;
3828 cpu-crit {
3836 cpu6-bottom-thermal {
3837 polling-delay-passive = <250>;
3838 polling-delay = <1000>;
3840 thermal-sensors = <&tsens0 13>;
3843 cpu-crit {
3851 cpu7-bottom-thermal {
3852 polling-delay-passive = <250>;
3853 polling-delay = <1000>;
3855 thermal-sensors = <&tsens0 14>;
3858 cpu-crit {
3866 aoss0-thermal {
3867 polling-delay-passive = <250>;
3868 polling-delay = <1000>;
3870 thermal-sensors = <&tsens0 0>;
3873 trip-point0 {
3881 cluster0-thermal {
3882 polling-delay-passive = <250>;
3883 polling-delay = <1000>;
3885 thermal-sensors = <&tsens0 5>;
3888 cluster-crit {
3896 cluster1-thermal {
3897 polling-delay-passive = <250>;
3898 polling-delay = <1000>;
3900 thermal-sensors = <&tsens0 6>;
3903 cluster-crit {
3911 gpu-top-thermal {
3912 polling-delay-passive = <250>;
3913 polling-delay = <1000>;
3915 thermal-sensors = <&tsens0 15>;
3918 trip-point0 {
3926 aoss1-thermal {
3927 polling-delay-passive = <250>;
3928 polling-delay = <1000>;
3930 thermal-sensors = <&tsens1 0>;
3933 trip-point0 {
3941 wlan-thermal {
3942 polling-delay-passive = <250>;
3943 polling-delay = <1000>;
3945 thermal-sensors = <&tsens1 1>;
3948 trip-point0 {
3956 video-thermal {
3957 polling-delay-passive = <250>;
3958 polling-delay = <1000>;
3960 thermal-sensors = <&tsens1 2>;
3963 trip-point0 {
3971 mem-thermal {
3972 polling-delay-passive = <250>;
3973 polling-delay = <1000>;
3975 thermal-sensors = <&tsens1 3>;
3978 trip-point0 {
3986 q6-hvx-thermal {
3987 polling-delay-passive = <250>;
3988 polling-delay = <1000>;
3990 thermal-sensors = <&tsens1 4>;
3993 trip-point0 {
4001 camera-thermal {
4002 polling-delay-passive = <250>;
4003 polling-delay = <1000>;
4005 thermal-sensors = <&tsens1 5>;
4008 trip-point0 {
4016 compute-thermal {
4017 polling-delay-passive = <250>;
4018 polling-delay = <1000>;
4020 thermal-sensors = <&tsens1 6>;
4023 trip-point0 {
4031 mdm-dsp-thermal {
4032 polling-delay-passive = <250>;
4033 polling-delay = <1000>;
4035 thermal-sensors = <&tsens1 7>;
4038 trip-point0 {
4046 npu-thermal {
4047 polling-delay-passive = <250>;
4048 polling-delay = <1000>;
4050 thermal-sensors = <&tsens1 8>;
4053 trip-point0 {
4061 gpu-bottom-thermal {
4062 polling-delay-passive = <250>;
4063 polling-delay = <1000>;
4065 thermal-sensors = <&tsens1 11>;
4068 trip-point0 {
4078 compatible = "arm,armv8-timer";