Lines Matching +full:0 +full:x0c440000
27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
100 reg = <0x0 0x200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
111 clocks = <&cpufreq_hw 0>;
124 reg = <0x0 0x300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
135 clocks = <&cpufreq_hw 0>;
148 reg = <0x0 0x400>;
172 reg = <0x0 0x500>;
196 reg = <0x0 0x600>;
220 reg = <0x0 0x700>;
280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
282 arm,psci-suspend-param = <0x40000004>;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
291 arm,psci-suspend-param = <0x40000004>;
300 CLUSTER_SLEEP_0: cluster-sleep-0 {
302 arm,psci-suspend-param = <0x4100a344>;
522 reg = <0x0 0x80000000 0x0 0x0>;
535 #power-domain-cells = <0>;
541 #power-domain-cells = <0>;
547 #power-domain-cells = <0>;
553 #power-domain-cells = <0>;
559 #power-domain-cells = <0>;
565 #power-domain-cells = <0>;
571 #power-domain-cells = <0>;
577 #power-domain-cells = <0>;
583 #power-domain-cells = <0>;
594 reg = <0x0 0x85700000 0x0 0x600000>;
599 reg = <0x0 0x85d00000 0x0 0x140000>;
604 reg = <0x0 0x85f00000 0x0 0x20000>;
610 reg = <0x0 0x85f20000 0x0 0x20000>;
615 reg = <0x0 0x85f40000 0x0 0x10000>;
621 reg = <0x0 0x86000000 0x0 0x200000>;
627 reg = <0x0 0x86200000 0x0 0x3900000>;
632 reg = <0x0 0x89b00000 0x0 0x1c00000>;
637 reg = <0x0 0x9d400000 0x0 0x1000000>;
642 reg = <0x0 0x9e400000 0x0 0x1400000>;
647 reg = <0x0 0x9f800000 0x0 0x800000>;
660 qcom,local-pid = <0>;
684 qcom,local-pid = <0>;
708 qcom,local-pid = <0>;
749 qcom,local-pid = <0>;
765 soc: soc@0 {
769 ranges = <0 0 0 0 0x10 0>;
770 dma-ranges = <0 0 0 0 0x10 0>;
774 reg = <0x0 0x00100000 0x0 0x1f0000>;
788 reg = <0 0x008c0000 0 0x6000>;
795 iommus = <&apps_smmu 0x4c3 0>;
800 reg = <0 0x00880000 0 0x4000>;
804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
805 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
806 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
809 #size-cells = <0>;
815 reg = <0 0x00880000 0 0x4000>;
819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
820 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
823 #size-cells = <0>;
829 reg = <0 0x00880000 0 0x4000>;
833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
834 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
841 reg = <0 0x00884000 0 0x4000>;
845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
847 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
850 #size-cells = <0>;
856 reg = <0 0x00884000 0 0x4000>;
860 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
861 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
864 #size-cells = <0>;
870 reg = <0 0x00884000 0 0x4000>;
874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
882 reg = <0 0x00888000 0 0x4000>;
886 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
888 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
891 #size-cells = <0>;
897 reg = <0 0x00888000 0 0x4000>;
901 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
902 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
905 #size-cells = <0>;
911 reg = <0 0x00888000 0 0x4000>;
915 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
916 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
923 reg = <0 0x0088c000 0 0x4000>;
927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
928 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
929 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
932 #size-cells = <0>;
938 reg = <0 0x0088c000 0 0x4000>;
942 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
943 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
946 #size-cells = <0>;
952 reg = <0 0x0088c000 0 0x4000>;
956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
964 reg = <0 0x00890000 0 0x4000>;
968 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
969 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
970 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
973 #size-cells = <0>;
979 reg = <0 0x00890000 0 0x4000>;
983 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
984 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
987 #size-cells = <0>;
993 reg = <0 0x00890000 0 0x4000>;
997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
998 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1005 reg = <0 0x00894000 0 0x4000>;
1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1011 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1014 #size-cells = <0>;
1020 reg = <0 0x00894000 0 0x4000>;
1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1028 #size-cells = <0>;
1034 reg = <0 0x00894000 0 0x4000>;
1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1039 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1046 reg = <0 0x00898000 0 0x4000>;
1050 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1052 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1055 #size-cells = <0>;
1061 reg = <0 0x00898000 0 0x4000>;
1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1069 #size-cells = <0>;
1075 reg = <0 0x00898000 0 0x4000>;
1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1087 reg = <0 0x0089c000 0 0x4000>;
1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1092 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1093 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1096 #size-cells = <0>;
1102 reg = <0 0x0089c000 0 0x4000>;
1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1110 #size-cells = <0>;
1116 reg = <0 0x0089c000 0 0x4000>;
1120 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1121 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1129 reg = <0x0 0x00ac0000 0x0 0x6000>;
1136 iommus = <&apps_smmu 0x603 0>;
1141 reg = <0 0x00a80000 0 0x4000>;
1145 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1147 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1150 #size-cells = <0>;
1156 reg = <0 0x00a80000 0 0x4000>;
1160 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1161 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1164 #size-cells = <0>;
1170 reg = <0 0x00a80000 0 0x4000>;
1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1182 reg = <0 0x00a84000 0 0x4000>;
1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1187 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1188 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1191 #size-cells = <0>;
1197 reg = <0 0x00a84000 0 0x4000>;
1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1202 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1205 #size-cells = <0>;
1211 reg = <0 0x00a84000 0 0x4000>;
1215 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1223 reg = <0 0x00a88000 0 0x4000>;
1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1232 #size-cells = <0>;
1238 reg = <0 0x00a88000 0 0x4000>;
1242 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1246 #size-cells = <0>;
1252 reg = <0 0x00a88000 0 0x4000>;
1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1257 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1264 reg = <0 0x00a8c000 0 0x4000>;
1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1269 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1270 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1273 #size-cells = <0>;
1279 reg = <0 0x00a8c000 0 0x4000>;
1283 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1284 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1287 #size-cells = <0>;
1293 reg = <0 0x00a8c000 0 0x4000>;
1297 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1298 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1305 reg = <0 0x00a90000 0 0x4000>;
1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1314 #size-cells = <0>;
1320 reg = <0 0x00a90000 0 0x4000>;
1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1325 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1328 #size-cells = <0>;
1334 reg = <0 0x00a90000 0 0x4000>;
1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1339 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1346 reg = <0 0x00a94000 0 0x4000>;
1350 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1351 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1352 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1355 #size-cells = <0>;
1361 reg = <0 0x00a94000 0 0x4000>;
1365 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1366 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1369 #size-cells = <0>;
1375 reg = <0 0x00a94000 0 0x4000>;
1379 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1388 reg = <0x0 0x00cc0000 0x0 0x6000>;
1395 iommus = <&apps_smmu 0x7a3 0>;
1400 reg = <0 0x00c80000 0 0x4000>;
1404 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1405 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1406 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1409 #size-cells = <0>;
1415 reg = <0 0x00c80000 0 0x4000>;
1419 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1423 #size-cells = <0>;
1429 reg = <0 0x00c80000 0 0x4000>;
1433 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1434 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1441 reg = <0 0x00c84000 0 0x4000>;
1445 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1446 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1447 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1450 #size-cells = <0>;
1456 reg = <0 0x00c84000 0 0x4000>;
1460 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1461 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1464 #size-cells = <0>;
1470 reg = <0 0x00c84000 0 0x4000>;
1474 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1475 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1482 reg = <0 0x00c88000 0 0x4000>;
1486 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1488 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1491 #size-cells = <0>;
1497 reg = <0 0x00c88000 0 0x4000>;
1501 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1502 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1505 #size-cells = <0>;
1511 reg = <0 0x00c88000 0 0x4000>;
1515 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1516 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1523 reg = <0 0x00c8c000 0 0x4000>;
1527 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1529 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1532 #size-cells = <0>;
1538 reg = <0 0x00c8c000 0 0x4000>;
1542 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1543 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1546 #size-cells = <0>;
1552 reg = <0 0x00c8c000 0 0x4000>;
1556 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1557 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1564 reg = <0 0x00c90000 0 0x4000>;
1568 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1570 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1573 #size-cells = <0>;
1579 reg = <0 0x00c90000 0 0x4000>;
1583 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1584 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1587 #size-cells = <0>;
1593 reg = <0 0x00c90000 0 0x4000>;
1597 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1598 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1605 reg = <0 0x00c94000 0 0x4000>;
1609 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1610 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1611 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1614 #size-cells = <0>;
1620 reg = <0 0x00c94000 0 0x4000>;
1624 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1625 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1628 #size-cells = <0>;
1634 reg = <0 0x00c94000 0 0x4000>;
1638 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1647 reg = <0 0x01500000 0 0x7400>;
1654 reg = <0 0x01620000 0 0x19400>;
1661 reg = <0 0x016e0000 0 0xd080>;
1668 reg = <0 0x01700000 0 0x20000>;
1675 reg = <0 0x01720000 0 0x7000>;
1682 reg = <0 0x01740000 0 0x1c100>;
1689 reg = <0 0x01c00000 0 0x3000>,
1690 <0 0x60000000 0 0xf1d>,
1691 <0 0x60000f20 0 0xa8>,
1692 <0 0x60001000 0 0x1000>,
1693 <0 0x60100000 0 0x100000>;
1700 linux,pci-domain = <0>;
1701 bus-range = <0x00 0xff>;
1707 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1713 interrupt-map-mask = <0 0 0 0x7>;
1714 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1715 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1716 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1717 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1739 iommus = <&apps_smmu 0x1d80 0x7f>;
1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1741 <0x100 &apps_smmu 0x1d81 0x1>;
1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1760 reg = <0 0x1c06000 0 0x1c0>;
1779 reg = <0 0x1c06200 0 0x170>, /* tx0 */
1780 <0 0x1c06400 0 0x200>, /* rx0 */
1781 <0 0x1c06a00 0 0x1f0>, /* pcs */
1782 <0 0x1c06600 0 0x170>, /* tx1 */
1783 <0 0x1c06800 0 0x200>, /* rx1 */
1784 <0 0x1c06e00 0 0xf4>; /* pcs_com */
1788 #clock-cells = <0>;
1790 #phy-cells = <0>;
1796 reg = <0 0x01c08000 0 0x3000>,
1797 <0 0x40000000 0 0xf1d>,
1798 <0 0x40000f20 0 0xa8>,
1799 <0 0x40001000 0 0x1000>,
1800 <0 0x40100000 0 0x100000>;
1808 bus-range = <0x00 0xff>;
1814 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1815 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1820 interrupt-map-mask = <0 0 0 0x7>;
1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1822 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1823 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1824 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1846 iommus = <&apps_smmu 0x1e00 0x7f>;
1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1848 <0x100 &apps_smmu 0x1e01 0x1>;
1855 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1867 reg = <0 0x1c0c000 0 0x1c0>;
1886 reg = <0 0x1c0c200 0 0x170>, /* tx0 */
1887 <0 0x1c0c400 0 0x200>, /* rx0 */
1888 <0 0x1c0ca00 0 0x1f0>, /* pcs */
1889 <0 0x1c0c600 0 0x170>, /* tx1 */
1890 <0 0x1c0c800 0 0x200>, /* rx1 */
1891 <0 0x1c0ce00 0 0xf4>; /* pcs_com */
1895 #clock-cells = <0>;
1897 #phy-cells = <0>;
1903 reg = <0 0x01c10000 0 0x3000>,
1904 <0 0x68000000 0 0xf1d>,
1905 <0 0x68000f20 0 0xa8>,
1906 <0 0x68001000 0 0x1000>,
1907 <0 0x68100000 0 0x100000>;
1915 bus-range = <0x00 0xff>;
1921 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1922 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1953 iommus = <&apps_smmu 0x1c80 0x7f>;
1954 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1955 <0x100 &apps_smmu 0x1c81 0x1>;
1962 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1963 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1974 reg = <0 0x1c16000 0 0x1c0>;
1993 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1994 <0 0x1c16400 0 0x200>, /* rx0 */
1995 <0 0x1c16a00 0 0x1f0>, /* pcs */
1996 <0 0x1c16600 0 0x170>, /* tx1 */
1997 <0 0x1c16800 0 0x200>, /* rx1 */
1998 <0 0x1c16e00 0 0xf4>; /* pcs_com */
2001 #clock-cells = <0>;
2004 #phy-cells = <0>;
2010 reg = <0 0x01c18000 0 0x3000>,
2011 <0 0x70000000 0 0xf1d>,
2012 <0 0x70000f20 0 0xa8>,
2013 <0 0x70001000 0 0x1000>,
2014 <0 0x70100000 0 0x100000>;
2022 bus-range = <0x00 0xff>;
2028 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2029 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2034 interrupt-map-mask = <0 0 0 0x7>;
2035 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2036 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2037 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2038 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2060 iommus = <&apps_smmu 0x1d00 0x7f>;
2061 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2062 <0x100 &apps_smmu 0x1d01 0x1>;
2069 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2070 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2081 reg = <0 0x1c1c000 0 0x1c0>;
2100 reg = <0 0x1c1c200 0 0x170>, /* tx0 */
2101 <0 0x1c1c400 0 0x200>, /* rx0 */
2102 <0 0x1c1ca00 0 0x1f0>, /* pcs */
2103 <0 0x1c1c600 0 0x170>, /* tx1 */
2104 <0 0x1c1c800 0 0x200>, /* rx1 */
2105 <0 0x1c1ce00 0 0xf4>; /* pcs_com */
2109 #clock-cells = <0>;
2112 #phy-cells = <0>;
2119 reg = <0 0x01d84000 0 0x2500>;
2128 iommus = <&apps_smmu 0x300 0>;
2147 <0 0>,
2148 <0 0>,
2150 <0 0>,
2151 <0 0>,
2152 <0 0>,
2153 <0 0>;
2160 reg = <0 0x01d87000 0 0x1c0>;
2169 resets = <&ufs_mem_hc 0>;
2174 reg = <0 0x01d87400 0 0x108>,
2175 <0 0x01d87600 0 0x1e0>,
2176 <0 0x01d87c00 0 0x1dc>,
2177 <0 0x01d87800 0 0x108>,
2178 <0 0x01d87a00 0 0x1e0>;
2179 #phy-cells = <0>;
2185 reg = <0 0x01e00000 0 0x1000>;
2192 reg = <0x0 0x01f40000 0x0 0x40000>;
2200 reg = <0 0x02c00000 0 0x40000>;
2205 iommus = <&adreno_smmu 0 0xc01>;
2209 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2258 reg = <0 0x02c6a000 0 0x30000>,
2259 <0 0x0b290000 0 0x10000>,
2260 <0 0x0b490000 0 0x10000>;
2280 iommus = <&adreno_smmu 5 0xc00>;
2301 reg = <0 0x02c90000 0 0x9000>;
2316 reg = <0 0x02ca0000 0 0x10000>;
2338 reg = <0 0x03100000 0 0x300000>,
2339 <0 0x03500000 0 0x700000>,
2340 <0 0x03d00000 0 0x300000>;
2347 gpio-ranges = <&tlmm 0 0 191>;
2353 reg = <0x0 0x04080000 0x0 0x4040>;
2356 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2373 qcom,smem-states = <&modem_smp2p_out 0>;
2386 reg = <0x0 0x08300000 0x0 0x4040>;
2389 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2404 qcom,smem-states = <&cdsp_smp2p_out 0>;
2420 reg = <0 0x088e2000 0 0x400>;
2425 #phy-cells = <0>;
2433 reg = <0 0x088e3000 0 0x400>;
2438 #phy-cells = <0>;
2445 reg = <0 0x088e9000 0 0x18c>,
2446 <0 0x088e8000 0 0x38>,
2447 <0 0x088ea000 0 0x40>;
2470 #size-cells = <0>;
2472 port@0 {
2473 reg = <0>;
2486 reg = <0 0x088e9200 0 0x200>,
2487 <0 0x088e9400 0 0x200>,
2488 <0 0x088e9c00 0 0x218>,
2489 <0 0x088e9600 0 0x200>,
2490 <0 0x088e9800 0 0x200>,
2491 <0 0x088e9a00 0 0x100>;
2492 #phy-cells = <0>;
2499 reg = <0 0x088ea200 0 0x200>,
2500 <0 0x088ea400 0 0x200>,
2501 <0 0x088eaa00 0 0x200>,
2502 <0 0x088ea600 0 0x200>,
2503 <0 0x088ea800 0 0x200>;
2505 #phy-cells = <0>;
2511 reg = <0 0x088ee000 0 0x18c>,
2512 <0 0x088ed000 0 0x10>,
2513 <0 0x088ef000 0 0x40>;
2536 #size-cells = <0>;
2538 port@0 {
2539 reg = <0>;
2552 reg = <0 0x088ee200 0 0x200>,
2553 <0 0x088ee400 0 0x200>,
2554 <0 0x088eec00 0 0x218>,
2555 <0 0x088ee600 0 0x200>,
2556 <0 0x088ee800 0 0x200>,
2557 <0 0x088eea00 0 0x100>;
2558 #phy-cells = <0>;
2565 reg = <0 0x088ef200 0 0x200>,
2566 <0 0x088ef400 0 0x200>,
2567 <0 0x088efa00 0 0x200>,
2568 <0 0x088ef600 0 0x200>,
2569 <0 0x088ef800 0 0x200>;
2571 #phy-cells = <0>;
2579 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
2580 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
2581 <0 0x09600000 0 0x50000>;
2589 reg = <0 0x09680000 0 0x58200>;
2596 reg = <0 0x0a6f8800 0 0x400>;
2621 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2622 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2638 reg = <0 0x0a600000 0 0xcd00>;
2640 iommus = <&apps_smmu 0x140 0>;
2655 reg = <0 0x0a8f8800 0 0x400>;
2682 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2683 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2695 reg = <0 0x0a800000 0 0xcd00>;
2697 iommus = <&apps_smmu 0x160 0>;
2712 reg = <0 0x0ae00000 0 0x1000>;
2732 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
2733 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
2736 iommus = <&apps_smmu 0x800 0x420>;
2746 reg = <0 0x0ae01000 0 0x8f000>,
2747 <0 0x0aeb0000 0 0x2008>;
2768 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2772 #size-cells = <0>;
2774 port@0 {
2775 reg = <0>;
2837 reg = <0 0x0ae94000 0 0x400>;
2866 #size-cells = <0>;
2868 port@0 {
2869 reg = <0>;
2904 reg = <0 0x0ae94400 0 0x200>,
2905 <0 0x0ae94600 0 0x280>,
2906 <0 0x0ae94900 0 0x260>;
2912 #phy-cells = <0>;
2923 reg = <0 0x0ae96000 0 0x400>;
2952 #size-cells = <0>;
2954 port@0 {
2955 reg = <0>;
2971 reg = <0 0x0ae96400 0 0x200>,
2972 <0 0x0ae96600 0 0x280>,
2973 <0 0x0ae96900 0 0x260>;
2979 #phy-cells = <0>;
2990 reg = <0 0xae90000 0 0x200>,
2991 <0 0xae90200 0 0x200>,
2992 <0 0xae90400 0 0x600>,
2993 <0 0xae90a00 0 0x400>;
3009 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
3014 #sound-dai-cells = <0>;
3023 #size-cells = <0>;
3025 port@0 {
3026 reg = <0>;
3066 reg = <0 0xae98000 0 0x200>,
3067 <0 0xae98200 0 0x200>,
3068 <0 0xae98400 0 0x600>,
3069 <0 0xae98a00 0 0x400>;
3085 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3090 #sound-dai-cells = <0>;
3099 #size-cells = <0>;
3101 port@0 {
3102 reg = <0>;
3142 reg = <0 0xae9a000 0 0x200>,
3143 <0 0xae9a200 0 0x200>,
3144 <0 0xae9a400 0 0x600>,
3145 <0 0xae9aa00 0 0x400>;
3161 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3166 #sound-dai-cells = <0>;
3175 #size-cells = <0>;
3177 port@0 {
3178 reg = <0>;
3213 reg = <0 0x0aec2a00 0 0x1c0>,
3214 <0 0x0aec2200 0 0xa0>,
3215 <0 0x0aec2600 0 0xa0>,
3216 <0 0x0aec2000 0 0x19c>;
3225 #phy-cells = <0>;
3230 reg = <0 0x0af00000 0 0x20000>;
3233 <&usb_prim_dpphy 0>,
3235 <&usb_sec_dpphy 0>,
3237 <&edp_phy 0>,
3255 reg = <0 0x0b220000 0 0x30000>;
3256 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3264 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3265 <0 0x0c222000 0 0x1ff>; /* SROT */
3275 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3276 <0 0x0c223000 0 0x1ff>; /* SROT */
3286 reg = <0x0 0x0c300000 0x0 0x100000>;
3288 mboxes = <&apss_shared 0>;
3290 #clock-cells = <0>;
3296 reg = <0x0 0x0c440000 0x0 0x0001100>,
3297 <0x0 0x0c600000 0x0 0x2000000>,
3298 <0x0 0x0e600000 0x0 0x0100000>,
3299 <0x0 0x0e700000 0x0 0x00a0000>,
3300 <0x0 0x0c40a000 0x0 0x0026000>;
3304 qcom,ee = <0>;
3305 qcom,channel = <0>;
3307 #size-cells = <0>;
3310 cell-index = <0>;
3315 reg = <0 0x15000000 0 0x100000>;
3430 reg = <0x0 0x17300000 0x0 0x4040>;
3433 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3448 qcom,smem-states = <&adsp_smp2p_out 0>;
3465 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3466 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3472 reg = <0x0 0x17c00000 0x0 0x1000>;
3478 reg = <0x0 0x17c20000 0x0 0x1000>;
3482 ranges = <0 0 0 0x20000000>;
3485 reg = <0x17c21000 0x1000>,
3486 <0x17c22000 0x1000>;
3487 frame-number = <0>;
3493 reg = <0x17c23000 0x1000>;
3500 reg = <0x17c25000 0x1000>;
3507 reg = <0x17c26000 0x1000>;
3514 reg = <0x17c29000 0x1000>;
3521 reg = <0x17c2b000 0x1000>;
3528 reg = <0x17c2d000 0x1000>;
3537 reg = <0x0 0x18200000 0x0 0x10000>,
3538 <0x0 0x18210000 0x0 0x10000>,
3539 <0x0 0x18220000 0x0 0x10000>;
3540 reg-names = "drv-0", "drv-1", "drv-2";
3544 qcom,tcs-offset = <0xd00>;
3549 <CONTROL_TCS 0>;
3617 reg = <0 0x18321000 0 0x1400>;
3627 reg = <0 0x18350800 0 0x400>;
3639 reg = <0 0x18358800 0 0x400>;
3651 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3663 reg = <0 0x18800000 0 0x800000>;
3679 iommus = <&apps_smmu 0x0640 0x1>;
3870 thermal-sensors = <&tsens0 0>;
3930 thermal-sensors = <&tsens1 0>;
4082 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;