Lines Matching +full:adreno +full:- +full:gmu +full:- +full:wrapper
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7280.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,lpass.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
31 #address-cells = <2>;
32 #size-cells = <2>;
74 xo_board: xo-board {
75 compatible = "fixed-clock";
76 clock-frequency = <76800000>;
77 #clock-cells = <0>;
80 sleep_clk: sleep-clk {
81 compatible = "fixed-clock";
82 clock-frequency = <32000>;
83 #clock-cells = <0>;
87 reserved-memory {
88 #address-cells = <2>;
89 #size-cells = <2>;
93 no-map;
99 no-map;
104 no-map;
109 no-map;
114 compatible = "qcom,cmd-db";
115 no-map;
120 no-map;
125 no-map;
130 no-map;
134 no-map;
140 no-map;
145 no-map;
150 no-map;
154 compatible = "qcom,rmtfs-mem";
156 no-map;
158 qcom,client-id = <1>;
164 #address-cells = <2>;
165 #size-cells = <0>;
172 enable-method = "psci";
173 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
176 next-level-cache = <&L2_0>;
177 operating-points-v2 = <&cpu0_opp_table>;
180 qcom,freq-domain = <&cpufreq_hw 0>;
181 #cooling-cells = <2>;
182 L2_0: l2-cache {
184 cache-level = <2>;
185 cache-unified;
186 next-level-cache = <&L3_0>;
187 L3_0: l3-cache {
189 cache-level = <3>;
190 cache-unified;
200 enable-method = "psci";
201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
204 next-level-cache = <&L2_100>;
205 operating-points-v2 = <&cpu0_opp_table>;
208 qcom,freq-domain = <&cpufreq_hw 0>;
209 #cooling-cells = <2>;
210 L2_100: l2-cache {
212 cache-level = <2>;
213 cache-unified;
214 next-level-cache = <&L3_0>;
223 enable-method = "psci";
224 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
227 next-level-cache = <&L2_200>;
228 operating-points-v2 = <&cpu0_opp_table>;
231 qcom,freq-domain = <&cpufreq_hw 0>;
232 #cooling-cells = <2>;
233 L2_200: l2-cache {
235 cache-level = <2>;
236 cache-unified;
237 next-level-cache = <&L3_0>;
246 enable-method = "psci";
247 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
250 next-level-cache = <&L2_300>;
251 operating-points-v2 = <&cpu0_opp_table>;
254 qcom,freq-domain = <&cpufreq_hw 0>;
255 #cooling-cells = <2>;
256 L2_300: l2-cache {
258 cache-level = <2>;
259 cache-unified;
260 next-level-cache = <&L3_0>;
269 enable-method = "psci";
270 cpu-idle-states = <&BIG_CPU_SLEEP_0
273 next-level-cache = <&L2_400>;
274 operating-points-v2 = <&cpu4_opp_table>;
277 qcom,freq-domain = <&cpufreq_hw 1>;
278 #cooling-cells = <2>;
279 L2_400: l2-cache {
281 cache-level = <2>;
282 cache-unified;
283 next-level-cache = <&L3_0>;
292 enable-method = "psci";
293 cpu-idle-states = <&BIG_CPU_SLEEP_0
296 next-level-cache = <&L2_500>;
297 operating-points-v2 = <&cpu4_opp_table>;
300 qcom,freq-domain = <&cpufreq_hw 1>;
301 #cooling-cells = <2>;
302 L2_500: l2-cache {
304 cache-level = <2>;
305 cache-unified;
306 next-level-cache = <&L3_0>;
315 enable-method = "psci";
316 cpu-idle-states = <&BIG_CPU_SLEEP_0
319 next-level-cache = <&L2_600>;
320 operating-points-v2 = <&cpu4_opp_table>;
323 qcom,freq-domain = <&cpufreq_hw 1>;
324 #cooling-cells = <2>;
325 L2_600: l2-cache {
327 cache-level = <2>;
328 cache-unified;
329 next-level-cache = <&L3_0>;
338 enable-method = "psci";
339 cpu-idle-states = <&BIG_CPU_SLEEP_0
342 next-level-cache = <&L2_700>;
343 operating-points-v2 = <&cpu7_opp_table>;
346 qcom,freq-domain = <&cpufreq_hw 2>;
347 #cooling-cells = <2>;
348 L2_700: l2-cache {
350 cache-level = <2>;
351 cache-unified;
352 next-level-cache = <&L3_0>;
356 cpu-map {
392 idle-states {
393 entry-method = "psci";
395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
396 compatible = "arm,idle-state";
397 idle-state-name = "little-power-down";
398 arm,psci-suspend-param = <0x40000003>;
399 entry-latency-us = <549>;
400 exit-latency-us = <901>;
401 min-residency-us = <1774>;
402 local-timer-stop;
405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
406 compatible = "arm,idle-state";
407 idle-state-name = "little-rail-power-down";
408 arm,psci-suspend-param = <0x40000004>;
409 entry-latency-us = <702>;
410 exit-latency-us = <915>;
411 min-residency-us = <4001>;
412 local-timer-stop;
415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
416 compatible = "arm,idle-state";
417 idle-state-name = "big-power-down";
418 arm,psci-suspend-param = <0x40000003>;
419 entry-latency-us = <523>;
420 exit-latency-us = <1244>;
421 min-residency-us = <2207>;
422 local-timer-stop;
425 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
426 compatible = "arm,idle-state";
427 idle-state-name = "big-rail-power-down";
428 arm,psci-suspend-param = <0x40000004>;
429 entry-latency-us = <526>;
430 exit-latency-us = <1854>;
431 min-residency-us = <5555>;
432 local-timer-stop;
435 CLUSTER_SLEEP_0: cluster-sleep-0 {
436 compatible = "arm,idle-state";
437 idle-state-name = "cluster-power-down";
438 arm,psci-suspend-param = <0x40003444>;
439 entry-latency-us = <3263>;
440 exit-latency-us = <6562>;
441 min-residency-us = <9926>;
442 local-timer-stop;
447 cpu0_opp_table: opp-table-cpu0 {
448 compatible = "operating-points-v2";
449 opp-shared;
451 cpu0_opp_300mhz: opp-300000000 {
452 opp-hz = /bits/ 64 <300000000>;
453 opp-peak-kBps = <800000 9600000>;
456 cpu0_opp_691mhz: opp-691200000 {
457 opp-hz = /bits/ 64 <691200000>;
458 opp-peak-kBps = <800000 17817600>;
461 cpu0_opp_806mhz: opp-806400000 {
462 opp-hz = /bits/ 64 <806400000>;
463 opp-peak-kBps = <800000 20889600>;
466 cpu0_opp_941mhz: opp-940800000 {
467 opp-hz = /bits/ 64 <940800000>;
468 opp-peak-kBps = <1804000 24576000>;
471 cpu0_opp_1152mhz: opp-1152000000 {
472 opp-hz = /bits/ 64 <1152000000>;
473 opp-peak-kBps = <2188000 27033600>;
476 cpu0_opp_1325mhz: opp-1324800000 {
477 opp-hz = /bits/ 64 <1324800000>;
478 opp-peak-kBps = <2188000 33792000>;
481 cpu0_opp_1517mhz: opp-1516800000 {
482 opp-hz = /bits/ 64 <1516800000>;
483 opp-peak-kBps = <3072000 38092800>;
486 cpu0_opp_1651mhz: opp-1651200000 {
487 opp-hz = /bits/ 64 <1651200000>;
488 opp-peak-kBps = <3072000 41779200>;
491 cpu0_opp_1805mhz: opp-1804800000 {
492 opp-hz = /bits/ 64 <1804800000>;
493 opp-peak-kBps = <4068000 48537600>;
496 cpu0_opp_1958mhz: opp-1958400000 {
497 opp-hz = /bits/ 64 <1958400000>;
498 opp-peak-kBps = <4068000 48537600>;
501 cpu0_opp_2016mhz: opp-2016000000 {
502 opp-hz = /bits/ 64 <2016000000>;
503 opp-peak-kBps = <6220000 48537600>;
507 cpu4_opp_table: opp-table-cpu4 {
508 compatible = "operating-points-v2";
509 opp-shared;
511 cpu4_opp_691mhz: opp-691200000 {
512 opp-hz = /bits/ 64 <691200000>;
513 opp-peak-kBps = <1804000 9600000>;
516 cpu4_opp_941mhz: opp-940800000 {
517 opp-hz = /bits/ 64 <940800000>;
518 opp-peak-kBps = <2188000 17817600>;
521 cpu4_opp_1229mhz: opp-1228800000 {
522 opp-hz = /bits/ 64 <1228800000>;
523 opp-peak-kBps = <4068000 24576000>;
526 cpu4_opp_1344mhz: opp-1344000000 {
527 opp-hz = /bits/ 64 <1344000000>;
528 opp-peak-kBps = <4068000 24576000>;
531 cpu4_opp_1517mhz: opp-1516800000 {
532 opp-hz = /bits/ 64 <1516800000>;
533 opp-peak-kBps = <4068000 24576000>;
536 cpu4_opp_1651mhz: opp-1651200000 {
537 opp-hz = /bits/ 64 <1651200000>;
538 opp-peak-kBps = <6220000 38092800>;
541 cpu4_opp_1901mhz: opp-1900800000 {
542 opp-hz = /bits/ 64 <1900800000>;
543 opp-peak-kBps = <6220000 44851200>;
546 cpu4_opp_2054mhz: opp-2054400000 {
547 opp-hz = /bits/ 64 <2054400000>;
548 opp-peak-kBps = <6220000 44851200>;
551 cpu4_opp_2112mhz: opp-2112000000 {
552 opp-hz = /bits/ 64 <2112000000>;
553 opp-peak-kBps = <6220000 44851200>;
556 cpu4_opp_2131mhz: opp-2131200000 {
557 opp-hz = /bits/ 64 <2131200000>;
558 opp-peak-kBps = <6220000 44851200>;
561 cpu4_opp_2208mhz: opp-2208000000 {
562 opp-hz = /bits/ 64 <2208000000>;
563 opp-peak-kBps = <6220000 44851200>;
566 cpu4_opp_2400mhz: opp-2400000000 {
567 opp-hz = /bits/ 64 <2400000000>;
568 opp-peak-kBps = <8532000 48537600>;
571 cpu4_opp_2611mhz: opp-2611200000 {
572 opp-hz = /bits/ 64 <2611200000>;
573 opp-peak-kBps = <8532000 48537600>;
577 cpu7_opp_table: opp-table-cpu7 {
578 compatible = "operating-points-v2";
579 opp-shared;
581 cpu7_opp_806mhz: opp-806400000 {
582 opp-hz = /bits/ 64 <806400000>;
583 opp-peak-kBps = <1804000 9600000>;
586 cpu7_opp_1056mhz: opp-1056000000 {
587 opp-hz = /bits/ 64 <1056000000>;
588 opp-peak-kBps = <2188000 17817600>;
591 cpu7_opp_1325mhz: opp-1324800000 {
592 opp-hz = /bits/ 64 <1324800000>;
593 opp-peak-kBps = <4068000 24576000>;
596 cpu7_opp_1517mhz: opp-1516800000 {
597 opp-hz = /bits/ 64 <1516800000>;
598 opp-peak-kBps = <4068000 24576000>;
601 cpu7_opp_1766mhz: opp-1766400000 {
602 opp-hz = /bits/ 64 <1766400000>;
603 opp-peak-kBps = <6220000 38092800>;
606 cpu7_opp_1862mhz: opp-1862400000 {
607 opp-hz = /bits/ 64 <1862400000>;
608 opp-peak-kBps = <6220000 38092800>;
611 cpu7_opp_2035mhz: opp-2035200000 {
612 opp-hz = /bits/ 64 <2035200000>;
613 opp-peak-kBps = <6220000 38092800>;
616 cpu7_opp_2112mhz: opp-2112000000 {
617 opp-hz = /bits/ 64 <2112000000>;
618 opp-peak-kBps = <6220000 44851200>;
621 cpu7_opp_2208mhz: opp-2208000000 {
622 opp-hz = /bits/ 64 <2208000000>;
623 opp-peak-kBps = <6220000 44851200>;
626 cpu7_opp_2381mhz: opp-2380800000 {
627 opp-hz = /bits/ 64 <2380800000>;
628 opp-peak-kBps = <6832000 44851200>;
631 cpu7_opp_2400mhz: opp-2400000000 {
632 opp-hz = /bits/ 64 <2400000000>;
633 opp-peak-kBps = <8532000 48537600>;
636 cpu7_opp_2515mhz: opp-2515200000 {
637 opp-hz = /bits/ 64 <2515200000>;
638 opp-peak-kBps = <8532000 48537600>;
641 cpu7_opp_2707mhz: opp-2707200000 {
642 opp-hz = /bits/ 64 <2707200000>;
643 opp-peak-kBps = <8532000 48537600>;
646 cpu7_opp_3014mhz: opp-3014400000 {
647 opp-hz = /bits/ 64 <3014400000>;
648 opp-peak-kBps = <8532000 48537600>;
653 compatible = "usb-c-connector";
658 remote-endpoint = <&eud_con>;
672 compatible = "qcom,scm-sc7280", "qcom,scm";
677 compatible = "qcom,sc7280-clk-virt";
678 #interconnect-cells = <2>;
679 qcom,bcm-voters = <&apps_bcm_voter>;
684 memory-region = <&smem_mem>;
688 smp2p-adsp {
691 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
697 qcom,local-pid = <0>;
698 qcom,remote-pid = <2>;
700 adsp_smp2p_out: master-kernel {
701 qcom,entry-name = "master-kernel";
702 #qcom,smem-state-cells = <1>;
705 adsp_smp2p_in: slave-kernel {
706 qcom,entry-name = "slave-kernel";
707 interrupt-controller;
708 #interrupt-cells = <2>;
712 smp2p-cdsp {
715 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
721 qcom,local-pid = <0>;
722 qcom,remote-pid = <5>;
724 cdsp_smp2p_out: master-kernel {
725 qcom,entry-name = "master-kernel";
726 #qcom,smem-state-cells = <1>;
729 cdsp_smp2p_in: slave-kernel {
730 qcom,entry-name = "slave-kernel";
731 interrupt-controller;
732 #interrupt-cells = <2>;
736 smp2p-mpss {
739 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
745 qcom,local-pid = <0>;
746 qcom,remote-pid = <1>;
748 modem_smp2p_out: master-kernel {
749 qcom,entry-name = "master-kernel";
750 #qcom,smem-state-cells = <1>;
753 modem_smp2p_in: slave-kernel {
754 qcom,entry-name = "slave-kernel";
755 interrupt-controller;
756 #interrupt-cells = <2>;
759 ipa_smp2p_out: ipa-ap-to-modem {
760 qcom,entry-name = "ipa";
761 #qcom,smem-state-cells = <1>;
764 ipa_smp2p_in: ipa-modem-to-ap {
765 qcom,entry-name = "ipa";
766 interrupt-controller;
767 #interrupt-cells = <2>;
771 smp2p-wpss {
774 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
780 qcom,local-pid = <0>;
781 qcom,remote-pid = <13>;
783 wpss_smp2p_out: master-kernel {
784 qcom,entry-name = "master-kernel";
785 #qcom,smem-state-cells = <1>;
788 wpss_smp2p_in: slave-kernel {
789 qcom,entry-name = "slave-kernel";
790 interrupt-controller;
791 #interrupt-cells = <2>;
794 wlan_smp2p_out: wlan-ap-to-wpss {
795 qcom,entry-name = "wlan";
796 #qcom,smem-state-cells = <1>;
799 wlan_smp2p_in: wlan-wpss-to-ap {
800 qcom,entry-name = "wlan";
801 interrupt-controller;
802 #interrupt-cells = <2>;
807 compatible = "arm,armv8-pmuv3";
812 compatible = "arm,psci-1.0";
816 qspi_opp_table: opp-table-qspi {
817 compatible = "operating-points-v2";
819 opp-75000000 {
820 opp-hz = /bits/ 64 <75000000>;
821 required-opps = <&rpmhpd_opp_low_svs>;
824 opp-150000000 {
825 opp-hz = /bits/ 64 <150000000>;
826 required-opps = <&rpmhpd_opp_svs>;
829 opp-200000000 {
830 opp-hz = /bits/ 64 <200000000>;
831 required-opps = <&rpmhpd_opp_svs_l1>;
834 opp-300000000 {
835 opp-hz = /bits/ 64 <300000000>;
836 required-opps = <&rpmhpd_opp_nom>;
840 qup_opp_table: opp-table-qup {
841 compatible = "operating-points-v2";
843 opp-75000000 {
844 opp-hz = /bits/ 64 <75000000>;
845 required-opps = <&rpmhpd_opp_low_svs>;
848 opp-100000000 {
849 opp-hz = /bits/ 64 <100000000>;
850 required-opps = <&rpmhpd_opp_svs>;
853 opp-128000000 {
854 opp-hz = /bits/ 64 <128000000>;
855 required-opps = <&rpmhpd_opp_nom>;
860 #address-cells = <2>;
861 #size-cells = <2>;
863 dma-ranges = <0 0 0 0 0x10 0>;
864 compatible = "simple-bus";
866 gcc: clock-controller@100000 {
867 compatible = "qcom,gcc-sc7280";
873 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
878 #clock-cells = <1>;
879 #reset-cells = <1>;
880 #power-domain-cells = <1>;
881 power-domains = <&rpmhpd SC7280_CX>;
885 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
888 interrupt-controller;
889 #interrupt-cells = <3>;
890 #mbox-cells = <2>;
894 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
900 clock-names = "core";
901 power-domains = <&rpmhpd SC7280_MX>;
902 #address-cells = <1>;
903 #size-cells = <1>;
912 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
913 pinctrl-names = "default", "sleep";
914 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
915 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
920 reg-names = "hc", "cqhci";
925 interrupt-names = "hc_irq", "pwr_irq";
930 clock-names = "iface", "core", "xo";
933 interconnect-names = "sdhc-ddr","cpu-sdhc";
934 power-domains = <&rpmhpd SC7280_CX>;
935 operating-points-v2 = <&sdhc1_opp_table>;
937 bus-width = <8>;
938 supports-cqe;
940 qcom,dll-config = <0x0007642c>;
941 qcom,ddr-config = <0x80040868>;
943 mmc-ddr-1_8v;
944 mmc-hs200-1_8v;
945 mmc-hs400-1_8v;
946 mmc-hs400-enhanced-strobe;
950 sdhc1_opp_table: opp-table {
951 compatible = "operating-points-v2";
953 opp-100000000 {
954 opp-hz = /bits/ 64 <100000000>;
955 required-opps = <&rpmhpd_opp_low_svs>;
956 opp-peak-kBps = <1800000 400000>;
957 opp-avg-kBps = <100000 0>;
960 opp-384000000 {
961 opp-hz = /bits/ 64 <384000000>;
962 required-opps = <&rpmhpd_opp_nom>;
963 opp-peak-kBps = <5400000 1600000>;
964 opp-avg-kBps = <390000 0>;
969 gpi_dma0: dma-controller@900000 {
970 #dma-cells = <3>;
971 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
985 dma-channels = <12>;
986 dma-channel-mask = <0x7f>;
992 compatible = "qcom,geni-se-qup";
996 clock-names = "m-ahb", "s-ahb";
997 #address-cells = <2>;
998 #size-cells = <2>;
1004 compatible = "qcom,geni-i2c";
1007 clock-names = "se";
1008 pinctrl-names = "default";
1009 pinctrl-0 = <&qup_i2c0_data_clk>;
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 interconnect-names = "qup-core", "qup-config",
1017 "qup-memory";
1018 power-domains = <&rpmhpd SC7280_CX>;
1019 required-opps = <&rpmhpd_opp_low_svs>;
1022 dma-names = "tx", "rx";
1027 compatible = "qcom,geni-spi";
1030 clock-names = "se";
1031 pinctrl-names = "default";
1032 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 power-domains = <&rpmhpd SC7280_CX>;
1037 operating-points-v2 = <&qup_opp_table>;
1040 interconnect-names = "qup-core", "qup-config";
1043 dma-names = "tx", "rx";
1048 compatible = "qcom,geni-uart";
1051 clock-names = "se";
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1055 power-domains = <&rpmhpd SC7280_CX>;
1056 operating-points-v2 = <&qup_opp_table>;
1059 interconnect-names = "qup-core", "qup-config";
1064 compatible = "qcom,geni-i2c";
1067 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_i2c1_data_clk>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1076 interconnect-names = "qup-core", "qup-config",
1077 "qup-memory";
1078 power-domains = <&rpmhpd SC7280_CX>;
1079 required-opps = <&rpmhpd_opp_low_svs>;
1082 dma-names = "tx", "rx";
1087 compatible = "qcom,geni-spi";
1090 clock-names = "se";
1091 pinctrl-names = "default";
1092 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096 power-domains = <&rpmhpd SC7280_CX>;
1097 operating-points-v2 = <&qup_opp_table>;
1100 interconnect-names = "qup-core", "qup-config";
1103 dma-names = "tx", "rx";
1108 compatible = "qcom,geni-uart";
1111 clock-names = "se";
1112 pinctrl-names = "default";
1113 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1115 power-domains = <&rpmhpd SC7280_CX>;
1116 operating-points-v2 = <&qup_opp_table>;
1119 interconnect-names = "qup-core", "qup-config";
1124 compatible = "qcom,geni-i2c";
1127 clock-names = "se";
1128 pinctrl-names = "default";
1129 pinctrl-0 = <&qup_i2c2_data_clk>;
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1136 interconnect-names = "qup-core", "qup-config",
1137 "qup-memory";
1138 power-domains = <&rpmhpd SC7280_CX>;
1139 required-opps = <&rpmhpd_opp_low_svs>;
1142 dma-names = "tx", "rx";
1147 compatible = "qcom,geni-spi";
1150 clock-names = "se";
1151 pinctrl-names = "default";
1152 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1156 power-domains = <&rpmhpd SC7280_CX>;
1157 operating-points-v2 = <&qup_opp_table>;
1160 interconnect-names = "qup-core", "qup-config";
1163 dma-names = "tx", "rx";
1168 compatible = "qcom,geni-uart";
1171 clock-names = "se";
1172 pinctrl-names = "default";
1173 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1175 power-domains = <&rpmhpd SC7280_CX>;
1176 operating-points-v2 = <&qup_opp_table>;
1179 interconnect-names = "qup-core", "qup-config";
1184 compatible = "qcom,geni-i2c";
1187 clock-names = "se";
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&qup_i2c3_data_clk>;
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1196 interconnect-names = "qup-core", "qup-config",
1197 "qup-memory";
1198 power-domains = <&rpmhpd SC7280_CX>;
1199 required-opps = <&rpmhpd_opp_low_svs>;
1202 dma-names = "tx", "rx";
1207 compatible = "qcom,geni-spi";
1210 clock-names = "se";
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 power-domains = <&rpmhpd SC7280_CX>;
1217 operating-points-v2 = <&qup_opp_table>;
1220 interconnect-names = "qup-core", "qup-config";
1223 dma-names = "tx", "rx";
1228 compatible = "qcom,geni-uart";
1231 clock-names = "se";
1232 pinctrl-names = "default";
1233 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1235 power-domains = <&rpmhpd SC7280_CX>;
1236 operating-points-v2 = <&qup_opp_table>;
1239 interconnect-names = "qup-core", "qup-config";
1244 compatible = "qcom,geni-i2c";
1247 clock-names = "se";
1248 pinctrl-names = "default";
1249 pinctrl-0 = <&qup_i2c4_data_clk>;
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1256 interconnect-names = "qup-core", "qup-config",
1257 "qup-memory";
1258 power-domains = <&rpmhpd SC7280_CX>;
1259 required-opps = <&rpmhpd_opp_low_svs>;
1262 dma-names = "tx", "rx";
1267 compatible = "qcom,geni-spi";
1270 clock-names = "se";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 power-domains = <&rpmhpd SC7280_CX>;
1277 operating-points-v2 = <&qup_opp_table>;
1280 interconnect-names = "qup-core", "qup-config";
1283 dma-names = "tx", "rx";
1288 compatible = "qcom,geni-uart";
1291 clock-names = "se";
1292 pinctrl-names = "default";
1293 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1295 power-domains = <&rpmhpd SC7280_CX>;
1296 operating-points-v2 = <&qup_opp_table>;
1299 interconnect-names = "qup-core", "qup-config";
1304 compatible = "qcom,geni-i2c";
1307 clock-names = "se";
1308 pinctrl-names = "default";
1309 pinctrl-0 = <&qup_i2c5_data_clk>;
1311 #address-cells = <1>;
1312 #size-cells = <0>;
1316 interconnect-names = "qup-core", "qup-config",
1317 "qup-memory";
1318 power-domains = <&rpmhpd SC7280_CX>;
1319 required-opps = <&rpmhpd_opp_low_svs>;
1322 dma-names = "tx", "rx";
1327 compatible = "qcom,geni-spi";
1330 clock-names = "se";
1331 pinctrl-names = "default";
1332 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 power-domains = <&rpmhpd SC7280_CX>;
1337 operating-points-v2 = <&qup_opp_table>;
1340 interconnect-names = "qup-core", "qup-config";
1343 dma-names = "tx", "rx";
1348 compatible = "qcom,geni-uart";
1351 clock-names = "se";
1352 pinctrl-names = "default";
1353 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1355 power-domains = <&rpmhpd SC7280_CX>;
1356 operating-points-v2 = <&qup_opp_table>;
1359 interconnect-names = "qup-core", "qup-config";
1364 compatible = "qcom,geni-i2c";
1367 clock-names = "se";
1368 pinctrl-names = "default";
1369 pinctrl-0 = <&qup_i2c6_data_clk>;
1371 #address-cells = <1>;
1372 #size-cells = <0>;
1376 interconnect-names = "qup-core", "qup-config",
1377 "qup-memory";
1378 power-domains = <&rpmhpd SC7280_CX>;
1379 required-opps = <&rpmhpd_opp_low_svs>;
1382 dma-names = "tx", "rx";
1387 compatible = "qcom,geni-spi";
1390 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 power-domains = <&rpmhpd SC7280_CX>;
1397 operating-points-v2 = <&qup_opp_table>;
1400 interconnect-names = "qup-core", "qup-config";
1403 dma-names = "tx", "rx";
1408 compatible = "qcom,geni-uart";
1411 clock-names = "se";
1412 pinctrl-names = "default";
1413 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1415 power-domains = <&rpmhpd SC7280_CX>;
1416 operating-points-v2 = <&qup_opp_table>;
1419 interconnect-names = "qup-core", "qup-config";
1424 compatible = "qcom,geni-i2c";
1427 clock-names = "se";
1428 pinctrl-names = "default";
1429 pinctrl-0 = <&qup_i2c7_data_clk>;
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1436 interconnect-names = "qup-core", "qup-config",
1437 "qup-memory";
1438 power-domains = <&rpmhpd SC7280_CX>;
1439 required-opps = <&rpmhpd_opp_low_svs>;
1442 dma-names = "tx", "rx";
1447 compatible = "qcom,geni-spi";
1450 clock-names = "se";
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1454 #address-cells = <1>;
1455 #size-cells = <0>;
1456 power-domains = <&rpmhpd SC7280_CX>;
1457 operating-points-v2 = <&qup_opp_table>;
1460 interconnect-names = "qup-core", "qup-config";
1463 dma-names = "tx", "rx";
1468 compatible = "qcom,geni-uart";
1471 clock-names = "se";
1472 pinctrl-names = "default";
1473 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1475 power-domains = <&rpmhpd SC7280_CX>;
1476 operating-points-v2 = <&qup_opp_table>;
1479 interconnect-names = "qup-core", "qup-config";
1484 gpi_dma1: dma-controller@a00000 {
1485 #dma-cells = <3>;
1486 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1500 dma-channels = <12>;
1501 dma-channel-mask = <0x1e>;
1507 compatible = "qcom,geni-se-qup";
1511 clock-names = "m-ahb", "s-ahb";
1512 #address-cells = <2>;
1513 #size-cells = <2>;
1519 compatible = "qcom,geni-i2c";
1522 clock-names = "se";
1523 pinctrl-names = "default";
1524 pinctrl-0 = <&qup_i2c8_data_clk>;
1526 #address-cells = <1>;
1527 #size-cells = <0>;
1531 interconnect-names = "qup-core", "qup-config",
1532 "qup-memory";
1533 power-domains = <&rpmhpd SC7280_CX>;
1534 required-opps = <&rpmhpd_opp_low_svs>;
1537 dma-names = "tx", "rx";
1542 compatible = "qcom,geni-spi";
1545 clock-names = "se";
1546 pinctrl-names = "default";
1547 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1549 #address-cells = <1>;
1550 #size-cells = <0>;
1551 power-domains = <&rpmhpd SC7280_CX>;
1552 operating-points-v2 = <&qup_opp_table>;
1555 interconnect-names = "qup-core", "qup-config";
1558 dma-names = "tx", "rx";
1563 compatible = "qcom,geni-uart";
1566 clock-names = "se";
1567 pinctrl-names = "default";
1568 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1570 power-domains = <&rpmhpd SC7280_CX>;
1571 operating-points-v2 = <&qup_opp_table>;
1574 interconnect-names = "qup-core", "qup-config";
1579 compatible = "qcom,geni-i2c";
1582 clock-names = "se";
1583 pinctrl-names = "default";
1584 pinctrl-0 = <&qup_i2c9_data_clk>;
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1591 interconnect-names = "qup-core", "qup-config",
1592 "qup-memory";
1593 power-domains = <&rpmhpd SC7280_CX>;
1594 required-opps = <&rpmhpd_opp_low_svs>;
1597 dma-names = "tx", "rx";
1602 compatible = "qcom,geni-spi";
1605 clock-names = "se";
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1609 #address-cells = <1>;
1610 #size-cells = <0>;
1611 power-domains = <&rpmhpd SC7280_CX>;
1612 operating-points-v2 = <&qup_opp_table>;
1615 interconnect-names = "qup-core", "qup-config";
1618 dma-names = "tx", "rx";
1623 compatible = "qcom,geni-uart";
1626 clock-names = "se";
1627 pinctrl-names = "default";
1628 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1630 power-domains = <&rpmhpd SC7280_CX>;
1631 operating-points-v2 = <&qup_opp_table>;
1634 interconnect-names = "qup-core", "qup-config";
1639 compatible = "qcom,geni-i2c";
1642 clock-names = "se";
1643 pinctrl-names = "default";
1644 pinctrl-0 = <&qup_i2c10_data_clk>;
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1651 interconnect-names = "qup-core", "qup-config",
1652 "qup-memory";
1653 power-domains = <&rpmhpd SC7280_CX>;
1654 required-opps = <&rpmhpd_opp_low_svs>;
1657 dma-names = "tx", "rx";
1662 compatible = "qcom,geni-spi";
1665 clock-names = "se";
1666 pinctrl-names = "default";
1667 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1669 #address-cells = <1>;
1670 #size-cells = <0>;
1671 power-domains = <&rpmhpd SC7280_CX>;
1672 operating-points-v2 = <&qup_opp_table>;
1675 interconnect-names = "qup-core", "qup-config";
1678 dma-names = "tx", "rx";
1683 compatible = "qcom,geni-uart";
1686 clock-names = "se";
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1690 power-domains = <&rpmhpd SC7280_CX>;
1691 operating-points-v2 = <&qup_opp_table>;
1694 interconnect-names = "qup-core", "qup-config";
1699 compatible = "qcom,geni-i2c";
1702 clock-names = "se";
1703 pinctrl-names = "default";
1704 pinctrl-0 = <&qup_i2c11_data_clk>;
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1711 interconnect-names = "qup-core", "qup-config",
1712 "qup-memory";
1713 power-domains = <&rpmhpd SC7280_CX>;
1714 required-opps = <&rpmhpd_opp_low_svs>;
1717 dma-names = "tx", "rx";
1722 compatible = "qcom,geni-spi";
1725 clock-names = "se";
1726 pinctrl-names = "default";
1727 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1731 power-domains = <&rpmhpd SC7280_CX>;
1732 operating-points-v2 = <&qup_opp_table>;
1735 interconnect-names = "qup-core", "qup-config";
1738 dma-names = "tx", "rx";
1743 compatible = "qcom,geni-uart";
1746 clock-names = "se";
1747 pinctrl-names = "default";
1748 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1750 power-domains = <&rpmhpd SC7280_CX>;
1751 operating-points-v2 = <&qup_opp_table>;
1754 interconnect-names = "qup-core", "qup-config";
1759 compatible = "qcom,geni-i2c";
1762 clock-names = "se";
1763 pinctrl-names = "default";
1764 pinctrl-0 = <&qup_i2c12_data_clk>;
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1771 interconnect-names = "qup-core", "qup-config",
1772 "qup-memory";
1773 power-domains = <&rpmhpd SC7280_CX>;
1774 required-opps = <&rpmhpd_opp_low_svs>;
1777 dma-names = "tx", "rx";
1782 compatible = "qcom,geni-spi";
1785 clock-names = "se";
1786 pinctrl-names = "default";
1787 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1789 #address-cells = <1>;
1790 #size-cells = <0>;
1791 power-domains = <&rpmhpd SC7280_CX>;
1792 operating-points-v2 = <&qup_opp_table>;
1795 interconnect-names = "qup-core", "qup-config";
1798 dma-names = "tx", "rx";
1803 compatible = "qcom,geni-uart";
1806 clock-names = "se";
1807 pinctrl-names = "default";
1808 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1810 power-domains = <&rpmhpd SC7280_CX>;
1811 operating-points-v2 = <&qup_opp_table>;
1814 interconnect-names = "qup-core", "qup-config";
1819 compatible = "qcom,geni-i2c";
1822 clock-names = "se";
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&qup_i2c13_data_clk>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1831 interconnect-names = "qup-core", "qup-config",
1832 "qup-memory";
1833 power-domains = <&rpmhpd SC7280_CX>;
1834 required-opps = <&rpmhpd_opp_low_svs>;
1837 dma-names = "tx", "rx";
1842 compatible = "qcom,geni-spi";
1845 clock-names = "se";
1846 pinctrl-names = "default";
1847 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1849 #address-cells = <1>;
1850 #size-cells = <0>;
1851 power-domains = <&rpmhpd SC7280_CX>;
1852 operating-points-v2 = <&qup_opp_table>;
1855 interconnect-names = "qup-core", "qup-config";
1858 dma-names = "tx", "rx";
1863 compatible = "qcom,geni-uart";
1866 clock-names = "se";
1867 pinctrl-names = "default";
1868 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1870 power-domains = <&rpmhpd SC7280_CX>;
1871 operating-points-v2 = <&qup_opp_table>;
1874 interconnect-names = "qup-core", "qup-config";
1879 compatible = "qcom,geni-i2c";
1882 clock-names = "se";
1883 pinctrl-names = "default";
1884 pinctrl-0 = <&qup_i2c14_data_clk>;
1886 #address-cells = <1>;
1887 #size-cells = <0>;
1891 interconnect-names = "qup-core", "qup-config",
1892 "qup-memory";
1893 power-domains = <&rpmhpd SC7280_CX>;
1894 required-opps = <&rpmhpd_opp_low_svs>;
1897 dma-names = "tx", "rx";
1902 compatible = "qcom,geni-spi";
1905 clock-names = "se";
1906 pinctrl-names = "default";
1907 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1909 #address-cells = <1>;
1910 #size-cells = <0>;
1911 power-domains = <&rpmhpd SC7280_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1915 interconnect-names = "qup-core", "qup-config";
1918 dma-names = "tx", "rx";
1923 compatible = "qcom,geni-uart";
1926 clock-names = "se";
1927 pinctrl-names = "default";
1928 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1930 power-domains = <&rpmhpd SC7280_CX>;
1931 operating-points-v2 = <&qup_opp_table>;
1934 interconnect-names = "qup-core", "qup-config";
1939 compatible = "qcom,geni-i2c";
1942 clock-names = "se";
1943 pinctrl-names = "default";
1944 pinctrl-0 = <&qup_i2c15_data_clk>;
1946 #address-cells = <1>;
1947 #size-cells = <0>;
1951 interconnect-names = "qup-core", "qup-config",
1952 "qup-memory";
1953 power-domains = <&rpmhpd SC7280_CX>;
1954 required-opps = <&rpmhpd_opp_low_svs>;
1957 dma-names = "tx", "rx";
1962 compatible = "qcom,geni-spi";
1965 clock-names = "se";
1966 pinctrl-names = "default";
1967 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1969 #address-cells = <1>;
1970 #size-cells = <0>;
1971 power-domains = <&rpmhpd SC7280_CX>;
1972 operating-points-v2 = <&qup_opp_table>;
1975 interconnect-names = "qup-core", "qup-config";
1978 dma-names = "tx", "rx";
1983 compatible = "qcom,geni-uart";
1986 clock-names = "se";
1987 pinctrl-names = "default";
1988 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1990 power-domains = <&rpmhpd SC7280_CX>;
1991 operating-points-v2 = <&qup_opp_table>;
1994 interconnect-names = "qup-core", "qup-config";
2001 compatible = "qcom,sc7280-cnoc2";
2002 #interconnect-cells = <2>;
2003 qcom,bcm-voters = <&apps_bcm_voter>;
2008 compatible = "qcom,sc7280-cnoc3";
2009 #interconnect-cells = <2>;
2010 qcom,bcm-voters = <&apps_bcm_voter>;
2015 compatible = "qcom,sc7280-mc-virt";
2016 #interconnect-cells = <2>;
2017 qcom,bcm-voters = <&apps_bcm_voter>;
2022 compatible = "qcom,sc7280-system-noc";
2023 #interconnect-cells = <2>;
2024 qcom,bcm-voters = <&apps_bcm_voter>;
2028 compatible = "qcom,sc7280-aggre1-noc";
2030 #interconnect-cells = <2>;
2031 qcom,bcm-voters = <&apps_bcm_voter>;
2036 compatible = "qcom,sc7280-aggre2-noc";
2037 #interconnect-cells = <2>;
2038 qcom,bcm-voters = <&apps_bcm_voter>;
2043 compatible = "qcom,sc7280-mmss-noc";
2044 #interconnect-cells = <2>;
2045 qcom,bcm-voters = <&apps_bcm_voter>;
2049 compatible = "qcom,wcn6750-wifi";
2085 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2087 qcom,smem-states = <&wlan_smp2p_out 0>;
2088 qcom,smem-state-names = "wlan-smp2p-out";
2092 compatible = "qcom,pcie-sc7280";
2099 reg-names = "parf", "dbi", "elbi", "atu", "config";
2101 linux,pci-domain = <1>;
2102 bus-range = <0x00 0xff>;
2103 num-lanes = <2>;
2105 #address-cells = <3>;
2106 #size-cells = <2>;
2112 interrupt-names = "msi";
2113 #interrupt-cells = <1>;
2114 interrupt-map-mask = <0 0 0 0x7>;
2115 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2134 clock-names = "pipe",
2148 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2149 assigned-clock-rates = <19200000>;
2152 reset-names = "pci";
2154 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2157 phy-names = "pciephy";
2159 pinctrl-names = "default";
2160 pinctrl-0 = <&pcie1_clkreq_n>;
2162 dma-coherent;
2164 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2171 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2173 #address-cells = <2>;
2174 #size-cells = <2>;
2180 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2183 reset-names = "phy";
2185 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2186 assigned-clock-rates = <100000000>;
2198 clock-names = "pipe0";
2200 #phy-cells = <0>;
2201 #clock-cells = <0>;
2202 clock-output-names = "pcie_1_pipe_clk";
2207 compatible = "qcom,sc7280-ipa";
2214 reg-names = "ipa-reg",
2215 "ipa-shared",
2218 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2222 interrupt-names = "ipa",
2224 "ipa-clock-query",
2225 "ipa-setup-ready";
2228 clock-names = "core";
2232 interconnect-names = "memory",
2237 qcom,smem-states = <&ipa_smp2p_out 0>,
2239 qcom,smem-state-names = "ipa-clock-enabled-valid",
2240 "ipa-clock-enabled";
2246 compatible = "qcom,tcsr-mutex";
2248 #hwlock-cells = <1>;
2252 compatible = "qcom,sc7280-tcsr", "syscon";
2257 compatible = "qcom,sc7280-tcsr", "syscon";
2262 compatible = "qcom,sc7280-lpasscc";
2265 reg-names = "qdsp6ss", "top_cc";
2267 clock-names = "iface";
2268 #clock-cells = <1>;
2272 compatible = "qcom,sc7280-lpass-rx-macro";
2275 pinctrl-names = "default";
2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2281 clock-names = "mclk", "npl", "fsgen";
2283 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2285 power-domain-names = "macro", "dcodec";
2287 #clock-cells = <0>;
2288 #sound-dai-cells = <1>;
2294 compatible = "qcom,soundwire-v1.6.0";
2299 clock-names = "iface";
2301 qcom,din-ports = <0>;
2302 qcom,dout-ports = <5>;
2305 reset-names = "swr_audio_cgcr";
2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2317 #sound-dai-cells = <1>;
2318 #address-cells = <2>;
2319 #size-cells = <0>;
2325 compatible = "qcom,sc7280-lpass-tx-macro";
2328 pinctrl-names = "default";
2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2334 clock-names = "mclk", "npl", "fsgen";
2336 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2338 power-domain-names = "macro", "dcodec";
2340 #clock-cells = <0>;
2341 #sound-dai-cells = <1>;
2347 compatible = "qcom,soundwire-v1.6.0";
2350 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2353 clock-names = "iface";
2355 qcom,din-ports = <3>;
2356 qcom,dout-ports = <0>;
2359 reset-names = "swr_audio_cgcr";
2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2371 #sound-dai-cells = <1>;
2372 #address-cells = <2>;
2373 #size-cells = <0>;
2378 lpass_audiocc: clock-controller@3300000 {
2379 compatible = "qcom,sc7280-lpassaudiocc";
2384 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2385 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2386 #clock-cells = <1>;
2387 #power-domain-cells = <1>;
2388 #reset-cells = <1>;
2392 compatible = "qcom,sc7280-lpass-va-macro";
2395 pinctrl-names = "default";
2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2399 clock-names = "mclk";
2401 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2403 power-domain-names = "macro", "dcodec";
2405 #clock-cells = <0>;
2406 #sound-dai-cells = <1>;
2411 lpass_aon: clock-controller@3380000 {
2412 compatible = "qcom,sc7280-lpassaoncc";
2417 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2418 #clock-cells = <1>;
2419 #power-domain-cells = <1>;
2422 lpass_core: clock-controller@3900000 {
2423 compatible = "qcom,sc7280-lpasscorecc";
2426 clock-names = "bi_tcxo";
2427 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2428 #clock-cells = <1>;
2429 #power-domain-cells = <1>;
2433 compatible = "qcom,sc7280-lpass-cpu";
2441 reg-names = "lpass-hdmiif",
2442 "lpass-lpaif",
2443 "lpass-rxtx-cdc-dma-lpm",
2444 "lpass-rxtx-lpaif",
2445 "lpass-va-lpaif",
2446 "lpass-va-cdc-dma-lpm";
2452 power-domains = <&rpmhpd SC7280_LCX>;
2453 power-domain-names = "lcx";
2454 required-opps = <&rpmhpd_opp_nom>;
2466 clock-names = "aon_cc_audio_hm_h",
2477 #sound-dai-cells = <1>;
2478 #address-cells = <1>;
2479 #size-cells = <0>;
2485 interrupt-names = "lpass-irq-lpaif",
2486 "lpass-irq-hdmi",
2487 "lpass-irq-vaif",
2488 "lpass-irq-rxtxif";
2493 lpass_hm: clock-controller@3c00000 {
2494 compatible = "qcom,sc7280-lpasshm";
2497 clock-names = "bi_tcxo";
2498 #clock-cells = <1>;
2499 #power-domain-cells = <1>;
2504 compatible = "qcom,sc7280-lpass-ag-noc";
2505 #interconnect-cells = <2>;
2506 qcom,bcm-voters = <&apps_bcm_voter>;
2510 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2513 qcom,adsp-bypass-mode;
2514 gpio-controller;
2515 #gpio-cells = <2>;
2516 gpio-ranges = <&lpass_tlmm 0 0 15>;
2518 lpass_dmic01_clk: dmic01-clk-state {
2523 lpass_dmic01_data: dmic01-data-state {
2528 lpass_dmic23_clk: dmic23-clk-state {
2533 lpass_dmic23_data: dmic23-data-state {
2538 lpass_rx_swr_clk: rx-swr-clk-state {
2543 lpass_rx_swr_data: rx-swr-data-state {
2548 lpass_tx_swr_clk: tx-swr-clk-state {
2553 lpass_tx_swr_data: tx-swr-data-state {
2560 compatible = "qcom,adreno-635.0", "qcom,adreno";
2564 reg-names = "kgsl_3d0_reg_memory",
2569 operating-points-v2 = <&gpu_opp_table>;
2570 qcom,gmu = <&gmu>;
2572 interconnect-names = "gfx-mem";
2573 #cooling-cells = <2>;
2575 nvmem-cells = <&gpu_speed_bin>;
2576 nvmem-cell-names = "speed_bin";
2578 gpu_opp_table: opp-table {
2579 compatible = "operating-points-v2";
2581 opp-315000000 {
2582 opp-hz = /bits/ 64 <315000000>;
2583 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2584 opp-peak-kBps = <1804000>;
2585 opp-supported-hw = <0x03>;
2588 opp-450000000 {
2589 opp-hz = /bits/ 64 <450000000>;
2590 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2591 opp-peak-kBps = <4068000>;
2592 opp-supported-hw = <0x03>;
2596 opp-550000000-0 {
2597 opp-hz = /bits/ 64 <550000000>;
2598 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2599 opp-peak-kBps = <8368000>;
2600 opp-supported-hw = <0x01>;
2603 opp-550000000-1 {
2604 opp-hz = /bits/ 64 <550000000>;
2605 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2606 opp-peak-kBps = <6832000>;
2607 opp-supported-hw = <0x02>;
2610 opp-608000000 {
2611 opp-hz = /bits/ 64 <608000000>;
2612 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2613 opp-peak-kBps = <8368000>;
2614 opp-supported-hw = <0x02>;
2617 opp-700000000 {
2618 opp-hz = /bits/ 64 <700000000>;
2619 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2620 opp-peak-kBps = <8532000>;
2621 opp-supported-hw = <0x02>;
2624 opp-812000000 {
2625 opp-hz = /bits/ 64 <812000000>;
2626 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2627 opp-peak-kBps = <8532000>;
2628 opp-supported-hw = <0x02>;
2631 opp-840000000 {
2632 opp-hz = /bits/ 64 <840000000>;
2633 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2634 opp-peak-kBps = <8532000>;
2635 opp-supported-hw = <0x02>;
2638 opp-900000000 {
2639 opp-hz = /bits/ 64 <900000000>;
2640 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2641 opp-peak-kBps = <8532000>;
2642 opp-supported-hw = <0x02>;
2647 gmu: gmu@3d6a000 { label
2648 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2652 reg-names = "gmu", "rscc", "gmu_pdc";
2655 interrupt-names = "hfi", "gmu";
2663 clock-names = "gmu",
2670 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2672 power-domain-names = "cx",
2675 operating-points-v2 = <&gmu_opp_table>;
2677 gmu_opp_table: opp-table {
2678 compatible = "operating-points-v2";
2680 opp-200000000 {
2681 opp-hz = /bits/ 64 <200000000>;
2682 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2687 gpucc: clock-controller@3d90000 {
2688 compatible = "qcom,sc7280-gpucc";
2693 clock-names = "bi_tcxo",
2696 #clock-cells = <1>;
2697 #reset-cells = <1>;
2698 #power-domain-cells = <1>;
2702 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2708 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2709 "qcom,smmu-500", "arm,mmu-500";
2711 #iommu-cells = <2>;
2712 #global-interrupts = <2>;
2733 clock-names = "gcc_gpu_memnoc_gfx_clk",
2741 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2745 compatible = "qcom,sc7280-mpss-pas";
2747 reg-names = "qdsp6", "rmb";
2749 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2755 interrupt-names = "wdog", "fatal", "ready", "handover",
2756 "stop-ack", "shutdown-ack";
2759 clock-names = "xo";
2761 power-domains = <&rpmhpd SC7280_CX>,
2763 power-domain-names = "cx", "mss";
2765 memory-region = <&mpss_mem>;
2769 qcom,smem-states = <&modem_smp2p_out 0>;
2770 qcom,smem-state-names = "stop";
2774 glink-edge {
2775 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2781 qcom,remote-pid = <1>;
2786 compatible = "arm,coresight-stm", "arm,primecell";
2789 reg-names = "stm-base", "stm-stimulus-base";
2792 clock-names = "apb_pclk";
2794 out-ports {
2797 remote-endpoint = <&funnel0_in7>;
2804 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2808 clock-names = "apb_pclk";
2810 out-ports {
2813 remote-endpoint = <&merge_funnel_in0>;
2818 in-ports {
2819 #address-cells = <1>;
2820 #size-cells = <0>;
2825 remote-endpoint = <&stm_out>;
2832 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2836 clock-names = "apb_pclk";
2838 out-ports {
2841 remote-endpoint = <&merge_funnel_in1>;
2846 in-ports {
2847 #address-cells = <1>;
2848 #size-cells = <0>;
2853 remote-endpoint = <&apss_merge_funnel_out>;
2860 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2864 clock-names = "apb_pclk";
2866 out-ports {
2869 remote-endpoint = <&swao_funnel_in>;
2874 in-ports {
2875 #address-cells = <1>;
2876 #size-cells = <0>;
2881 remote-endpoint = <&funnel0_out>;
2888 remote-endpoint = <&funnel1_out>;
2895 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2899 clock-names = "apb_pclk";
2901 out-ports {
2904 remote-endpoint = <&etr_in>;
2909 in-ports {
2912 remote-endpoint = <&swao_replicator_out>;
2919 compatible = "arm,coresight-tmc", "arm,primecell";
2924 clock-names = "apb_pclk";
2925 arm,scatter-gather;
2927 in-ports {
2930 remote-endpoint = <&replicator_out>;
2937 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2941 clock-names = "apb_pclk";
2943 out-ports {
2946 remote-endpoint = <&etf_in>;
2951 in-ports {
2952 #address-cells = <1>;
2953 #size-cells = <0>;
2958 remote-endpoint = <&merge_funnel_out>;
2965 compatible = "arm,coresight-tmc", "arm,primecell";
2969 clock-names = "apb_pclk";
2971 out-ports {
2974 remote-endpoint = <&swao_replicator_in>;
2979 in-ports {
2982 remote-endpoint = <&swao_funnel_out>;
2989 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2993 clock-names = "apb_pclk";
2994 qcom,replicator-loses-context;
2996 out-ports {
2999 remote-endpoint = <&replicator_in>;
3004 in-ports {
3007 remote-endpoint = <&etf_out>;
3014 compatible = "arm,coresight-etm4x", "arm,primecell";
3020 clock-names = "apb_pclk";
3021 arm,coresight-loses-context-with-cpu;
3022 qcom,skip-power-up;
3024 out-ports {
3027 remote-endpoint = <&apss_funnel_in0>;
3034 compatible = "arm,coresight-etm4x", "arm,primecell";
3040 clock-names = "apb_pclk";
3041 arm,coresight-loses-context-with-cpu;
3042 qcom,skip-power-up;
3044 out-ports {
3047 remote-endpoint = <&apss_funnel_in1>;
3054 compatible = "arm,coresight-etm4x", "arm,primecell";
3060 clock-names = "apb_pclk";
3061 arm,coresight-loses-context-with-cpu;
3062 qcom,skip-power-up;
3064 out-ports {
3067 remote-endpoint = <&apss_funnel_in2>;
3074 compatible = "arm,coresight-etm4x", "arm,primecell";
3080 clock-names = "apb_pclk";
3081 arm,coresight-loses-context-with-cpu;
3082 qcom,skip-power-up;
3084 out-ports {
3087 remote-endpoint = <&apss_funnel_in3>;
3094 compatible = "arm,coresight-etm4x", "arm,primecell";
3100 clock-names = "apb_pclk";
3101 arm,coresight-loses-context-with-cpu;
3102 qcom,skip-power-up;
3104 out-ports {
3107 remote-endpoint = <&apss_funnel_in4>;
3114 compatible = "arm,coresight-etm4x", "arm,primecell";
3120 clock-names = "apb_pclk";
3121 arm,coresight-loses-context-with-cpu;
3122 qcom,skip-power-up;
3124 out-ports {
3127 remote-endpoint = <&apss_funnel_in5>;
3134 compatible = "arm,coresight-etm4x", "arm,primecell";
3140 clock-names = "apb_pclk";
3141 arm,coresight-loses-context-with-cpu;
3142 qcom,skip-power-up;
3144 out-ports {
3147 remote-endpoint = <&apss_funnel_in6>;
3154 compatible = "arm,coresight-etm4x", "arm,primecell";
3160 clock-names = "apb_pclk";
3161 arm,coresight-loses-context-with-cpu;
3162 qcom,skip-power-up;
3164 out-ports {
3167 remote-endpoint = <&apss_funnel_in7>;
3174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3178 clock-names = "apb_pclk";
3180 out-ports {
3183 remote-endpoint = <&apss_merge_funnel_in>;
3188 in-ports {
3189 #address-cells = <1>;
3190 #size-cells = <0>;
3195 remote-endpoint = <&etm0_out>;
3202 remote-endpoint = <&etm1_out>;
3209 remote-endpoint = <&etm2_out>;
3216 remote-endpoint = <&etm3_out>;
3223 remote-endpoint = <&etm4_out>;
3230 remote-endpoint = <&etm5_out>;
3237 remote-endpoint = <&etm6_out>;
3244 remote-endpoint = <&etm7_out>;
3251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3255 clock-names = "apb_pclk";
3257 out-ports {
3260 remote-endpoint = <&funnel1_in4>;
3265 in-ports {
3268 remote-endpoint = <&apss_funnel_out>;
3275 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3276 pinctrl-names = "default", "sleep";
3277 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3278 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3286 interrupt-names = "hc_irq", "pwr_irq";
3291 clock-names = "iface", "core", "xo";
3294 interconnect-names = "sdhc-ddr","cpu-sdhc";
3295 power-domains = <&rpmhpd SC7280_CX>;
3296 operating-points-v2 = <&sdhc2_opp_table>;
3298 bus-width = <4>;
3300 qcom,dll-config = <0x0007642c>;
3304 sdhc2_opp_table: opp-table {
3305 compatible = "operating-points-v2";
3307 opp-100000000 {
3308 opp-hz = /bits/ 64 <100000000>;
3309 required-opps = <&rpmhpd_opp_low_svs>;
3310 opp-peak-kBps = <1800000 400000>;
3311 opp-avg-kBps = <100000 0>;
3314 opp-202000000 {
3315 opp-hz = /bits/ 64 <202000000>;
3316 required-opps = <&rpmhpd_opp_nom>;
3317 opp-peak-kBps = <5400000 1600000>;
3318 opp-avg-kBps = <200000 0>;
3324 compatible = "qcom,sc7280-usb-hs-phy",
3325 "qcom,usb-snps-hs-7nm-phy";
3328 #phy-cells = <0>;
3331 clock-names = "ref";
3337 compatible = "qcom,sc7280-usb-hs-phy",
3338 "qcom,usb-snps-hs-7nm-phy";
3341 #phy-cells = <0>;
3344 clock-names = "ref";
3349 usb_1_qmpphy: phy-wrapper@88e9000 {
3350 compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3351 "qcom,sm8250-qmp-usb3-dp-phy";
3356 #address-cells = <2>;
3357 #size-cells = <2>;
3363 clock-names = "aux", "ref_clk_src", "com_aux";
3367 reset-names = "phy", "common";
3369 usb_1_ssphy: usb3-phy@88e9200 {
3376 #clock-cells = <0>;
3377 #phy-cells = <0>;
3379 clock-names = "pipe0";
3380 clock-output-names = "usb3_phy_pipe_clk_src";
3383 dp_phy: dp-phy@88ea200 {
3389 #phy-cells = <0>;
3390 #clock-cells = <1>;
3395 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3398 #address-cells = <2>;
3399 #size-cells = <2>;
3401 dma-ranges;
3408 clock-names = "cfg_noc",
3414 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3416 assigned-clock-rates = <19200000>, <200000000>;
3418 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3421 interrupt-names = "hs_phy_irq",
3425 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3426 required-opps = <&rpmhpd_opp_nom>;
3432 interconnect-names = "usb-ddr", "apps-usb";
3442 phy-names = "usb2-phy";
3443 maximum-speed = "high-speed";
3444 usb-role-switch;
3448 remote-endpoint = <&eud_ep>;
3455 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3458 #address-cells = <1>;
3459 #size-cells = <0>;
3463 clock-names = "iface", "core";
3466 interconnect-names = "qspi-config";
3467 power-domains = <&rpmhpd SC7280_CX>;
3468 operating-points-v2 = <&qspi_opp_table>;
3473 compatible = "qcom,sc7280-wpss-pil";
3476 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3482 interrupt-names = "wdog", "fatal", "ready", "handover",
3483 "stop-ack", "shutdown-ack";
3489 clock-names = "ahb_bdg", "ahb",
3492 power-domains = <&rpmhpd SC7280_CX>,
3494 power-domain-names = "cx", "mx";
3496 memory-region = <&wpss_mem>;
3500 qcom,smem-states = <&wpss_smp2p_out 0>;
3501 qcom,smem-state-names = "stop";
3505 reset-names = "restart", "pdc_sync";
3507 qcom,halt-regs = <&tcsr_1 0x17000>;
3511 glink-edge {
3512 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3519 qcom,remote-pid = <13>;
3524 compatible = "qcom,sc7280-llcc-bwmon";
3531 operating-points-v2 = <&llcc_bwmon_opp_table>;
3533 llcc_bwmon_opp_table: opp-table {
3534 compatible = "operating-points-v2";
3536 opp-0 {
3537 opp-peak-kBps = <800000>;
3539 opp-1 {
3540 opp-peak-kBps = <1804000>;
3542 opp-2 {
3543 opp-peak-kBps = <2188000>;
3545 opp-3 {
3546 opp-peak-kBps = <3072000>;
3548 opp-4 {
3549 opp-peak-kBps = <4068000>;
3551 opp-5 {
3552 opp-peak-kBps = <6220000>;
3554 opp-6 {
3555 opp-peak-kBps = <6832000>;
3557 opp-7 {
3558 opp-peak-kBps = <8532000>;
3564 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3570 operating-points-v2 = <&cpu_bwmon_opp_table>;
3572 cpu_bwmon_opp_table: opp-table {
3573 compatible = "operating-points-v2";
3575 opp-0 {
3576 opp-peak-kBps = <2400000>;
3578 opp-1 {
3579 opp-peak-kBps = <4800000>;
3581 opp-2 {
3582 opp-peak-kBps = <7456000>;
3584 opp-3 {
3585 opp-peak-kBps = <9600000>;
3587 opp-4 {
3588 opp-peak-kBps = <12896000>;
3590 opp-5 {
3591 opp-peak-kBps = <14928000>;
3593 opp-6 {
3594 opp-peak-kBps = <17056000>;
3601 compatible = "qcom,sc7280-dc-noc";
3602 #interconnect-cells = <2>;
3603 qcom,bcm-voters = <&apps_bcm_voter>;
3608 compatible = "qcom,sc7280-gem-noc";
3609 #interconnect-cells = <2>;
3610 qcom,bcm-voters = <&apps_bcm_voter>;
3613 system-cache-controller@9200000 {
3614 compatible = "qcom,sc7280-llcc";
3617 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3622 compatible = "qcom,sc7280-eud", "qcom,eud";
3625 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3628 #address-cells = <1>;
3629 #size-cells = <0>;
3634 remote-endpoint = <&usb2_role_switch>;
3641 remote-endpoint = <&con_eud>;
3649 compatible = "qcom,sc7280-nsp-noc";
3650 #interconnect-cells = <2>;
3651 qcom,bcm-voters = <&apps_bcm_voter>;
3655 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3658 #address-cells = <2>;
3659 #size-cells = <2>;
3661 dma-ranges;
3668 clock-names = "cfg_noc",
3674 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3676 assigned-clock-rates = <19200000>, <200000000>;
3678 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3682 interrupt-names = "hs_phy_irq",
3687 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3688 required-opps = <&rpmhpd_opp_nom>;
3694 interconnect-names = "usb-ddr", "apps-usb";
3696 wakeup-source;
3706 phy-names = "usb2-phy", "usb3-phy";
3707 maximum-speed = "super-speed";
3711 venus: video-codec@aa00000 {
3712 compatible = "qcom,sc7280-venus";
3721 clock-names = "core", "bus", "iface",
3724 power-domains = <&videocc MVSC_GDSC>,
3727 power-domain-names = "venus", "vcodec0", "cx";
3728 operating-points-v2 = <&venus_opp_table>;
3732 interconnect-names = "cpu-cfg", "video-mem";
3736 memory-region = <&video_mem>;
3738 video-decoder {
3739 compatible = "venus-decoder";
3742 video-encoder {
3743 compatible = "venus-encoder";
3746 video-firmware {
3750 venus_opp_table: opp-table {
3751 compatible = "operating-points-v2";
3753 opp-133330000 {
3754 opp-hz = /bits/ 64 <133330000>;
3755 required-opps = <&rpmhpd_opp_low_svs>;
3758 opp-240000000 {
3759 opp-hz = /bits/ 64 <240000000>;
3760 required-opps = <&rpmhpd_opp_svs>;
3763 opp-335000000 {
3764 opp-hz = /bits/ 64 <335000000>;
3765 required-opps = <&rpmhpd_opp_svs_l1>;
3768 opp-424000000 {
3769 opp-hz = /bits/ 64 <424000000>;
3770 required-opps = <&rpmhpd_opp_nom>;
3773 opp-460000048 {
3774 opp-hz = /bits/ 64 <460000048>;
3775 required-opps = <&rpmhpd_opp_turbo>;
3780 videocc: clock-controller@aaf0000 {
3781 compatible = "qcom,sc7280-videocc";
3785 clock-names = "bi_tcxo", "bi_tcxo_ao";
3786 #clock-cells = <1>;
3787 #reset-cells = <1>;
3788 #power-domain-cells = <1>;
3791 camcc: clock-controller@ad00000 {
3792 compatible = "qcom,sc7280-camcc";
3797 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3798 #clock-cells = <1>;
3799 #reset-cells = <1>;
3800 #power-domain-cells = <1>;
3803 dispcc: clock-controller@af00000 {
3804 compatible = "qcom,sc7280-dispcc";
3814 clock-names = "bi_tcxo",
3822 #clock-cells = <1>;
3823 #reset-cells = <1>;
3824 #power-domain-cells = <1>;
3827 mdss: display-subsystem@ae00000 {
3828 compatible = "qcom,sc7280-mdss";
3830 reg-names = "mdss";
3832 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3837 clock-names = "iface",
3842 interrupt-controller;
3843 #interrupt-cells = <1>;
3846 interconnect-names = "mdp0-mem";
3850 #address-cells = <2>;
3851 #size-cells = <2>;
3856 mdss_mdp: display-controller@ae01000 {
3857 compatible = "qcom,sc7280-dpu";
3860 reg-names = "mdp", "vbif";
3868 clock-names = "bus",
3874 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3876 assigned-clock-rates = <19200000>,
3878 operating-points-v2 = <&mdp_opp_table>;
3879 power-domains = <&rpmhpd SC7280_CX>;
3881 interrupt-parent = <&mdss>;
3885 #address-cells = <1>;
3886 #size-cells = <0>;
3891 remote-endpoint = <&mdss_dsi0_in>;
3898 remote-endpoint = <&edp_in>;
3905 remote-endpoint = <&dp_in>;
3910 mdp_opp_table: opp-table {
3911 compatible = "operating-points-v2";
3913 opp-200000000 {
3914 opp-hz = /bits/ 64 <200000000>;
3915 required-opps = <&rpmhpd_opp_low_svs>;
3918 opp-300000000 {
3919 opp-hz = /bits/ 64 <300000000>;
3920 required-opps = <&rpmhpd_opp_svs>;
3923 opp-380000000 {
3924 opp-hz = /bits/ 64 <380000000>;
3925 required-opps = <&rpmhpd_opp_svs_l1>;
3928 opp-506666667 {
3929 opp-hz = /bits/ 64 <506666667>;
3930 required-opps = <&rpmhpd_opp_nom>;
3936 compatible = "qcom,sc7280-dsi-ctrl",
3937 "qcom,mdss-dsi-ctrl";
3939 reg-names = "dsi_ctrl";
3941 interrupt-parent = <&mdss>;
3950 clock-names = "byte",
3957 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3958 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3960 operating-points-v2 = <&dsi_opp_table>;
3961 power-domains = <&rpmhpd SC7280_CX>;
3965 #address-cells = <1>;
3966 #size-cells = <0>;
3971 #address-cells = <1>;
3972 #size-cells = <0>;
3977 remote-endpoint = <&dpu_intf1_out>;
3988 dsi_opp_table: opp-table {
3989 compatible = "operating-points-v2";
3991 opp-187500000 {
3992 opp-hz = /bits/ 64 <187500000>;
3993 required-opps = <&rpmhpd_opp_low_svs>;
3996 opp-300000000 {
3997 opp-hz = /bits/ 64 <300000000>;
3998 required-opps = <&rpmhpd_opp_svs>;
4001 opp-358000000 {
4002 opp-hz = /bits/ 64 <358000000>;
4003 required-opps = <&rpmhpd_opp_svs_l1>;
4009 compatible = "qcom,sc7280-dsi-phy-7nm";
4013 reg-names = "dsi_phy",
4017 #clock-cells = <1>;
4018 #phy-cells = <0>;
4022 clock-names = "iface", "ref";
4028 compatible = "qcom,sc7280-edp";
4029 pinctrl-names = "default";
4030 pinctrl-0 = <&edp_hot_plug_det>;
4037 interrupt-parent = <&mdss>;
4045 clock-names = "core_iface",
4050 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4052 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4055 phy-names = "dp";
4057 operating-points-v2 = <&edp_opp_table>;
4058 power-domains = <&rpmhpd SC7280_CX>;
4063 #address-cells = <1>;
4064 #size-cells = <0>;
4069 remote-endpoint = <&dpu_intf5_out>;
4079 edp_opp_table: opp-table {
4080 compatible = "operating-points-v2";
4082 opp-160000000 {
4083 opp-hz = /bits/ 64 <160000000>;
4084 required-opps = <&rpmhpd_opp_low_svs>;
4087 opp-270000000 {
4088 opp-hz = /bits/ 64 <270000000>;
4089 required-opps = <&rpmhpd_opp_svs>;
4092 opp-540000000 {
4093 opp-hz = /bits/ 64 <540000000>;
4094 required-opps = <&rpmhpd_opp_nom>;
4097 opp-810000000 {
4098 opp-hz = /bits/ 64 <810000000>;
4099 required-opps = <&rpmhpd_opp_nom>;
4105 compatible = "qcom,sc7280-edp-phy";
4114 clock-names = "aux",
4117 #clock-cells = <1>;
4118 #phy-cells = <0>;
4123 mdss_dp: displayport-controller@ae90000 {
4124 compatible = "qcom,sc7280-dp";
4132 interrupt-parent = <&mdss>;
4140 clock-names = "core_iface",
4145 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4147 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4149 phy-names = "dp";
4151 operating-points-v2 = <&dp_opp_table>;
4152 power-domains = <&rpmhpd SC7280_CX>;
4154 #sound-dai-cells = <0>;
4159 #address-cells = <1>;
4160 #size-cells = <0>;
4165 remote-endpoint = <&dpu_intf0_out>;
4175 dp_opp_table: opp-table {
4176 compatible = "operating-points-v2";
4178 opp-160000000 {
4179 opp-hz = /bits/ 64 <160000000>;
4180 required-opps = <&rpmhpd_opp_low_svs>;
4183 opp-270000000 {
4184 opp-hz = /bits/ 64 <270000000>;
4185 required-opps = <&rpmhpd_opp_svs>;
4188 opp-540000000 {
4189 opp-hz = /bits/ 64 <540000000>;
4190 required-opps = <&rpmhpd_opp_svs_l1>;
4193 opp-810000000 {
4194 opp-hz = /bits/ 64 <810000000>;
4195 required-opps = <&rpmhpd_opp_nom>;
4201 pdc: interrupt-controller@b220000 {
4202 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4204 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4209 #interrupt-cells = <2>;
4210 interrupt-parent = <&intc>;
4211 interrupt-controller;
4214 pdc_reset: reset-controller@b5e0000 {
4215 compatible = "qcom,sc7280-pdc-global";
4217 #reset-cells = <1>;
4220 tsens0: thermal-sensor@c263000 {
4221 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4227 interrupt-names = "uplow","critical";
4228 #thermal-sensor-cells = <1>;
4231 tsens1: thermal-sensor@c265000 {
4232 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4238 interrupt-names = "uplow","critical";
4239 #thermal-sensor-cells = <1>;
4242 aoss_reset: reset-controller@c2a0000 {
4243 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4245 #reset-cells = <1>;
4248 aoss_qmp: power-management@c300000 {
4249 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4251 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4257 #clock-cells = <0>;
4261 compatible = "qcom,rpmh-stats";
4266 compatible = "qcom,spmi-pmic-arb";
4272 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4273 interrupt-names = "periph_irq";
4274 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4277 #address-cells = <2>;
4278 #size-cells = <0>;
4279 interrupt-controller;
4280 #interrupt-cells = <4>;
4284 compatible = "qcom,sc7280-pinctrl";
4287 gpio-controller;
4288 #gpio-cells = <2>;
4289 interrupt-controller;
4290 #interrupt-cells = <2>;
4291 gpio-ranges = <&tlmm 0 0 175>;
4292 wakeup-parent = <&pdc>;
4294 dp_hot_plug_det: dp-hot-plug-det-state {
4299 edp_hot_plug_det: edp-hot-plug-det-state {
4304 mi2s0_data0: mi2s0-data0-state {
4309 mi2s0_data1: mi2s0-data1-state {
4314 mi2s0_mclk: mi2s0-mclk-state {
4319 mi2s0_sclk: mi2s0-sclk-state {
4324 mi2s0_ws: mi2s0-ws-state {
4329 mi2s1_data0: mi2s1-data0-state {
4334 mi2s1_sclk: mi2s1-sclk-state {
4339 mi2s1_ws: mi2s1-ws-state {
4344 pcie1_clkreq_n: pcie1-clkreq-n-state {
4349 qspi_clk: qspi-clk-state {
4354 qspi_cs0: qspi-cs0-state {
4359 qspi_cs1: qspi-cs1-state {
4364 qspi_data0: qspi-data0-state {
4369 qspi_data1: qspi-data1-state {
4374 qspi_data23: qspi-data23-state {
4379 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4384 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4389 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4394 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4399 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4404 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4409 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4414 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4419 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4424 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4429 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4434 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4439 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4444 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4449 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4454 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4459 qup_spi0_data_clk: qup-spi0-data-clk-state {
4464 qup_spi0_cs: qup-spi0-cs-state {
4469 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4474 qup_spi1_data_clk: qup-spi1-data-clk-state {
4479 qup_spi1_cs: qup-spi1-cs-state {
4484 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4489 qup_spi2_data_clk: qup-spi2-data-clk-state {
4494 qup_spi2_cs: qup-spi2-cs-state {
4499 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4504 qup_spi3_data_clk: qup-spi3-data-clk-state {
4509 qup_spi3_cs: qup-spi3-cs-state {
4514 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4519 qup_spi4_data_clk: qup-spi4-data-clk-state {
4524 qup_spi4_cs: qup-spi4-cs-state {
4529 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4534 qup_spi5_data_clk: qup-spi5-data-clk-state {
4539 qup_spi5_cs: qup-spi5-cs-state {
4544 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4549 qup_spi6_data_clk: qup-spi6-data-clk-state {
4554 qup_spi6_cs: qup-spi6-cs-state {
4559 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4564 qup_spi7_data_clk: qup-spi7-data-clk-state {
4569 qup_spi7_cs: qup-spi7-cs-state {
4574 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
4579 qup_spi8_data_clk: qup-spi8-data-clk-state {
4584 qup_spi8_cs: qup-spi8-cs-state {
4589 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4594 qup_spi9_data_clk: qup-spi9-data-clk-state {
4599 qup_spi9_cs: qup-spi9-cs-state {
4604 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4609 qup_spi10_data_clk: qup-spi10-data-clk-state {
4614 qup_spi10_cs: qup-spi10-cs-state {
4619 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4624 qup_spi11_data_clk: qup-spi11-data-clk-state {
4629 qup_spi11_cs: qup-spi11-cs-state {
4634 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
4639 qup_spi12_data_clk: qup-spi12-data-clk-state {
4644 qup_spi12_cs: qup-spi12-cs-state {
4649 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4654 qup_spi13_data_clk: qup-spi13-data-clk-state {
4659 qup_spi13_cs: qup-spi13-cs-state {
4664 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4669 qup_spi14_data_clk: qup-spi14-data-clk-state {
4674 qup_spi14_cs: qup-spi14-cs-state {
4679 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4684 qup_spi15_data_clk: qup-spi15-data-clk-state {
4689 qup_spi15_cs: qup-spi15-cs-state {
4694 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4699 qup_uart0_cts: qup-uart0-cts-state {
4704 qup_uart0_rts: qup-uart0-rts-state {
4709 qup_uart0_tx: qup-uart0-tx-state {
4714 qup_uart0_rx: qup-uart0-rx-state {
4719 qup_uart1_cts: qup-uart1-cts-state {
4724 qup_uart1_rts: qup-uart1-rts-state {
4729 qup_uart1_tx: qup-uart1-tx-state {
4734 qup_uart1_rx: qup-uart1-rx-state {
4739 qup_uart2_cts: qup-uart2-cts-state {
4744 qup_uart2_rts: qup-uart2-rts-state {
4749 qup_uart2_tx: qup-uart2-tx-state {
4754 qup_uart2_rx: qup-uart2-rx-state {
4759 qup_uart3_cts: qup-uart3-cts-state {
4764 qup_uart3_rts: qup-uart3-rts-state {
4769 qup_uart3_tx: qup-uart3-tx-state {
4774 qup_uart3_rx: qup-uart3-rx-state {
4779 qup_uart4_cts: qup-uart4-cts-state {
4784 qup_uart4_rts: qup-uart4-rts-state {
4789 qup_uart4_tx: qup-uart4-tx-state {
4794 qup_uart4_rx: qup-uart4-rx-state {
4799 qup_uart5_cts: qup-uart5-cts-state {
4804 qup_uart5_rts: qup-uart5-rts-state {
4809 qup_uart5_tx: qup-uart5-tx-state {
4814 qup_uart5_rx: qup-uart5-rx-state {
4819 qup_uart6_cts: qup-uart6-cts-state {
4824 qup_uart6_rts: qup-uart6-rts-state {
4829 qup_uart6_tx: qup-uart6-tx-state {
4834 qup_uart6_rx: qup-uart6-rx-state {
4839 qup_uart7_cts: qup-uart7-cts-state {
4844 qup_uart7_rts: qup-uart7-rts-state {
4849 qup_uart7_tx: qup-uart7-tx-state {
4854 qup_uart7_rx: qup-uart7-rx-state {
4859 qup_uart8_cts: qup-uart8-cts-state {
4864 qup_uart8_rts: qup-uart8-rts-state {
4869 qup_uart8_tx: qup-uart8-tx-state {
4874 qup_uart8_rx: qup-uart8-rx-state {
4879 qup_uart9_cts: qup-uart9-cts-state {
4884 qup_uart9_rts: qup-uart9-rts-state {
4889 qup_uart9_tx: qup-uart9-tx-state {
4894 qup_uart9_rx: qup-uart9-rx-state {
4899 qup_uart10_cts: qup-uart10-cts-state {
4904 qup_uart10_rts: qup-uart10-rts-state {
4909 qup_uart10_tx: qup-uart10-tx-state {
4914 qup_uart10_rx: qup-uart10-rx-state {
4919 qup_uart11_cts: qup-uart11-cts-state {
4924 qup_uart11_rts: qup-uart11-rts-state {
4929 qup_uart11_tx: qup-uart11-tx-state {
4934 qup_uart11_rx: qup-uart11-rx-state {
4939 qup_uart12_cts: qup-uart12-cts-state {
4944 qup_uart12_rts: qup-uart12-rts-state {
4949 qup_uart12_tx: qup-uart12-tx-state {
4954 qup_uart12_rx: qup-uart12-rx-state {
4959 qup_uart13_cts: qup-uart13-cts-state {
4964 qup_uart13_rts: qup-uart13-rts-state {
4969 qup_uart13_tx: qup-uart13-tx-state {
4974 qup_uart13_rx: qup-uart13-rx-state {
4979 qup_uart14_cts: qup-uart14-cts-state {
4984 qup_uart14_rts: qup-uart14-rts-state {
4989 qup_uart14_tx: qup-uart14-tx-state {
4994 qup_uart14_rx: qup-uart14-rx-state {
4999 qup_uart15_cts: qup-uart15-cts-state {
5004 qup_uart15_rts: qup-uart15-rts-state {
5009 qup_uart15_tx: qup-uart15-tx-state {
5014 qup_uart15_rx: qup-uart15-rx-state {
5019 sdc1_clk: sdc1-clk-state {
5023 sdc1_cmd: sdc1-cmd-state {
5027 sdc1_data: sdc1-data-state {
5031 sdc1_rclk: sdc1-rclk-state {
5035 sdc1_clk_sleep: sdc1-clk-sleep-state {
5037 drive-strength = <2>;
5038 bias-bus-hold;
5041 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5043 drive-strength = <2>;
5044 bias-bus-hold;
5047 sdc1_data_sleep: sdc1-data-sleep-state {
5049 drive-strength = <2>;
5050 bias-bus-hold;
5053 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5055 drive-strength = <2>;
5056 bias-bus-hold;
5059 sdc2_clk: sdc2-clk-state {
5063 sdc2_cmd: sdc2-cmd-state {
5067 sdc2_data: sdc2-data-state {
5071 sdc2_clk_sleep: sdc2-clk-sleep-state {
5073 drive-strength = <2>;
5074 bias-bus-hold;
5077 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5079 drive-strength = <2>;
5080 bias-bus-hold;
5083 sdc2_data_sleep: sdc2-data-sleep-state {
5085 drive-strength = <2>;
5086 bias-bus-hold;
5091 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5094 #address-cells = <1>;
5095 #size-cells = <1>;
5099 pil-reloc@594c {
5100 compatible = "qcom,pil-reloc-info";
5106 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5108 #iommu-cells = <2>;
5109 #global-interrupts = <1>;
5110 dma-coherent;
5194 intc: interrupt-controller@17a00000 {
5195 compatible = "arm,gic-v3";
5199 #interrupt-cells = <3>;
5200 interrupt-controller;
5201 #address-cells = <2>;
5202 #size-cells = <2>;
5205 msi-controller@17a40000 {
5206 compatible = "arm,gic-v3-its";
5208 msi-controller;
5209 #msi-cells = <1>;
5215 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5222 #address-cells = <1>;
5223 #size-cells = <1>;
5225 compatible = "arm,armv7-timer-mem";
5229 frame-number = <0>;
5237 frame-number = <1>;
5244 frame-number = <2>;
5251 frame-number = <3>;
5258 frame-number = <4>;
5265 frame-number = <5>;
5272 frame-number = <6>;
5280 compatible = "qcom,rpmh-rsc";
5284 reg-names = "drv-0", "drv-1", "drv-2";
5288 qcom,tcs-offset = <0xd00>;
5289 qcom,drv-id = <2>;
5290 qcom,tcs-config = <ACTIVE_TCS 2>,
5295 apps_bcm_voter: bcm-voter {
5296 compatible = "qcom,bcm-voter";
5299 rpmhpd: power-controller {
5300 compatible = "qcom,sc7280-rpmhpd";
5301 #power-domain-cells = <1>;
5302 operating-points-v2 = <&rpmhpd_opp_table>;
5304 rpmhpd_opp_table: opp-table {
5305 compatible = "operating-points-v2";
5308 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5312 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5320 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5324 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5328 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5332 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5345 rpmhcc: clock-controller {
5346 compatible = "qcom,sc7280-rpmh-clk";
5348 clock-names = "xo";
5349 #clock-cells = <1>;
5354 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5357 clock-names = "xo", "alternate";
5358 #interconnect-cells = <1>;
5362 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5367 clock-names = "xo", "alternate";
5368 #freq-domain-cells = <1>;
5369 #clock-cells = <1>;
5373 thermal_zones: thermal-zones {
5374 cpu0-thermal {
5375 polling-delay-passive = <250>;
5376 polling-delay = <0>;
5378 thermal-sensors = <&tsens0 1>;
5381 cpu0_alert0: trip-point0 {
5387 cpu0_alert1: trip-point1 {
5393 cpu0_crit: cpu-crit {
5400 cooling-maps {
5403 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5410 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5418 cpu1-thermal {
5419 polling-delay-passive = <250>;
5420 polling-delay = <0>;
5422 thermal-sensors = <&tsens0 2>;
5425 cpu1_alert0: trip-point0 {
5431 cpu1_alert1: trip-point1 {
5437 cpu1_crit: cpu-crit {
5444 cooling-maps {
5447 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5454 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5462 cpu2-thermal {
5463 polling-delay-passive = <250>;
5464 polling-delay = <0>;
5466 thermal-sensors = <&tsens0 3>;
5469 cpu2_alert0: trip-point0 {
5475 cpu2_alert1: trip-point1 {
5481 cpu2_crit: cpu-crit {
5488 cooling-maps {
5491 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5498 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5506 cpu3-thermal {
5507 polling-delay-passive = <250>;
5508 polling-delay = <0>;
5510 thermal-sensors = <&tsens0 4>;
5513 cpu3_alert0: trip-point0 {
5519 cpu3_alert1: trip-point1 {
5525 cpu3_crit: cpu-crit {
5532 cooling-maps {
5535 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5542 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5550 cpu4-thermal {
5551 polling-delay-passive = <250>;
5552 polling-delay = <0>;
5554 thermal-sensors = <&tsens0 7>;
5557 cpu4_alert0: trip-point0 {
5563 cpu4_alert1: trip-point1 {
5569 cpu4_crit: cpu-crit {
5576 cooling-maps {
5579 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5586 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5594 cpu5-thermal {
5595 polling-delay-passive = <250>;
5596 polling-delay = <0>;
5598 thermal-sensors = <&tsens0 8>;
5601 cpu5_alert0: trip-point0 {
5607 cpu5_alert1: trip-point1 {
5613 cpu5_crit: cpu-crit {
5620 cooling-maps {
5623 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5630 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5638 cpu6-thermal {
5639 polling-delay-passive = <250>;
5640 polling-delay = <0>;
5642 thermal-sensors = <&tsens0 9>;
5645 cpu6_alert0: trip-point0 {
5651 cpu6_alert1: trip-point1 {
5657 cpu6_crit: cpu-crit {
5664 cooling-maps {
5667 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5674 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5682 cpu7-thermal {
5683 polling-delay-passive = <250>;
5684 polling-delay = <0>;
5686 thermal-sensors = <&tsens0 10>;
5689 cpu7_alert0: trip-point0 {
5695 cpu7_alert1: trip-point1 {
5701 cpu7_crit: cpu-crit {
5708 cooling-maps {
5711 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5718 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5726 cpu8-thermal {
5727 polling-delay-passive = <250>;
5728 polling-delay = <0>;
5730 thermal-sensors = <&tsens0 11>;
5733 cpu8_alert0: trip-point0 {
5739 cpu8_alert1: trip-point1 {
5745 cpu8_crit: cpu-crit {
5752 cooling-maps {
5755 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5762 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5770 cpu9-thermal {
5771 polling-delay-passive = <250>;
5772 polling-delay = <0>;
5774 thermal-sensors = <&tsens0 12>;
5777 cpu9_alert0: trip-point0 {
5783 cpu9_alert1: trip-point1 {
5789 cpu9_crit: cpu-crit {
5796 cooling-maps {
5799 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5806 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5814 cpu10-thermal {
5815 polling-delay-passive = <250>;
5816 polling-delay = <0>;
5818 thermal-sensors = <&tsens0 13>;
5821 cpu10_alert0: trip-point0 {
5827 cpu10_alert1: trip-point1 {
5833 cpu10_crit: cpu-crit {
5840 cooling-maps {
5843 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5850 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5858 cpu11-thermal {
5859 polling-delay-passive = <250>;
5860 polling-delay = <0>;
5862 thermal-sensors = <&tsens0 14>;
5865 cpu11_alert0: trip-point0 {
5871 cpu11_alert1: trip-point1 {
5877 cpu11_crit: cpu-crit {
5884 cooling-maps {
5887 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5894 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5902 aoss0-thermal {
5903 polling-delay-passive = <0>;
5904 polling-delay = <0>;
5906 thermal-sensors = <&tsens0 0>;
5909 aoss0_alert0: trip-point0 {
5915 aoss0_crit: aoss0-crit {
5923 aoss1-thermal {
5924 polling-delay-passive = <0>;
5925 polling-delay = <0>;
5927 thermal-sensors = <&tsens1 0>;
5930 aoss1_alert0: trip-point0 {
5936 aoss1_crit: aoss1-crit {
5944 cpuss0-thermal {
5945 polling-delay-passive = <0>;
5946 polling-delay = <0>;
5948 thermal-sensors = <&tsens0 5>;
5951 cpuss0_alert0: trip-point0 {
5956 cpuss0_crit: cluster0-crit {
5964 cpuss1-thermal {
5965 polling-delay-passive = <0>;
5966 polling-delay = <0>;
5968 thermal-sensors = <&tsens0 6>;
5971 cpuss1_alert0: trip-point0 {
5976 cpuss1_crit: cluster0-crit {
5984 gpuss0-thermal {
5985 polling-delay-passive = <100>;
5986 polling-delay = <0>;
5988 thermal-sensors = <&tsens1 1>;
5991 gpuss0_alert0: trip-point0 {
5997 gpuss0_crit: gpuss0-crit {
6004 cooling-maps {
6007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6012 gpuss1-thermal {
6013 polling-delay-passive = <100>;
6014 polling-delay = <0>;
6016 thermal-sensors = <&tsens1 2>;
6019 gpuss1_alert0: trip-point0 {
6025 gpuss1_crit: gpuss1-crit {
6032 cooling-maps {
6035 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6040 nspss0-thermal {
6041 polling-delay-passive = <0>;
6042 polling-delay = <0>;
6044 thermal-sensors = <&tsens1 3>;
6047 nspss0_alert0: trip-point0 {
6053 nspss0_crit: nspss0-crit {
6061 nspss1-thermal {
6062 polling-delay-passive = <0>;
6063 polling-delay = <0>;
6065 thermal-sensors = <&tsens1 4>;
6068 nspss1_alert0: trip-point0 {
6074 nspss1_crit: nspss1-crit {
6082 video-thermal {
6083 polling-delay-passive = <0>;
6084 polling-delay = <0>;
6086 thermal-sensors = <&tsens1 5>;
6089 video_alert0: trip-point0 {
6095 video_crit: video-crit {
6103 ddr-thermal {
6104 polling-delay-passive = <0>;
6105 polling-delay = <0>;
6107 thermal-sensors = <&tsens1 6>;
6110 ddr_alert0: trip-point0 {
6116 ddr_crit: ddr-crit {
6124 mdmss0-thermal {
6125 polling-delay-passive = <0>;
6126 polling-delay = <0>;
6128 thermal-sensors = <&tsens1 7>;
6131 mdmss0_alert0: trip-point0 {
6137 mdmss0_crit: mdmss0-crit {
6145 mdmss1-thermal {
6146 polling-delay-passive = <0>;
6147 polling-delay = <0>;
6149 thermal-sensors = <&tsens1 8>;
6152 mdmss1_alert0: trip-point0 {
6158 mdmss1_crit: mdmss1-crit {
6166 mdmss2-thermal {
6167 polling-delay-passive = <0>;
6168 polling-delay = <0>;
6170 thermal-sensors = <&tsens1 9>;
6173 mdmss2_alert0: trip-point0 {
6179 mdmss2_crit: mdmss2-crit {
6187 mdmss3-thermal {
6188 polling-delay-passive = <0>;
6189 polling-delay = <0>;
6191 thermal-sensors = <&tsens1 10>;
6194 mdmss3_alert0: trip-point0 {
6200 mdmss3_crit: mdmss3-crit {
6208 camera0-thermal {
6209 polling-delay-passive = <0>;
6210 polling-delay = <0>;
6212 thermal-sensors = <&tsens1 11>;
6215 camera0_alert0: trip-point0 {
6221 camera0_crit: camera0-crit {
6231 compatible = "arm,armv8-timer";