Lines Matching +full:0 +full:x04180000
77 #clock-cells = <0>;
83 #clock-cells = <0>;
94 reg = <0x0 0x004cd000 0x0 0x1000>;
98 reg = <0x0 0x80000000 0x0 0x600000>;
103 reg = <0x0 0x80600000 0x0 0x200000>;
108 reg = <0x0 0x80800000 0x0 0x60000>;
113 reg = <0x0 0x80860000 0x0 0x20000>;
119 reg = <0x0 0x80884000 0x0 0x10000>;
124 reg = <0x0 0x808ff000 0x0 0x1000>;
129 reg = <0x0 0x80900000 0x0 0x200000>;
135 reg = <0x0 0x80b00000 0x0 0x100000>;
139 reg = <0x0 0x80c00000 0x0 0xc00000>;
144 reg = <0x0 0x8b200000 0x0 0x500000>;
149 reg = <0 0x8b700000 0 0x10000>;
155 reg = <0x0 0x9c900000 0x0 0x280000>;
165 #size-cells = <0>;
167 CPU0: cpu@0 {
170 reg = <0x0 0x0>;
171 clocks = <&cpufreq_hw 0>;
180 qcom,freq-domain = <&cpufreq_hw 0>;
198 reg = <0x0 0x100>;
199 clocks = <&cpufreq_hw 0>;
208 qcom,freq-domain = <&cpufreq_hw 0>;
221 reg = <0x0 0x200>;
222 clocks = <&cpufreq_hw 0>;
231 qcom,freq-domain = <&cpufreq_hw 0>;
244 reg = <0x0 0x300>;
245 clocks = <&cpufreq_hw 0>;
254 qcom,freq-domain = <&cpufreq_hw 0>;
267 reg = <0x0 0x400>;
290 reg = <0x0 0x500>;
313 reg = <0x0 0x600>;
336 reg = <0x0 0x700>;
395 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
398 arm,psci-suspend-param = <0x40000003>;
405 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
408 arm,psci-suspend-param = <0x40000004>;
415 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
418 arm,psci-suspend-param = <0x40000003>;
428 arm,psci-suspend-param = <0x40000004>;
435 CLUSTER_SLEEP_0: cluster-sleep-0 {
438 arm,psci-suspend-param = <0x40003444>;
656 port@0 {
667 reg = <0 0x80000000 0 0>;
697 qcom,local-pid = <0>;
721 qcom,local-pid = <0>;
745 qcom,local-pid = <0>;
780 qcom,local-pid = <0>;
859 soc: soc@0 {
862 ranges = <0 0 0 0 0x10 0>;
863 dma-ranges = <0 0 0 0 0x10 0>;
868 reg = <0 0x00100000 0 0x1f0000>;
871 <0>, <&pcie1_lane>,
872 <0>, <0>, <0>, <0>;
886 reg = <0 0x00408000 0 0x1000>;
895 reg = <0 0x00784000 0 0xa20>,
896 <0 0x00780000 0 0xa20>,
897 <0 0x00782000 0 0x120>,
898 <0 0x00786000 0 0x1fff>;
906 reg = <0x1e9 0x2>;
914 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
918 reg = <0 0x007c4000 0 0x1000>,
919 <0 0x007c5000 0 0x1000>;
922 iommus = <&apps_smmu 0xc0 0x0>;
931 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
932 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
940 qcom,dll-config = <0x0007642c>;
941 qcom,ddr-config = <0x80040868>;
957 opp-avg-kBps = <100000 0>;
964 opp-avg-kBps = <390000 0>;
972 reg = <0 0x00900000 0 0x60000>;
986 dma-channel-mask = <0x7f>;
987 iommus = <&apps_smmu 0x0136 0x0>;
993 reg = <0 0x009c0000 0 0x2000>;
1000 iommus = <&apps_smmu 0x123 0x0>;
1005 reg = <0 0x00980000 0 0x4000>;
1009 pinctrl-0 = <&qup_i2c0_data_clk>;
1012 #size-cells = <0>;
1013 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1014 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1015 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1020 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1021 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1028 reg = <0 0x00980000 0 0x4000>;
1032 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1035 #size-cells = <0>;
1038 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1039 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1041 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1042 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1049 reg = <0 0x00980000 0 0x4000>;
1053 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1057 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1058 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1065 reg = <0 0x00984000 0 0x4000>;
1069 pinctrl-0 = <&qup_i2c1_data_clk>;
1072 #size-cells = <0>;
1073 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1074 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1075 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1080 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1088 reg = <0 0x00984000 0 0x4000>;
1092 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1095 #size-cells = <0>;
1098 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1099 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1101 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1109 reg = <0 0x00984000 0 0x4000>;
1113 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1125 reg = <0 0x00988000 0 0x4000>;
1129 pinctrl-0 = <&qup_i2c2_data_clk>;
1132 #size-cells = <0>;
1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1134 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1135 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1140 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1148 reg = <0 0x00988000 0 0x4000>;
1152 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1155 #size-cells = <0>;
1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1159 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1161 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1169 reg = <0 0x00988000 0 0x4000>;
1173 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1177 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1178 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1185 reg = <0 0x0098c000 0 0x4000>;
1189 pinctrl-0 = <&qup_i2c3_data_clk>;
1192 #size-cells = <0>;
1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1195 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1200 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1208 reg = <0 0x0098c000 0 0x4000>;
1212 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1215 #size-cells = <0>;
1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1221 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1229 reg = <0 0x0098c000 0 0x4000>;
1233 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1245 reg = <0 0x00990000 0 0x4000>;
1249 pinctrl-0 = <&qup_i2c4_data_clk>;
1252 #size-cells = <0>;
1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1260 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1268 reg = <0 0x00990000 0 0x4000>;
1272 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1275 #size-cells = <0>;
1278 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1279 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1281 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1289 reg = <0 0x00990000 0 0x4000>;
1293 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1297 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1305 reg = <0 0x00994000 0 0x4000>;
1309 pinctrl-0 = <&qup_i2c5_data_clk>;
1312 #size-cells = <0>;
1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1315 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1320 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1328 reg = <0 0x00994000 0 0x4000>;
1332 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1335 #size-cells = <0>;
1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1339 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1341 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1349 reg = <0 0x00994000 0 0x4000>;
1353 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1358 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1365 reg = <0 0x00998000 0 0x4000>;
1369 pinctrl-0 = <&qup_i2c6_data_clk>;
1372 #size-cells = <0>;
1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1374 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1375 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1380 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1388 reg = <0 0x00998000 0 0x4000>;
1392 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1395 #size-cells = <0>;
1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1399 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1401 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1409 reg = <0 0x00998000 0 0x4000>;
1413 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1418 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1425 reg = <0 0x0099c000 0 0x4000>;
1429 pinctrl-0 = <&qup_i2c7_data_clk>;
1432 #size-cells = <0>;
1433 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1435 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1440 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1448 reg = <0 0x0099c000 0 0x4000>;
1452 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1455 #size-cells = <0>;
1458 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1459 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1461 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1469 reg = <0 0x0099c000 0 0x4000>;
1473 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1477 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1478 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1487 reg = <0 0x00a00000 0 0x60000>;
1501 dma-channel-mask = <0x1e>;
1502 iommus = <&apps_smmu 0x56 0x0>;
1508 reg = <0 0x00ac0000 0 0x2000>;
1515 iommus = <&apps_smmu 0x43 0x0>;
1520 reg = <0 0x00a80000 0 0x4000>;
1524 pinctrl-0 = <&qup_i2c8_data_clk>;
1527 #size-cells = <0>;
1528 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1529 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1530 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1535 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1536 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1543 reg = <0 0x00a80000 0 0x4000>;
1547 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1550 #size-cells = <0>;
1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1554 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1556 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1557 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1564 reg = <0 0x00a80000 0 0x4000>;
1568 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1572 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1580 reg = <0 0x00a84000 0 0x4000>;
1584 pinctrl-0 = <&qup_i2c9_data_clk>;
1587 #size-cells = <0>;
1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1589 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1590 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1595 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1603 reg = <0 0x00a84000 0 0x4000>;
1607 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1610 #size-cells = <0>;
1613 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1614 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1616 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1624 reg = <0 0x00a84000 0 0x4000>;
1628 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1632 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1633 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1640 reg = <0 0x00a88000 0 0x4000>;
1644 pinctrl-0 = <&qup_i2c10_data_clk>;
1647 #size-cells = <0>;
1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1649 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1650 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1655 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1663 reg = <0 0x00a88000 0 0x4000>;
1667 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1670 #size-cells = <0>;
1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1674 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1676 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1684 reg = <0 0x00a88000 0 0x4000>;
1688 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1692 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1700 reg = <0 0x00a8c000 0 0x4000>;
1704 pinctrl-0 = <&qup_i2c11_data_clk>;
1707 #size-cells = <0>;
1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1710 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1715 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1723 reg = <0 0x00a8c000 0 0x4000>;
1727 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1730 #size-cells = <0>;
1733 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1734 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1736 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1744 reg = <0 0x00a8c000 0 0x4000>;
1748 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1753 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1760 reg = <0 0x00a90000 0 0x4000>;
1764 pinctrl-0 = <&qup_i2c12_data_clk>;
1767 #size-cells = <0>;
1768 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1770 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1775 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1783 reg = <0 0x00a90000 0 0x4000>;
1787 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1790 #size-cells = <0>;
1793 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1794 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1796 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1804 reg = <0 0x00a90000 0 0x4000>;
1808 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1812 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1813 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1820 reg = <0 0x00a94000 0 0x4000>;
1824 pinctrl-0 = <&qup_i2c13_data_clk>;
1827 #size-cells = <0>;
1828 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1829 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1830 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1835 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1843 reg = <0 0x00a94000 0 0x4000>;
1847 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1850 #size-cells = <0>;
1853 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1854 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1856 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1864 reg = <0 0x00a94000 0 0x4000>;
1868 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1872 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1873 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1880 reg = <0 0x00a98000 0 0x4000>;
1884 pinctrl-0 = <&qup_i2c14_data_clk>;
1887 #size-cells = <0>;
1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1889 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1890 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1895 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1903 reg = <0 0x00a98000 0 0x4000>;
1907 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1910 #size-cells = <0>;
1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1914 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1916 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1924 reg = <0 0x00a98000 0 0x4000>;
1928 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1932 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1933 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1940 reg = <0 0x00a9c000 0 0x4000>;
1944 pinctrl-0 = <&qup_i2c15_data_clk>;
1947 #size-cells = <0>;
1948 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1950 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1955 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1963 reg = <0 0x00a9c000 0 0x4000>;
1967 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1970 #size-cells = <0>;
1973 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1974 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1976 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1984 reg = <0 0x00a9c000 0 0x4000>;
1988 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1992 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1993 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
2000 reg = <0 0x01500000 0 0x1000>;
2007 reg = <0 0x01502000 0 0x1000>;
2014 reg = <0 0x01580000 0 0x4>;
2021 reg = <0 0x01680000 0 0x15480>;
2029 reg = <0 0x016e0000 0 0x1c080>;
2035 reg = <0 0x01700000 0 0x2b080>;
2042 reg = <0 0x01740000 0 0x1e080>;
2050 reg = <0 0x17a10040 0 0x0>;
2051 iommus = <&apps_smmu 0x1c00 0x1>;
2087 qcom,smem-states = <&wlan_smp2p_out 0>;
2093 reg = <0 0x01c08000 0 0x3000>,
2094 <0 0x40000000 0 0xf1d>,
2095 <0 0x40000f20 0 0xa8>,
2096 <0 0x40001000 0 0x1000>,
2097 <0 0x40100000 0 0x100000>;
2102 bus-range = <0x00 0xff>;
2108 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2109 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2114 interrupt-map-mask = <0 0 0 0x7>;
2115 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2116 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2117 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2118 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2160 pinctrl-0 = <&pcie1_clkreq_n>;
2164 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2165 <0x100 &apps_smmu 0x1c81 0x1>;
2172 reg = <0 0x01c0e000 0 0x1c0>;
2191 reg = <0 0x01c0e200 0 0x170>,
2192 <0 0x01c0e400 0 0x200>,
2193 <0 0x01c0ea00 0 0x1f0>,
2194 <0 0x01c0e600 0 0x170>,
2195 <0 0x01c0e800 0 0x200>,
2196 <0 0x01c0ee00 0 0xf4>;
2200 #phy-cells = <0>;
2201 #clock-cells = <0>;
2209 iommus = <&apps_smmu 0x480 0x0>,
2210 <&apps_smmu 0x482 0x0>;
2211 reg = <0 0x01e40000 0 0x8000>,
2212 <0 0x01e50000 0 0x4ad0>,
2213 <0 0x01e04000 0 0x23000>;
2220 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2230 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2231 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2237 qcom,smem-states = <&ipa_smp2p_out 0>,
2247 reg = <0 0x01f40000 0 0x20000>;
2253 reg = <0 0x01f60000 0 0x20000>;
2258 reg = <0 0x01fc0000 0 0x30000>;
2263 reg = <0 0x03000000 0 0x40>,
2264 <0 0x03c04000 0 0x4>;
2273 reg = <0 0x03200000 0 0x1000>;
2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2287 #clock-cells = <0>;
2295 reg = <0 0x03210000 0 0x2000>;
2301 qcom,din-ports = <0>;
2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2319 #size-cells = <0>;
2326 reg = <0 0x03220000 0 0x1000>;
2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2340 #clock-cells = <0>;
2348 reg = <0 0x03230000 0 0x2000>;
2356 qcom,dout-ports = <0>;
2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2373 #size-cells = <0>;
2380 reg = <0 0x03300000 0 0x30000>,
2381 <0 0x032a9000 0 0x1000>;
2393 reg = <0 0x03370000 0 0x1000>;
2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2405 #clock-cells = <0>;
2413 reg = <0 0x03380000 0 0x30000>;
2424 reg = <0 0x03900000 0 0x50000>;
2435 reg = <0 0x03987000 0 0x68000>,
2436 <0 0x03b00000 0 0x29000>,
2437 <0 0x03260000 0 0xc000>,
2438 <0 0x03280000 0 0x29000>,
2439 <0 0x03340000 0 0x29000>,
2440 <0 0x0336c000 0 0x3000>;
2448 iommus = <&apps_smmu 0x1820 0>,
2449 <&apps_smmu 0x1821 0>,
2450 <&apps_smmu 0x1832 0>;
2479 #size-cells = <0>;
2495 reg = <0 0x03c00000 0 0x28>;
2503 reg = <0 0x03c40000 0 0xf080>;
2511 reg = <0 0x033c0000 0x0 0x20000>,
2512 <0 0x03550000 0x0 0x10000>;
2516 gpio-ranges = <&lpass_tlmm 0 0 15>;
2561 reg = <0 0x03d00000 0 0x40000>,
2562 <0 0x03d9e000 0 0x1000>,
2563 <0 0x03d61000 0 0x800>;
2568 iommus = <&adreno_smmu 0 0x401>;
2571 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2585 opp-supported-hw = <0x03>;
2592 opp-supported-hw = <0x03>;
2596 opp-550000000-0 {
2600 opp-supported-hw = <0x01>;
2607 opp-supported-hw = <0x02>;
2614 opp-supported-hw = <0x02>;
2621 opp-supported-hw = <0x02>;
2628 opp-supported-hw = <0x02>;
2635 opp-supported-hw = <0x02>;
2642 opp-supported-hw = <0x02>;
2649 reg = <0 0x03d6a000 0 0x34000>,
2650 <0 0x3de0000 0 0x10000>,
2651 <0 0x0b290000 0 0x10000>;
2674 iommus = <&adreno_smmu 5 0x400>;
2689 reg = <0 0x03d90000 0 0x9000>;
2703 reg = <0x0 0x0117f000 0x0 0x1000>,
2704 <0x0 0x01112000 0x0 0x6000>;
2710 reg = <0 0x03da0000 0 0x20000>;
2746 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2750 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2769 qcom,smem-states = <&modem_smp2p_out 0>;
2787 reg = <0 0x06002000 0 0x1000>,
2788 <0 0x16280000 0 0x180000>;
2805 reg = <0 0x06041000 0 0x1000>;
2820 #size-cells = <0>;
2833 reg = <0 0x06042000 0 0x1000>;
2848 #size-cells = <0>;
2861 reg = <0 0x06045000 0 0x1000>;
2876 #size-cells = <0>;
2878 port@0 {
2879 reg = <0>;
2896 reg = <0 0x06046000 0 0x1000>;
2920 reg = <0 0x06048000 0 0x1000>;
2921 iommus = <&apps_smmu 0x04c0 0>;
2938 reg = <0 0x06b04000 0 0x1000>;
2953 #size-cells = <0>;
2966 reg = <0 0x06b05000 0 0x1000>;
2990 reg = <0 0x06b06000 0 0x1000>;
3015 reg = <0 0x07040000 0 0x1000>;
3035 reg = <0 0x07140000 0 0x1000>;
3055 reg = <0 0x07240000 0 0x1000>;
3075 reg = <0 0x07340000 0 0x1000>;
3095 reg = <0 0x07440000 0 0x1000>;
3115 reg = <0 0x07540000 0 0x1000>;
3135 reg = <0 0x07640000 0 0x1000>;
3155 reg = <0 0x07740000 0 0x1000>;
3175 reg = <0 0x07800000 0 0x1000>;
3190 #size-cells = <0>;
3192 port@0 {
3193 reg = <0>;
3252 reg = <0 0x07810000 0 0x1000>;
3277 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3281 reg = <0 0x08804000 0 0x1000>;
3283 iommus = <&apps_smmu 0x100 0x0>;
3292 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3293 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3300 qcom,dll-config = <0x0007642c>;
3311 opp-avg-kBps = <100000 0>;
3318 opp-avg-kBps = <200000 0>;
3326 reg = <0 0x088e3000 0 0x400>;
3328 #phy-cells = <0>;
3339 reg = <0 0x088e4000 0 0x400>;
3341 #phy-cells = <0>;
3352 reg = <0 0x088e9000 0 0x200>,
3353 <0 0x088e8000 0 0x40>,
3354 <0 0x088ea000 0 0x200>;
3370 reg = <0 0x088e9200 0 0x200>,
3371 <0 0x088e9400 0 0x200>,
3372 <0 0x088e9c00 0 0x400>,
3373 <0 0x088e9600 0 0x200>,
3374 <0 0x088e9800 0 0x200>,
3375 <0 0x088e9a00 0 0x100>;
3376 #clock-cells = <0>;
3377 #phy-cells = <0>;
3384 reg = <0 0x088ea200 0 0x200>,
3385 <0 0x088ea400 0 0x200>,
3386 <0 0x088eaa00 0 0x200>,
3387 <0 0x088ea600 0 0x200>,
3388 <0 0x088ea800 0 0x200>;
3389 #phy-cells = <0>;
3396 reg = <0 0x08cf8800 0 0x400>;
3430 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3431 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3436 reg = <0 0x08c00000 0 0xe000>;
3438 iommus = <&apps_smmu 0xa0 0x0>;
3456 reg = <0 0x088dc000 0 0x1000>;
3457 iommus = <&apps_smmu 0x20 0x0>;
3459 #size-cells = <0>;
3464 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3465 &cnoc2 SLAVE_QSPI_0 0>;
3474 reg = <0 0x08a00000 0 0x10000>;
3477 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3500 qcom,smem-states = <&wpss_smp2p_out 0>;
3507 qcom,halt-regs = <&tcsr_1 0x17000>;
3525 reg = <0 0x09091000 0 0x1000>;
3536 opp-0 {
3565 reg = <0 0x090b6400 0 0x600>;
3575 opp-0 {
3600 reg = <0 0x090e0000 0 0x5080>;
3607 reg = <0 0x09100000 0 0xe2200>;
3615 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3616 <0 0x09600000 0 0x58000>;
3623 reg = <0 0x88e0000 0 0x2000>,
3624 <0 0x88e2000 0 0x1000>;
3629 #size-cells = <0>;
3631 port@0 {
3632 reg = <0>;
3648 reg = <0 0x0a0c0000 0 0x10000>;
3656 reg = <0 0x0a6f8800 0 0x400>;
3692 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3693 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3700 reg = <0 0x0a600000 0 0xe000>;
3702 iommus = <&apps_smmu 0xe0 0x0>;
3713 reg = <0 0x0aa00000 0 0xd0600>;
3730 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3731 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3734 iommus = <&apps_smmu 0x2180 0x20>,
3735 <&apps_smmu 0x2184 0x20>;
3747 iommus = <&apps_smmu 0x21a2 0x0>;
3782 reg = <0 0x0aaf0000 0 0x10000>;
3793 reg = <0 0x0ad00000 0 0x10000>;
3805 reg = <0 0x0af00000 0 0x20000>;
3808 <&mdss_dsi_phy 0>,
3810 <&dp_phy 0>,
3812 <&mdss_edp_phy 0>,
3829 reg = <0 0x0ae00000 0 0x1000>;
3845 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3848 iommus = <&apps_smmu 0x900 0x402>;
3858 reg = <0 0x0ae01000 0 0x8f030>,
3859 <0 0x0aeb0000 0 0x2008>;
3882 interrupts = <0>;
3886 #size-cells = <0>;
3888 port@0 {
3889 reg = <0>;
3938 reg = <0 0x0ae94000 0 0x400>;
3958 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3966 #size-cells = <0>;
3972 #size-cells = <0>;
3974 port@0 {
3975 reg = <0>;
4010 reg = <0 0x0ae94400 0 0x200>,
4011 <0 0x0ae94600 0 0x280>,
4012 <0 0x0ae94900 0 0x280>;
4018 #phy-cells = <0>;
4030 pinctrl-0 = <&edp_hot_plug_det>;
4032 reg = <0 0x0aea0000 0 0x200>,
4033 <0 0x0aea0200 0 0x200>,
4034 <0 0x0aea0400 0 0xc00>,
4035 <0 0x0aea1000 0 0x400>;
4052 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4064 #size-cells = <0>;
4066 port@0 {
4067 reg = <0>;
4107 reg = <0 0x0aec2a00 0 0x19c>,
4108 <0 0x0aec2200 0 0xa0>,
4109 <0 0x0aec2600 0 0xa0>,
4110 <0 0x0aec2000 0 0x1c0>;
4118 #phy-cells = <0>;
4126 reg = <0 0x0ae90000 0 0x200>,
4127 <0 0x0ae90200 0 0x200>,
4128 <0 0x0ae90400 0 0xc00>,
4129 <0 0x0ae91000 0 0x400>,
4130 <0 0x0ae91400 0 0x400>;
4147 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4154 #sound-dai-cells = <0>;
4160 #size-cells = <0>;
4162 port@0 {
4163 reg = <0>;
4203 reg = <0 0x0b220000 0 0x30000>;
4204 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4216 reg = <0 0x0b5e0000 0 0x20000>;
4222 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4223 <0 0x0c222000 0 0x1ff>; /* SROT */
4233 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4234 <0 0x0c223000 0 0x1ff>; /* SROT */
4244 reg = <0 0x0c2a0000 0 0x31000>;
4250 reg = <0 0x0c300000 0 0x400>;
4257 #clock-cells = <0>;
4262 reg = <0 0x0c3f0000 0 0x400>;
4267 reg = <0 0x0c440000 0 0x1100>,
4268 <0 0x0c600000 0 0x2000000>,
4269 <0 0x0e600000 0 0x100000>,
4270 <0 0x0e700000 0 0xa0000>,
4271 <0 0x0c40a000 0 0x26000>;
4275 qcom,ee = <0>;
4276 qcom,channel = <0>;
4278 #size-cells = <0>;
4285 reg = <0 0x0f100000 0 0x300000>;
4291 gpio-ranges = <&tlmm 0 0 175>;
5092 reg = <0 0x146a5000 0 0x6000>;
5097 ranges = <0 0 0x146a5000 0x6000>;
5101 reg = <0x594c 0xc8>;
5107 reg = <0 0x15000000 0 0x100000>;
5196 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5197 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5207 reg = <0 0x17a40000 0 0x20000>;
5216 reg = <0 0x17c10000 0 0x1000>;
5218 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5224 ranges = <0 0 0 0x20000000>;
5226 reg = <0 0x17c20000 0 0x1000>;
5229 frame-number = <0>;
5232 reg = <0x17c21000 0x1000>,
5233 <0x17c22000 0x1000>;
5239 reg = <0x17c23000 0x1000>;
5246 reg = <0x17c25000 0x1000>;
5253 reg = <0x17c27000 0x1000>;
5260 reg = <0x17c29000 0x1000>;
5267 reg = <0x17c2b000 0x1000>;
5274 reg = <0x17c2d000 0x1000>;
5281 reg = <0 0x18200000 0 0x10000>,
5282 <0 0x18210000 0 0x10000>,
5283 <0 0x18220000 0 0x10000>;
5284 reg-names = "drv-0", "drv-1", "drv-2";
5288 qcom,tcs-offset = <0xd00>;
5355 reg = <0 0x18590000 0 0x1000>;
5363 reg = <0 0x18591000 0 0x1000>,
5364 <0 0x18592000 0 0x1000>,
5365 <0 0x18593000 0 0x1000>;
5376 polling-delay = <0>;
5395 hysteresis = <0>;
5420 polling-delay = <0>;
5439 hysteresis = <0>;
5464 polling-delay = <0>;
5483 hysteresis = <0>;
5508 polling-delay = <0>;
5527 hysteresis = <0>;
5552 polling-delay = <0>;
5571 hysteresis = <0>;
5596 polling-delay = <0>;
5615 hysteresis = <0>;
5640 polling-delay = <0>;
5659 hysteresis = <0>;
5684 polling-delay = <0>;
5703 hysteresis = <0>;
5728 polling-delay = <0>;
5747 hysteresis = <0>;
5772 polling-delay = <0>;
5791 hysteresis = <0>;
5816 polling-delay = <0>;
5835 hysteresis = <0>;
5860 polling-delay = <0>;
5879 hysteresis = <0>;
5903 polling-delay-passive = <0>;
5904 polling-delay = <0>;
5906 thermal-sensors = <&tsens0 0>;
5917 hysteresis = <0>;
5924 polling-delay-passive = <0>;
5925 polling-delay = <0>;
5927 thermal-sensors = <&tsens1 0>;
5938 hysteresis = <0>;
5945 polling-delay-passive = <0>;
5946 polling-delay = <0>;
5958 hysteresis = <0>;
5965 polling-delay-passive = <0>;
5966 polling-delay = <0>;
5978 hysteresis = <0>;
5986 polling-delay = <0>;
5999 hysteresis = <0>;
6014 polling-delay = <0>;
6027 hysteresis = <0>;
6041 polling-delay-passive = <0>;
6042 polling-delay = <0>;
6055 hysteresis = <0>;
6062 polling-delay-passive = <0>;
6063 polling-delay = <0>;
6076 hysteresis = <0>;
6083 polling-delay-passive = <0>;
6084 polling-delay = <0>;
6097 hysteresis = <0>;
6104 polling-delay-passive = <0>;
6105 polling-delay = <0>;
6118 hysteresis = <0>;
6125 polling-delay-passive = <0>;
6126 polling-delay = <0>;
6139 hysteresis = <0>;
6146 polling-delay-passive = <0>;
6147 polling-delay = <0>;
6160 hysteresis = <0>;
6167 polling-delay-passive = <0>;
6168 polling-delay = <0>;
6181 hysteresis = <0>;
6188 polling-delay-passive = <0>;
6189 polling-delay = <0>;
6202 hysteresis = <0>;
6209 polling-delay-passive = <0>;
6210 polling-delay = <0>;
6223 hysteresis = <0>;