Lines Matching +full:adreno +full:- +full:gmu +full:- +full:wrapper
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,icc.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sc7180.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/phy/phy-qcom-qusb2.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
59 xo_board: xo-board {
60 compatible = "fixed-clock";
61 clock-frequency = <38400000>;
62 #clock-cells = <0>;
65 sleep_clk: sleep-clk {
66 compatible = "fixed-clock";
67 clock-frequency = <32764>;
68 #clock-cells = <0>;
73 #address-cells = <2>;
74 #size-cells = <0>;
81 enable-method = "psci";
82 power-domains = <&CPU_PD0>;
83 power-domain-names = "psci";
84 capacity-dmips-mhz = <415>;
85 dynamic-power-coefficient = <137>;
86 operating-points-v2 = <&cpu0_opp_table>;
89 next-level-cache = <&L2_0>;
90 #cooling-cells = <2>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
92 L2_0: l2-cache {
94 cache-level = <2>;
95 cache-unified;
96 next-level-cache = <&L3_0>;
97 L3_0: l3-cache {
99 cache-level = <3>;
100 cache-unified;
110 enable-method = "psci";
111 power-domains = <&CPU_PD1>;
112 power-domain-names = "psci";
113 capacity-dmips-mhz = <415>;
114 dynamic-power-coefficient = <137>;
115 next-level-cache = <&L2_100>;
116 operating-points-v2 = <&cpu0_opp_table>;
119 #cooling-cells = <2>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
121 L2_100: l2-cache {
123 cache-level = <2>;
124 cache-unified;
125 next-level-cache = <&L3_0>;
134 enable-method = "psci";
135 power-domains = <&CPU_PD2>;
136 power-domain-names = "psci";
137 capacity-dmips-mhz = <415>;
138 dynamic-power-coefficient = <137>;
139 next-level-cache = <&L2_200>;
140 operating-points-v2 = <&cpu0_opp_table>;
143 #cooling-cells = <2>;
144 qcom,freq-domain = <&cpufreq_hw 0>;
145 L2_200: l2-cache {
147 cache-level = <2>;
148 cache-unified;
149 next-level-cache = <&L3_0>;
158 enable-method = "psci";
159 power-domains = <&CPU_PD3>;
160 power-domain-names = "psci";
161 capacity-dmips-mhz = <415>;
162 dynamic-power-coefficient = <137>;
163 next-level-cache = <&L2_300>;
164 operating-points-v2 = <&cpu0_opp_table>;
167 #cooling-cells = <2>;
168 qcom,freq-domain = <&cpufreq_hw 0>;
169 L2_300: l2-cache {
171 cache-level = <2>;
172 cache-unified;
173 next-level-cache = <&L3_0>;
182 enable-method = "psci";
183 power-domains = <&CPU_PD4>;
184 power-domain-names = "psci";
185 capacity-dmips-mhz = <415>;
186 dynamic-power-coefficient = <137>;
187 next-level-cache = <&L2_400>;
188 operating-points-v2 = <&cpu0_opp_table>;
191 #cooling-cells = <2>;
192 qcom,freq-domain = <&cpufreq_hw 0>;
193 L2_400: l2-cache {
195 cache-level = <2>;
196 cache-unified;
197 next-level-cache = <&L3_0>;
206 enable-method = "psci";
207 power-domains = <&CPU_PD5>;
208 power-domain-names = "psci";
209 capacity-dmips-mhz = <415>;
210 dynamic-power-coefficient = <137>;
211 next-level-cache = <&L2_500>;
212 operating-points-v2 = <&cpu0_opp_table>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 0>;
217 L2_500: l2-cache {
219 cache-level = <2>;
220 cache-unified;
221 next-level-cache = <&L3_0>;
230 enable-method = "psci";
231 power-domains = <&CPU_PD6>;
232 power-domain-names = "psci";
233 capacity-dmips-mhz = <1024>;
234 dynamic-power-coefficient = <480>;
235 next-level-cache = <&L2_600>;
236 operating-points-v2 = <&cpu6_opp_table>;
239 #cooling-cells = <2>;
240 qcom,freq-domain = <&cpufreq_hw 1>;
241 L2_600: l2-cache {
243 cache-level = <2>;
244 cache-unified;
245 next-level-cache = <&L3_0>;
254 enable-method = "psci";
255 power-domains = <&CPU_PD7>;
256 power-domain-names = "psci";
257 capacity-dmips-mhz = <1024>;
258 dynamic-power-coefficient = <480>;
259 next-level-cache = <&L2_700>;
260 operating-points-v2 = <&cpu6_opp_table>;
263 #cooling-cells = <2>;
264 qcom,freq-domain = <&cpufreq_hw 1>;
265 L2_700: l2-cache {
267 cache-level = <2>;
268 cache-unified;
269 next-level-cache = <&L3_0>;
273 cpu-map {
309 idle_states: idle-states {
310 entry-method = "psci";
312 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
313 compatible = "arm,idle-state";
314 idle-state-name = "little-power-down";
315 arm,psci-suspend-param = <0x40000003>;
316 entry-latency-us = <549>;
317 exit-latency-us = <901>;
318 min-residency-us = <1774>;
319 local-timer-stop;
322 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
323 compatible = "arm,idle-state";
324 idle-state-name = "little-rail-power-down";
325 arm,psci-suspend-param = <0x40000004>;
326 entry-latency-us = <702>;
327 exit-latency-us = <915>;
328 min-residency-us = <4001>;
329 local-timer-stop;
332 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
333 compatible = "arm,idle-state";
334 idle-state-name = "big-power-down";
335 arm,psci-suspend-param = <0x40000003>;
336 entry-latency-us = <523>;
337 exit-latency-us = <1244>;
338 min-residency-us = <2207>;
339 local-timer-stop;
342 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
343 compatible = "arm,idle-state";
344 idle-state-name = "big-rail-power-down";
345 arm,psci-suspend-param = <0x40000004>;
346 entry-latency-us = <526>;
347 exit-latency-us = <1854>;
348 min-residency-us = <5555>;
349 local-timer-stop;
353 domain_idle_states: domain-idle-states {
354 CLUSTER_SLEEP_PC: cluster-sleep-0 {
355 compatible = "domain-idle-state";
356 idle-state-name = "cluster-l3-power-collapse";
357 arm,psci-suspend-param = <0x41000044>;
358 entry-latency-us = <2752>;
359 exit-latency-us = <3048>;
360 min-residency-us = <6118>;
363 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
364 compatible = "domain-idle-state";
365 idle-state-name = "cluster-cx-retention";
366 arm,psci-suspend-param = <0x41001244>;
367 entry-latency-us = <3638>;
368 exit-latency-us = <4562>;
369 min-residency-us = <8467>;
372 CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
373 compatible = "domain-idle-state";
374 idle-state-name = "cluster-power-down";
375 arm,psci-suspend-param = <0x4100b244>;
376 entry-latency-us = <3263>;
377 exit-latency-us = <6562>;
378 min-residency-us = <9826>;
385 compatible = "qcom,scm-sc7180", "qcom,scm";
395 cpu0_opp_table: opp-table-cpu0 {
396 compatible = "operating-points-v2";
397 opp-shared;
399 cpu0_opp1: opp-300000000 {
400 opp-hz = /bits/ 64 <300000000>;
401 opp-peak-kBps = <1200000 4800000>;
404 cpu0_opp2: opp-576000000 {
405 opp-hz = /bits/ 64 <576000000>;
406 opp-peak-kBps = <1200000 4800000>;
409 cpu0_opp3: opp-768000000 {
410 opp-hz = /bits/ 64 <768000000>;
411 opp-peak-kBps = <1200000 4800000>;
414 cpu0_opp4: opp-1017600000 {
415 opp-hz = /bits/ 64 <1017600000>;
416 opp-peak-kBps = <1804000 8908800>;
419 cpu0_opp5: opp-1248000000 {
420 opp-hz = /bits/ 64 <1248000000>;
421 opp-peak-kBps = <2188000 12902400>;
424 cpu0_opp6: opp-1324800000 {
425 opp-hz = /bits/ 64 <1324800000>;
426 opp-peak-kBps = <2188000 12902400>;
429 cpu0_opp7: opp-1516800000 {
430 opp-hz = /bits/ 64 <1516800000>;
431 opp-peak-kBps = <3072000 15052800>;
434 cpu0_opp8: opp-1612800000 {
435 opp-hz = /bits/ 64 <1612800000>;
436 opp-peak-kBps = <3072000 15052800>;
439 cpu0_opp9: opp-1708800000 {
440 opp-hz = /bits/ 64 <1708800000>;
441 opp-peak-kBps = <3072000 15052800>;
444 cpu0_opp10: opp-1804800000 {
445 opp-hz = /bits/ 64 <1804800000>;
446 opp-peak-kBps = <4068000 22425600>;
450 cpu6_opp_table: opp-table-cpu6 {
451 compatible = "operating-points-v2";
452 opp-shared;
454 cpu6_opp1: opp-300000000 {
455 opp-hz = /bits/ 64 <300000000>;
456 opp-peak-kBps = <2188000 8908800>;
459 cpu6_opp2: opp-652800000 {
460 opp-hz = /bits/ 64 <652800000>;
461 opp-peak-kBps = <2188000 8908800>;
464 cpu6_opp3: opp-825600000 {
465 opp-hz = /bits/ 64 <825600000>;
466 opp-peak-kBps = <2188000 8908800>;
469 cpu6_opp4: opp-979200000 {
470 opp-hz = /bits/ 64 <979200000>;
471 opp-peak-kBps = <2188000 8908800>;
474 cpu6_opp5: opp-1113600000 {
475 opp-hz = /bits/ 64 <1113600000>;
476 opp-peak-kBps = <2188000 8908800>;
479 cpu6_opp6: opp-1267200000 {
480 opp-hz = /bits/ 64 <1267200000>;
481 opp-peak-kBps = <4068000 12902400>;
484 cpu6_opp7: opp-1555200000 {
485 opp-hz = /bits/ 64 <1555200000>;
486 opp-peak-kBps = <4068000 15052800>;
489 cpu6_opp8: opp-1708800000 {
490 opp-hz = /bits/ 64 <1708800000>;
491 opp-peak-kBps = <6220000 19353600>;
494 cpu6_opp9: opp-1843200000 {
495 opp-hz = /bits/ 64 <1843200000>;
496 opp-peak-kBps = <6220000 19353600>;
499 cpu6_opp10: opp-1900800000 {
500 opp-hz = /bits/ 64 <1900800000>;
501 opp-peak-kBps = <6220000 22425600>;
504 cpu6_opp11: opp-1996800000 {
505 opp-hz = /bits/ 64 <1996800000>;
506 opp-peak-kBps = <6220000 22425600>;
509 cpu6_opp12: opp-2112000000 {
510 opp-hz = /bits/ 64 <2112000000>;
511 opp-peak-kBps = <6220000 22425600>;
514 cpu6_opp13: opp-2208000000 {
515 opp-hz = /bits/ 64 <2208000000>;
516 opp-peak-kBps = <7216000 22425600>;
519 cpu6_opp14: opp-2323200000 {
520 opp-hz = /bits/ 64 <2323200000>;
521 opp-peak-kBps = <7216000 22425600>;
524 cpu6_opp15: opp-2400000000 {
525 opp-hz = /bits/ 64 <2400000000>;
526 opp-peak-kBps = <8532000 23347200>;
529 cpu6_opp16: opp-2553600000 {
530 opp-hz = /bits/ 64 <2553600000>;
531 opp-peak-kBps = <8532000 23347200>;
535 qspi_opp_table: opp-table-qspi {
536 compatible = "operating-points-v2";
538 opp-75000000 {
539 opp-hz = /bits/ 64 <75000000>;
540 required-opps = <&rpmhpd_opp_low_svs>;
543 opp-150000000 {
544 opp-hz = /bits/ 64 <150000000>;
545 required-opps = <&rpmhpd_opp_svs>;
548 opp-300000000 {
549 opp-hz = /bits/ 64 <300000000>;
550 required-opps = <&rpmhpd_opp_nom>;
554 qup_opp_table: opp-table-qup {
555 compatible = "operating-points-v2";
557 opp-75000000 {
558 opp-hz = /bits/ 64 <75000000>;
559 required-opps = <&rpmhpd_opp_low_svs>;
562 opp-100000000 {
563 opp-hz = /bits/ 64 <100000000>;
564 required-opps = <&rpmhpd_opp_svs>;
567 opp-128000000 {
568 opp-hz = /bits/ 64 <128000000>;
569 required-opps = <&rpmhpd_opp_nom>;
574 compatible = "arm,armv8-pmuv3";
579 compatible = "arm,psci-1.0";
583 #power-domain-cells = <0>;
584 power-domains = <&CLUSTER_PD>;
585 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
589 #power-domain-cells = <0>;
590 power-domains = <&CLUSTER_PD>;
591 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
595 #power-domain-cells = <0>;
596 power-domains = <&CLUSTER_PD>;
597 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
601 #power-domain-cells = <0>;
602 power-domains = <&CLUSTER_PD>;
603 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
607 #power-domain-cells = <0>;
608 power-domains = <&CLUSTER_PD>;
609 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
613 #power-domain-cells = <0>;
614 power-domains = <&CLUSTER_PD>;
615 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
619 #power-domain-cells = <0>;
620 power-domains = <&CLUSTER_PD>;
621 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
625 #power-domain-cells = <0>;
626 power-domains = <&CLUSTER_PD>;
627 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
630 CLUSTER_PD: cpu-cluster0 {
631 #power-domain-cells = <0>;
632 domain-idle-states = <&CLUSTER_SLEEP_PC
638 reserved_memory: reserved-memory {
639 #address-cells = <2>;
640 #size-cells = <2>;
645 no-map;
650 no-map;
655 no-map;
660 compatible = "qcom,cmd-db";
661 no-map;
666 no-map;
671 no-map;
676 no-map;
681 no-map;
685 compatible = "qcom,rmtfs-mem";
687 no-map;
689 qcom,client-id = <1>;
696 memory-region = <&smem_mem>;
700 smp2p-cdsp {
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <5>;
711 cdsp_smp2p_out: master-kernel {
712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells = <1>;
716 cdsp_smp2p_in: slave-kernel {
717 qcom,entry-name = "slave-kernel";
719 interrupt-controller;
720 #interrupt-cells = <2>;
724 smp2p-lpass {
732 qcom,local-pid = <0>;
733 qcom,remote-pid = <2>;
735 adsp_smp2p_out: master-kernel {
736 qcom,entry-name = "master-kernel";
737 #qcom,smem-state-cells = <1>;
740 adsp_smp2p_in: slave-kernel {
741 qcom,entry-name = "slave-kernel";
743 interrupt-controller;
744 #interrupt-cells = <2>;
748 smp2p-mpss {
753 qcom,local-pid = <0>;
754 qcom,remote-pid = <1>;
756 modem_smp2p_out: master-kernel {
757 qcom,entry-name = "master-kernel";
758 #qcom,smem-state-cells = <1>;
761 modem_smp2p_in: slave-kernel {
762 qcom,entry-name = "slave-kernel";
763 interrupt-controller;
764 #interrupt-cells = <2>;
767 ipa_smp2p_out: ipa-ap-to-modem {
768 qcom,entry-name = "ipa";
769 #qcom,smem-state-cells = <1>;
772 ipa_smp2p_in: ipa-modem-to-ap {
773 qcom,entry-name = "ipa";
774 interrupt-controller;
775 #interrupt-cells = <2>;
780 #address-cells = <2>;
781 #size-cells = <2>;
783 dma-ranges = <0 0 0 0 0x10 0>;
784 compatible = "simple-bus";
786 gcc: clock-controller@100000 {
787 compatible = "qcom,gcc-sc7180";
792 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
793 #clock-cells = <1>;
794 #reset-cells = <1>;
795 #power-domain-cells = <1>;
796 power-domains = <&rpmhpd SC7180_CX>;
800 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
807 clock-names = "core";
808 #address-cells = <1>;
809 #size-cells = <1>;
811 qusb2p_hstx_trim: hstx-trim-primary@25b {
823 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
826 reg-names = "hc", "cqhci";
831 interrupt-names = "hc_irq", "pwr_irq";
836 clock-names = "iface", "core", "xo";
839 interconnect-names = "sdhc-ddr","cpu-sdhc";
840 power-domains = <&rpmhpd SC7180_CX>;
841 operating-points-v2 = <&sdhc1_opp_table>;
843 bus-width = <8>;
844 non-removable;
845 supports-cqe;
847 mmc-ddr-1_8v;
848 mmc-hs200-1_8v;
849 mmc-hs400-1_8v;
850 mmc-hs400-enhanced-strobe;
854 sdhc1_opp_table: opp-table {
855 compatible = "operating-points-v2";
857 opp-100000000 {
858 opp-hz = /bits/ 64 <100000000>;
859 required-opps = <&rpmhpd_opp_low_svs>;
860 opp-peak-kBps = <1800000 600000>;
861 opp-avg-kBps = <100000 0>;
864 opp-384000000 {
865 opp-hz = /bits/ 64 <384000000>;
866 required-opps = <&rpmhpd_opp_nom>;
867 opp-peak-kBps = <5400000 1600000>;
868 opp-avg-kBps = <390000 0>;
874 compatible = "qcom,geni-se-qup";
876 clock-names = "m-ahb", "s-ahb";
879 #address-cells = <2>;
880 #size-cells = <2>;
886 compatible = "qcom,geni-i2c";
888 clock-names = "se";
890 pinctrl-names = "default";
891 pinctrl-0 = <&qup_i2c0_default>;
893 #address-cells = <1>;
894 #size-cells = <0>;
898 interconnect-names = "qup-core", "qup-config",
899 "qup-memory";
900 power-domains = <&rpmhpd SC7180_CX>;
901 required-opps = <&rpmhpd_opp_low_svs>;
906 compatible = "qcom,geni-spi";
908 clock-names = "se";
910 pinctrl-names = "default";
911 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
913 #address-cells = <1>;
914 #size-cells = <0>;
915 power-domains = <&rpmhpd SC7180_CX>;
916 operating-points-v2 = <&qup_opp_table>;
919 interconnect-names = "qup-core", "qup-config";
924 compatible = "qcom,geni-uart";
926 clock-names = "se";
928 pinctrl-names = "default";
929 pinctrl-0 = <&qup_uart0_default>;
931 power-domains = <&rpmhpd SC7180_CX>;
932 operating-points-v2 = <&qup_opp_table>;
935 interconnect-names = "qup-core", "qup-config";
940 compatible = "qcom,geni-i2c";
942 clock-names = "se";
944 pinctrl-names = "default";
945 pinctrl-0 = <&qup_i2c1_default>;
947 #address-cells = <1>;
948 #size-cells = <0>;
952 interconnect-names = "qup-core", "qup-config",
953 "qup-memory";
954 power-domains = <&rpmhpd SC7180_CX>;
955 required-opps = <&rpmhpd_opp_low_svs>;
960 compatible = "qcom,geni-spi";
962 clock-names = "se";
964 pinctrl-names = "default";
965 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
967 #address-cells = <1>;
968 #size-cells = <0>;
969 power-domains = <&rpmhpd SC7180_CX>;
970 operating-points-v2 = <&qup_opp_table>;
973 interconnect-names = "qup-core", "qup-config";
978 compatible = "qcom,geni-uart";
980 clock-names = "se";
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_uart1_default>;
985 power-domains = <&rpmhpd SC7180_CX>;
986 operating-points-v2 = <&qup_opp_table>;
989 interconnect-names = "qup-core", "qup-config";
994 compatible = "qcom,geni-i2c";
996 clock-names = "se";
998 pinctrl-names = "default";
999 pinctrl-0 = <&qup_i2c2_default>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1006 interconnect-names = "qup-core", "qup-config",
1007 "qup-memory";
1008 power-domains = <&rpmhpd SC7180_CX>;
1009 required-opps = <&rpmhpd_opp_low_svs>;
1014 compatible = "qcom,geni-uart";
1016 clock-names = "se";
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_uart2_default>;
1021 power-domains = <&rpmhpd SC7180_CX>;
1022 operating-points-v2 = <&qup_opp_table>;
1025 interconnect-names = "qup-core", "qup-config";
1030 compatible = "qcom,geni-i2c";
1032 clock-names = "se";
1034 pinctrl-names = "default";
1035 pinctrl-0 = <&qup_i2c3_default>;
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1042 interconnect-names = "qup-core", "qup-config",
1043 "qup-memory";
1044 power-domains = <&rpmhpd SC7180_CX>;
1045 required-opps = <&rpmhpd_opp_low_svs>;
1050 compatible = "qcom,geni-spi";
1052 clock-names = "se";
1054 pinctrl-names = "default";
1055 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059 power-domains = <&rpmhpd SC7180_CX>;
1060 operating-points-v2 = <&qup_opp_table>;
1063 interconnect-names = "qup-core", "qup-config";
1068 compatible = "qcom,geni-uart";
1070 clock-names = "se";
1072 pinctrl-names = "default";
1073 pinctrl-0 = <&qup_uart3_default>;
1075 power-domains = <&rpmhpd SC7180_CX>;
1076 operating-points-v2 = <&qup_opp_table>;
1079 interconnect-names = "qup-core", "qup-config";
1084 compatible = "qcom,geni-i2c";
1086 clock-names = "se";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&qup_i2c4_default>;
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1096 interconnect-names = "qup-core", "qup-config",
1097 "qup-memory";
1098 power-domains = <&rpmhpd SC7180_CX>;
1099 required-opps = <&rpmhpd_opp_low_svs>;
1104 compatible = "qcom,geni-uart";
1106 clock-names = "se";
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&qup_uart4_default>;
1111 power-domains = <&rpmhpd SC7180_CX>;
1112 operating-points-v2 = <&qup_opp_table>;
1115 interconnect-names = "qup-core", "qup-config";
1120 compatible = "qcom,geni-i2c";
1122 clock-names = "se";
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&qup_i2c5_default>;
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1132 interconnect-names = "qup-core", "qup-config",
1133 "qup-memory";
1134 power-domains = <&rpmhpd SC7180_CX>;
1135 required-opps = <&rpmhpd_opp_low_svs>;
1140 compatible = "qcom,geni-spi";
1142 clock-names = "se";
1144 pinctrl-names = "default";
1145 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 power-domains = <&rpmhpd SC7180_CX>;
1150 operating-points-v2 = <&qup_opp_table>;
1153 interconnect-names = "qup-core", "qup-config";
1158 compatible = "qcom,geni-uart";
1160 clock-names = "se";
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_uart5_default>;
1165 power-domains = <&rpmhpd SC7180_CX>;
1166 operating-points-v2 = <&qup_opp_table>;
1169 interconnect-names = "qup-core", "qup-config";
1175 compatible = "qcom,geni-se-qup";
1177 clock-names = "m-ahb", "s-ahb";
1180 #address-cells = <2>;
1181 #size-cells = <2>;
1187 compatible = "qcom,geni-i2c";
1189 clock-names = "se";
1191 pinctrl-names = "default";
1192 pinctrl-0 = <&qup_i2c6_default>;
1194 #address-cells = <1>;
1195 #size-cells = <0>;
1199 interconnect-names = "qup-core", "qup-config",
1200 "qup-memory";
1201 power-domains = <&rpmhpd SC7180_CX>;
1202 required-opps = <&rpmhpd_opp_low_svs>;
1207 compatible = "qcom,geni-spi";
1209 clock-names = "se";
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216 power-domains = <&rpmhpd SC7180_CX>;
1217 operating-points-v2 = <&qup_opp_table>;
1220 interconnect-names = "qup-core", "qup-config";
1225 compatible = "qcom,geni-uart";
1227 clock-names = "se";
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_uart6_default>;
1232 power-domains = <&rpmhpd SC7180_CX>;
1233 operating-points-v2 = <&qup_opp_table>;
1236 interconnect-names = "qup-core", "qup-config";
1241 compatible = "qcom,geni-i2c";
1243 clock-names = "se";
1245 pinctrl-names = "default";
1246 pinctrl-0 = <&qup_i2c7_default>;
1248 #address-cells = <1>;
1249 #size-cells = <0>;
1253 interconnect-names = "qup-core", "qup-config",
1254 "qup-memory";
1255 power-domains = <&rpmhpd SC7180_CX>;
1256 required-opps = <&rpmhpd_opp_low_svs>;
1261 compatible = "qcom,geni-uart";
1263 clock-names = "se";
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&qup_uart7_default>;
1268 power-domains = <&rpmhpd SC7180_CX>;
1269 operating-points-v2 = <&qup_opp_table>;
1272 interconnect-names = "qup-core", "qup-config";
1277 compatible = "qcom,geni-i2c";
1279 clock-names = "se";
1281 pinctrl-names = "default";
1282 pinctrl-0 = <&qup_i2c8_default>;
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1289 interconnect-names = "qup-core", "qup-config",
1290 "qup-memory";
1291 power-domains = <&rpmhpd SC7180_CX>;
1292 required-opps = <&rpmhpd_opp_low_svs>;
1297 compatible = "qcom,geni-spi";
1299 clock-names = "se";
1301 pinctrl-names = "default";
1302 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1306 power-domains = <&rpmhpd SC7180_CX>;
1307 operating-points-v2 = <&qup_opp_table>;
1310 interconnect-names = "qup-core", "qup-config";
1315 compatible = "qcom,geni-debug-uart";
1317 clock-names = "se";
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_uart8_default>;
1322 power-domains = <&rpmhpd SC7180_CX>;
1323 operating-points-v2 = <&qup_opp_table>;
1326 interconnect-names = "qup-core", "qup-config";
1331 compatible = "qcom,geni-i2c";
1333 clock-names = "se";
1335 pinctrl-names = "default";
1336 pinctrl-0 = <&qup_i2c9_default>;
1338 #address-cells = <1>;
1339 #size-cells = <0>;
1343 interconnect-names = "qup-core", "qup-config",
1344 "qup-memory";
1345 power-domains = <&rpmhpd SC7180_CX>;
1346 required-opps = <&rpmhpd_opp_low_svs>;
1351 compatible = "qcom,geni-uart";
1353 clock-names = "se";
1355 pinctrl-names = "default";
1356 pinctrl-0 = <&qup_uart9_default>;
1358 power-domains = <&rpmhpd SC7180_CX>;
1359 operating-points-v2 = <&qup_opp_table>;
1362 interconnect-names = "qup-core", "qup-config";
1367 compatible = "qcom,geni-i2c";
1369 clock-names = "se";
1371 pinctrl-names = "default";
1372 pinctrl-0 = <&qup_i2c10_default>;
1374 #address-cells = <1>;
1375 #size-cells = <0>;
1379 interconnect-names = "qup-core", "qup-config",
1380 "qup-memory";
1381 power-domains = <&rpmhpd SC7180_CX>;
1382 required-opps = <&rpmhpd_opp_low_svs>;
1387 compatible = "qcom,geni-spi";
1389 clock-names = "se";
1391 pinctrl-names = "default";
1392 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1396 power-domains = <&rpmhpd SC7180_CX>;
1397 operating-points-v2 = <&qup_opp_table>;
1400 interconnect-names = "qup-core", "qup-config";
1405 compatible = "qcom,geni-uart";
1407 clock-names = "se";
1409 pinctrl-names = "default";
1410 pinctrl-0 = <&qup_uart10_default>;
1412 power-domains = <&rpmhpd SC7180_CX>;
1413 operating-points-v2 = <&qup_opp_table>;
1416 interconnect-names = "qup-core", "qup-config";
1421 compatible = "qcom,geni-i2c";
1423 clock-names = "se";
1425 pinctrl-names = "default";
1426 pinctrl-0 = <&qup_i2c11_default>;
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1433 interconnect-names = "qup-core", "qup-config",
1434 "qup-memory";
1435 power-domains = <&rpmhpd SC7180_CX>;
1436 required-opps = <&rpmhpd_opp_low_svs>;
1441 compatible = "qcom,geni-spi";
1443 clock-names = "se";
1445 pinctrl-names = "default";
1446 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 power-domains = <&rpmhpd SC7180_CX>;
1451 operating-points-v2 = <&qup_opp_table>;
1454 interconnect-names = "qup-core", "qup-config";
1459 compatible = "qcom,geni-uart";
1461 clock-names = "se";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_uart11_default>;
1466 power-domains = <&rpmhpd SC7180_CX>;
1467 operating-points-v2 = <&qup_opp_table>;
1470 interconnect-names = "qup-core", "qup-config";
1476 compatible = "qcom,sc7180-config-noc";
1478 #interconnect-cells = <2>;
1479 qcom,bcm-voters = <&apps_bcm_voter>;
1483 compatible = "qcom,sc7180-system-noc";
1485 #interconnect-cells = <2>;
1486 qcom,bcm-voters = <&apps_bcm_voter>;
1490 compatible = "qcom,sc7180-mc-virt";
1492 #interconnect-cells = <2>;
1493 qcom,bcm-voters = <&apps_bcm_voter>;
1497 compatible = "qcom,sc7180-qup-virt";
1499 #interconnect-cells = <2>;
1500 qcom,bcm-voters = <&apps_bcm_voter>;
1504 compatible = "qcom,sc7180-aggre1-noc";
1506 #interconnect-cells = <2>;
1507 qcom,bcm-voters = <&apps_bcm_voter>;
1511 compatible = "qcom,sc7180-aggre2-noc";
1513 #interconnect-cells = <2>;
1514 qcom,bcm-voters = <&apps_bcm_voter>;
1518 compatible = "qcom,sc7180-compute-noc";
1520 #interconnect-cells = <2>;
1521 qcom,bcm-voters = <&apps_bcm_voter>;
1525 compatible = "qcom,sc7180-mmss-noc";
1527 #interconnect-cells = <2>;
1528 qcom,bcm-voters = <&apps_bcm_voter>;
1532 compatible = "qcom,sc7180-ipa";
1539 reg-names = "ipa-reg",
1540 "ipa-shared",
1543 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1547 interrupt-names = "ipa",
1549 "ipa-clock-query",
1550 "ipa-setup-ready";
1553 clock-names = "core";
1558 interconnect-names = "memory",
1564 qcom,smem-states = <&ipa_smp2p_out 0>,
1566 qcom,smem-state-names = "ipa-clock-enabled-valid",
1567 "ipa-clock-enabled";
1573 compatible = "qcom,tcsr-mutex";
1575 #hwlock-cells = <1>;
1579 compatible = "qcom,sc7180-tcsr", "syscon";
1584 compatible = "qcom,sc7180-tcsr", "syscon";
1589 compatible = "qcom,sc7180-pinctrl";
1593 reg-names = "west", "north", "south";
1595 gpio-controller;
1596 #gpio-cells = <2>;
1597 interrupt-controller;
1598 #interrupt-cells = <2>;
1599 gpio-ranges = <&tlmm 0 0 120>;
1600 wakeup-parent = <&pdc>;
1602 dp_hot_plug_det: dp-hot-plug-det-state {
1607 qspi_clk: qspi-clk-state {
1612 qspi_cs0: qspi-cs0-state {
1617 qspi_cs1: qspi-cs1-state {
1622 qspi_data0: qspi-data0-state {
1627 qspi_data1: qspi-data1-state {
1632 qspi_data23: qspi-data23-state {
1637 qup_i2c0_default: qup-i2c0-default-state {
1642 qup_i2c1_default: qup-i2c1-default-state {
1647 qup_i2c2_default: qup-i2c2-default-state {
1652 qup_i2c3_default: qup-i2c3-default-state {
1657 qup_i2c4_default: qup-i2c4-default-state {
1662 qup_i2c5_default: qup-i2c5-default-state {
1667 qup_i2c6_default: qup-i2c6-default-state {
1672 qup_i2c7_default: qup-i2c7-default-state {
1677 qup_i2c8_default: qup-i2c8-default-state {
1682 qup_i2c9_default: qup-i2c9-default-state {
1687 qup_i2c10_default: qup-i2c10-default-state {
1692 qup_i2c11_default: qup-i2c11-default-state {
1697 qup_spi0_spi: qup-spi0-spi-state {
1702 qup_spi0_cs: qup-spi0-cs-state {
1707 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1712 qup_spi1_spi: qup-spi1-spi-state {
1717 qup_spi1_cs: qup-spi1-cs-state {
1722 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1727 qup_spi3_spi: qup-spi3-spi-state {
1732 qup_spi3_cs: qup-spi3-cs-state {
1737 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1742 qup_spi5_spi: qup-spi5-spi-state {
1747 qup_spi5_cs: qup-spi5-cs-state {
1752 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1757 qup_spi6_spi: qup-spi6-spi-state {
1762 qup_spi6_cs: qup-spi6-cs-state {
1767 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1772 qup_spi8_spi: qup-spi8-spi-state {
1777 qup_spi8_cs: qup-spi8-cs-state {
1782 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1787 qup_spi10_spi: qup-spi10-spi-state {
1792 qup_spi10_cs: qup-spi10-cs-state {
1797 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1802 qup_spi11_spi: qup-spi11-spi-state {
1807 qup_spi11_cs: qup-spi11-cs-state {
1812 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1817 qup_uart0_default: qup-uart0-default-state {
1818 qup_uart0_cts: cts-pins {
1823 qup_uart0_rts: rts-pins {
1828 qup_uart0_tx: tx-pins {
1833 qup_uart0_rx: rx-pins {
1839 qup_uart1_default: qup-uart1-default-state {
1840 qup_uart1_cts: cts-pins {
1845 qup_uart1_rts: rts-pins {
1850 qup_uart1_tx: tx-pins {
1855 qup_uart1_rx: rx-pins {
1861 qup_uart2_default: qup-uart2-default-state {
1862 qup_uart2_tx: tx-pins {
1867 qup_uart2_rx: rx-pins {
1873 qup_uart3_default: qup-uart3-default-state {
1874 qup_uart3_cts: cts-pins {
1879 qup_uart3_rts: rts-pins {
1884 qup_uart3_tx: tx-pins {
1889 qup_uart3_rx: rx-pins {
1895 qup_uart4_default: qup-uart4-default-state {
1896 qup_uart4_tx: tx-pins {
1901 qup_uart4_rx: rx-pins {
1907 qup_uart5_default: qup-uart5-default-state {
1908 qup_uart5_cts: cts-pins {
1913 qup_uart5_rts: rts-pins {
1918 qup_uart5_tx: tx-pins {
1923 qup_uart5_rx: rx-pins {
1929 qup_uart6_default: qup-uart6-default-state {
1930 qup_uart6_cts: cts-pins {
1935 qup_uart6_rts: rts-pins {
1940 qup_uart6_tx: tx-pins {
1945 qup_uart6_rx: rx-pins {
1951 qup_uart7_default: qup-uart7-default-state {
1952 qup_uart7_tx: tx-pins {
1957 qup_uart7_rx: rx-pins {
1963 qup_uart8_default: qup-uart8-default-state {
1964 qup_uart8_tx: tx-pins {
1969 qup_uart8_rx: rx-pins {
1975 qup_uart9_default: qup-uart9-default-state {
1976 qup_uart9_tx: tx-pins {
1981 qup_uart9_rx: rx-pins {
1987 qup_uart10_default: qup-uart10-default-state {
1988 qup_uart10_cts: cts-pins {
1993 qup_uart10_rts: rts-pins {
1998 qup_uart10_tx: tx-pins {
2003 qup_uart10_rx: rx-pins {
2009 qup_uart11_default: qup-uart11-default-state {
2010 qup_uart11_cts: cts-pins {
2015 qup_uart11_rts: rts-pins {
2020 qup_uart11_tx: tx-pins {
2025 qup_uart11_rx: rx-pins {
2031 sec_mi2s_active: sec-mi2s-active-state {
2036 pri_mi2s_active: pri-mi2s-active-state {
2041 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
2048 compatible = "qcom,sc7180-mpss-pas";
2051 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2057 interrupt-names = "wdog", "fatal", "ready", "handover",
2058 "stop-ack", "shutdown-ack";
2061 clock-names = "xo";
2063 power-domains = <&rpmhpd SC7180_CX>,
2066 power-domain-names = "cx", "mx", "mss";
2068 memory-region = <&mpss_mem>;
2072 qcom,smem-states = <&modem_smp2p_out 0>;
2073 qcom,smem-state-names = "stop";
2077 glink-edge {
2080 qcom,remote-pid = <1>;
2086 compatible = "qcom,adreno-618.0", "qcom,adreno";
2089 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2092 operating-points-v2 = <&gpu_opp_table>;
2093 qcom,gmu = <&gmu>;
2095 #cooling-cells = <2>;
2097 nvmem-cells = <&gpu_speed_bin>;
2098 nvmem-cell-names = "speed_bin";
2101 interconnect-names = "gfx-mem";
2103 gpu_opp_table: opp-table {
2104 compatible = "operating-points-v2";
2106 opp-825000000 {
2107 opp-hz = /bits/ 64 <825000000>;
2108 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2109 opp-peak-kBps = <8532000>;
2110 opp-supported-hw = <0x04>;
2113 opp-800000000 {
2114 opp-hz = /bits/ 64 <800000000>;
2115 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2116 opp-peak-kBps = <8532000>;
2117 opp-supported-hw = <0x07>;
2120 opp-650000000 {
2121 opp-hz = /bits/ 64 <650000000>;
2122 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2123 opp-peak-kBps = <7216000>;
2124 opp-supported-hw = <0x07>;
2127 opp-565000000 {
2128 opp-hz = /bits/ 64 <565000000>;
2129 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2130 opp-peak-kBps = <5412000>;
2131 opp-supported-hw = <0x07>;
2134 opp-430000000 {
2135 opp-hz = /bits/ 64 <430000000>;
2136 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2137 opp-peak-kBps = <5412000>;
2138 opp-supported-hw = <0x07>;
2141 opp-355000000 {
2142 opp-hz = /bits/ 64 <355000000>;
2143 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2144 opp-peak-kBps = <3072000>;
2145 opp-supported-hw = <0x07>;
2148 opp-267000000 {
2149 opp-hz = /bits/ 64 <267000000>;
2150 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2151 opp-peak-kBps = <3072000>;
2152 opp-supported-hw = <0x07>;
2155 opp-180000000 {
2156 opp-hz = /bits/ 64 <180000000>;
2157 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2158 opp-peak-kBps = <1804000>;
2159 opp-supported-hw = <0x07>;
2165 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2167 #iommu-cells = <1>;
2168 #global-interrupts = <2>;
2182 clock-names = "bus", "iface";
2184 power-domains = <&gpucc CX_GDSC>;
2187 gmu: gmu@506a000 { label
2188 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2191 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2194 interrupt-names = "hfi", "gmu";
2199 clock-names = "gmu", "cxo", "axi", "memnoc";
2200 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2201 power-domain-names = "cx", "gx";
2203 operating-points-v2 = <&gmu_opp_table>;
2205 gmu_opp_table: opp-table {
2206 compatible = "operating-points-v2";
2208 opp-200000000 {
2209 opp-hz = /bits/ 64 <200000000>;
2210 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2215 gpucc: clock-controller@5090000 {
2216 compatible = "qcom,sc7180-gpucc";
2221 clock-names = "bi_tcxo",
2224 #clock-cells = <1>;
2225 #reset-cells = <1>;
2226 #power-domain-cells = <1>;
2230 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2236 compatible = "arm,coresight-stm", "arm,primecell";
2239 reg-names = "stm-base", "stm-stimulus-base";
2242 clock-names = "apb_pclk";
2244 out-ports {
2247 remote-endpoint = <&funnel0_in7>;
2254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2258 clock-names = "apb_pclk";
2260 out-ports {
2263 remote-endpoint = <&merge_funnel_in0>;
2268 in-ports {
2269 #address-cells = <1>;
2270 #size-cells = <0>;
2275 remote-endpoint = <&stm_out>;
2282 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2286 clock-names = "apb_pclk";
2288 out-ports {
2291 remote-endpoint = <&merge_funnel_in1>;
2296 in-ports {
2297 #address-cells = <1>;
2298 #size-cells = <0>;
2303 remote-endpoint = <&apss_merge_funnel_out>;
2310 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2314 clock-names = "apb_pclk";
2316 out-ports {
2319 remote-endpoint = <&swao_funnel_in>;
2324 in-ports {
2325 #address-cells = <1>;
2326 #size-cells = <0>;
2331 remote-endpoint = <&funnel0_out>;
2338 remote-endpoint = <&funnel1_out>;
2345 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2349 clock-names = "apb_pclk";
2351 out-ports {
2354 remote-endpoint = <&etr_in>;
2359 in-ports {
2362 remote-endpoint = <&swao_replicator_out>;
2369 compatible = "arm,coresight-tmc", "arm,primecell";
2374 clock-names = "apb_pclk";
2375 arm,scatter-gather;
2377 in-ports {
2380 remote-endpoint = <&replicator_out>;
2387 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2391 clock-names = "apb_pclk";
2393 out-ports {
2396 remote-endpoint = <&etf_in>;
2401 in-ports {
2402 #address-cells = <1>;
2403 #size-cells = <0>;
2408 remote-endpoint = <&merge_funnel_out>;
2415 compatible = "arm,coresight-tmc", "arm,primecell";
2419 clock-names = "apb_pclk";
2421 out-ports {
2424 remote-endpoint = <&swao_replicator_in>;
2429 in-ports {
2432 remote-endpoint = <&swao_funnel_out>;
2439 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2443 clock-names = "apb_pclk";
2444 qcom,replicator-loses-context;
2446 out-ports {
2449 remote-endpoint = <&replicator_in>;
2454 in-ports {
2457 remote-endpoint = <&etf_out>;
2464 compatible = "arm,coresight-etm4x", "arm,primecell";
2470 clock-names = "apb_pclk";
2471 arm,coresight-loses-context-with-cpu;
2472 qcom,skip-power-up;
2474 out-ports {
2477 remote-endpoint = <&apss_funnel_in0>;
2484 compatible = "arm,coresight-etm4x", "arm,primecell";
2490 clock-names = "apb_pclk";
2491 arm,coresight-loses-context-with-cpu;
2492 qcom,skip-power-up;
2494 out-ports {
2497 remote-endpoint = <&apss_funnel_in1>;
2504 compatible = "arm,coresight-etm4x", "arm,primecell";
2510 clock-names = "apb_pclk";
2511 arm,coresight-loses-context-with-cpu;
2512 qcom,skip-power-up;
2514 out-ports {
2517 remote-endpoint = <&apss_funnel_in2>;
2524 compatible = "arm,coresight-etm4x", "arm,primecell";
2530 clock-names = "apb_pclk";
2531 arm,coresight-loses-context-with-cpu;
2532 qcom,skip-power-up;
2534 out-ports {
2537 remote-endpoint = <&apss_funnel_in3>;
2544 compatible = "arm,coresight-etm4x", "arm,primecell";
2550 clock-names = "apb_pclk";
2551 arm,coresight-loses-context-with-cpu;
2552 qcom,skip-power-up;
2554 out-ports {
2557 remote-endpoint = <&apss_funnel_in4>;
2564 compatible = "arm,coresight-etm4x", "arm,primecell";
2570 clock-names = "apb_pclk";
2571 arm,coresight-loses-context-with-cpu;
2572 qcom,skip-power-up;
2574 out-ports {
2577 remote-endpoint = <&apss_funnel_in5>;
2584 compatible = "arm,coresight-etm4x", "arm,primecell";
2590 clock-names = "apb_pclk";
2591 arm,coresight-loses-context-with-cpu;
2592 qcom,skip-power-up;
2594 out-ports {
2597 remote-endpoint = <&apss_funnel_in6>;
2604 compatible = "arm,coresight-etm4x", "arm,primecell";
2610 clock-names = "apb_pclk";
2611 arm,coresight-loses-context-with-cpu;
2612 qcom,skip-power-up;
2614 out-ports {
2617 remote-endpoint = <&apss_funnel_in7>;
2624 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2628 clock-names = "apb_pclk";
2630 out-ports {
2633 remote-endpoint = <&apss_merge_funnel_in>;
2638 in-ports {
2639 #address-cells = <1>;
2640 #size-cells = <0>;
2645 remote-endpoint = <&etm0_out>;
2652 remote-endpoint = <&etm1_out>;
2659 remote-endpoint = <&etm2_out>;
2666 remote-endpoint = <&etm3_out>;
2673 remote-endpoint = <&etm4_out>;
2680 remote-endpoint = <&etm5_out>;
2687 remote-endpoint = <&etm6_out>;
2694 remote-endpoint = <&etm7_out>;
2701 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2705 clock-names = "apb_pclk";
2707 out-ports {
2710 remote-endpoint = <&funnel1_in4>;
2715 in-ports {
2718 remote-endpoint = <&apss_funnel_out>;
2725 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2731 interrupt-names = "hc_irq", "pwr_irq";
2736 clock-names = "iface", "core", "xo";
2740 interconnect-names = "sdhc-ddr","cpu-sdhc";
2741 power-domains = <&rpmhpd SC7180_CX>;
2742 operating-points-v2 = <&sdhc2_opp_table>;
2744 bus-width = <4>;
2748 sdhc2_opp_table: opp-table {
2749 compatible = "operating-points-v2";
2751 opp-100000000 {
2752 opp-hz = /bits/ 64 <100000000>;
2753 required-opps = <&rpmhpd_opp_low_svs>;
2754 opp-peak-kBps = <1800000 600000>;
2755 opp-avg-kBps = <100000 0>;
2758 opp-202000000 {
2759 opp-hz = /bits/ 64 <202000000>;
2760 required-opps = <&rpmhpd_opp_nom>;
2761 opp-peak-kBps = <5400000 1600000>;
2762 opp-avg-kBps = <200000 0>;
2768 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2771 #address-cells = <1>;
2772 #size-cells = <0>;
2776 clock-names = "iface", "core";
2779 interconnect-names = "qspi-config";
2780 power-domains = <&rpmhpd SC7180_CX>;
2781 operating-points-v2 = <&qspi_opp_table>;
2786 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2789 #phy-cells = <0>;
2792 clock-names = "cfg_ahb", "ref";
2795 nvmem-cells = <&qusb2p_hstx_trim>;
2798 usb_1_qmpphy: phy-wrapper@88e9000 {
2799 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2804 #address-cells = <2>;
2805 #size-cells = <2>;
2812 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2816 reset-names = "phy", "common";
2818 usb_1_ssphy: usb3-phy@88e9200 {
2825 #clock-cells = <0>;
2826 #phy-cells = <0>;
2828 clock-names = "pipe0";
2829 clock-output-names = "usb3_phy_pipe_clk_src";
2832 dp_phy: dp-phy@88ea200 {
2838 #clock-cells = <1>;
2839 #phy-cells = <0>;
2844 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon";
2850 operating-points-v2 = <&cpu_bwmon_opp_table>;
2852 cpu_bwmon_opp_table: opp-table {
2853 compatible = "operating-points-v2";
2855 opp-0 {
2856 opp-peak-kBps = <2288000>;
2859 opp-1 {
2860 opp-peak-kBps = <4577000>;
2863 opp-2 {
2864 opp-peak-kBps = <7110000>;
2867 opp-3 {
2868 opp-peak-kBps = <9155000>;
2871 opp-4 {
2872 opp-peak-kBps = <12298000>;
2875 opp-5 {
2876 opp-peak-kBps = <14236000>;
2882 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
2888 operating-points-v2 = <&llcc_bwmon_opp_table>;
2890 llcc_bwmon_opp_table: opp-table {
2891 compatible = "operating-points-v2";
2893 opp-0 {
2894 opp-peak-kBps = <1144000>;
2897 opp-1 {
2898 opp-peak-kBps = <1720000>;
2901 opp-2 {
2902 opp-peak-kBps = <2086000>;
2905 opp-3 {
2906 opp-peak-kBps = <2929000>;
2909 opp-4 {
2910 opp-peak-kBps = <3879000>;
2913 opp-5 {
2914 opp-peak-kBps = <5931000>;
2917 opp-6 {
2918 opp-peak-kBps = <6881000>;
2921 opp-7 {
2922 opp-peak-kBps = <8137000>;
2928 compatible = "qcom,sc7180-dc-noc";
2930 #interconnect-cells = <2>;
2931 qcom,bcm-voters = <&apps_bcm_voter>;
2934 system-cache-controller@9200000 {
2935 compatible = "qcom,sc7180-llcc";
2937 reg-names = "llcc0_base", "llcc_broadcast_base";
2942 compatible = "qcom,sc7180-gem-noc";
2944 #interconnect-cells = <2>;
2945 qcom,bcm-voters = <&apps_bcm_voter>;
2949 compatible = "qcom,sc7180-npu-noc";
2951 #interconnect-cells = <2>;
2952 qcom,bcm-voters = <&apps_bcm_voter>;
2956 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2959 #address-cells = <2>;
2960 #size-cells = <2>;
2962 dma-ranges;
2969 clock-names = "cfg_noc",
2975 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2977 assigned-clock-rates = <19200000>, <150000000>;
2979 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2983 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2986 power-domains = <&gcc USB30_PRIM_GDSC>;
2987 required-opps = <&rpmhpd_opp_nom>;
2993 interconnect-names = "usb-ddr", "apps-usb";
2995 wakeup-source;
3005 phy-names = "usb2-phy", "usb3-phy";
3006 maximum-speed = "super-speed";
3010 venus: video-codec@aa00000 {
3011 compatible = "qcom,sc7180-venus";
3014 power-domains = <&videocc VENUS_GDSC>,
3017 power-domain-names = "venus", "vcodec0", "cx";
3018 operating-points-v2 = <&venus_opp_table>;
3024 clock-names = "core", "iface", "bus",
3027 memory-region = <&venus_mem>;
3030 interconnect-names = "video-mem", "cpu-cfg";
3032 video-decoder {
3033 compatible = "venus-decoder";
3036 video-encoder {
3037 compatible = "venus-encoder";
3040 venus_opp_table: opp-table {
3041 compatible = "operating-points-v2";
3043 opp-150000000 {
3044 opp-hz = /bits/ 64 <150000000>;
3045 required-opps = <&rpmhpd_opp_low_svs>;
3048 opp-270000000 {
3049 opp-hz = /bits/ 64 <270000000>;
3050 required-opps = <&rpmhpd_opp_svs>;
3053 opp-340000000 {
3054 opp-hz = /bits/ 64 <340000000>;
3055 required-opps = <&rpmhpd_opp_svs_l1>;
3058 opp-434000000 {
3059 opp-hz = /bits/ 64 <434000000>;
3060 required-opps = <&rpmhpd_opp_nom>;
3063 opp-500000097 {
3064 opp-hz = /bits/ 64 <500000097>;
3065 required-opps = <&rpmhpd_opp_turbo>;
3070 videocc: clock-controller@ab00000 {
3071 compatible = "qcom,sc7180-videocc";
3074 clock-names = "bi_tcxo";
3075 #clock-cells = <1>;
3076 #reset-cells = <1>;
3077 #power-domain-cells = <1>;
3081 compatible = "qcom,sc7180-camnoc-virt";
3083 #interconnect-cells = <2>;
3084 qcom,bcm-voters = <&apps_bcm_voter>;
3087 camcc: clock-controller@ad00000 {
3088 compatible = "qcom,sc7180-camcc";
3093 clock-names = "bi_tcxo", "iface", "xo";
3094 #clock-cells = <1>;
3095 #reset-cells = <1>;
3096 #power-domain-cells = <1>;
3099 mdss: display-subsystem@ae00000 {
3100 compatible = "qcom,sc7180-mdss";
3102 reg-names = "mdss";
3104 power-domains = <&dispcc MDSS_GDSC>;
3109 clock-names = "iface", "ahb", "core";
3112 interrupt-controller;
3113 #interrupt-cells = <1>;
3116 interconnect-names = "mdp0-mem";
3120 #address-cells = <2>;
3121 #size-cells = <2>;
3126 mdp: display-controller@ae01000 {
3127 compatible = "qcom,sc7180-dpu";
3130 reg-names = "mdp", "vbif";
3138 clock-names = "bus", "iface", "rot", "lut", "core",
3140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3143 assigned-clock-rates = <19200000>,
3146 operating-points-v2 = <&mdp_opp_table>;
3147 power-domains = <&rpmhpd SC7180_CX>;
3149 interrupt-parent = <&mdss>;
3153 #address-cells = <1>;
3154 #size-cells = <0>;
3159 remote-endpoint = <&mdss_dsi0_in>;
3166 remote-endpoint = <&dp_in>;
3171 mdp_opp_table: opp-table {
3172 compatible = "operating-points-v2";
3174 opp-200000000 {
3175 opp-hz = /bits/ 64 <200000000>;
3176 required-opps = <&rpmhpd_opp_low_svs>;
3179 opp-300000000 {
3180 opp-hz = /bits/ 64 <300000000>;
3181 required-opps = <&rpmhpd_opp_svs>;
3184 opp-345000000 {
3185 opp-hz = /bits/ 64 <345000000>;
3186 required-opps = <&rpmhpd_opp_svs_l1>;
3189 opp-460000000 {
3190 opp-hz = /bits/ 64 <460000000>;
3191 required-opps = <&rpmhpd_opp_nom>;
3197 compatible = "qcom,sc7180-dsi-ctrl",
3198 "qcom,mdss-dsi-ctrl";
3200 reg-names = "dsi_ctrl";
3202 interrupt-parent = <&mdss>;
3211 clock-names = "byte",
3218 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3219 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3221 operating-points-v2 = <&dsi_opp_table>;
3222 power-domains = <&rpmhpd SC7180_CX>;
3226 #address-cells = <1>;
3227 #size-cells = <0>;
3232 #address-cells = <1>;
3233 #size-cells = <0>;
3238 remote-endpoint = <&dpu_intf1_out>;
3249 dsi_opp_table: opp-table {
3250 compatible = "operating-points-v2";
3252 opp-187500000 {
3253 opp-hz = /bits/ 64 <187500000>;
3254 required-opps = <&rpmhpd_opp_low_svs>;
3257 opp-300000000 {
3258 opp-hz = /bits/ 64 <300000000>;
3259 required-opps = <&rpmhpd_opp_svs>;
3262 opp-358000000 {
3263 opp-hz = /bits/ 64 <358000000>;
3264 required-opps = <&rpmhpd_opp_svs_l1>;
3270 compatible = "qcom,dsi-phy-10nm";
3274 reg-names = "dsi_phy",
3278 #clock-cells = <1>;
3279 #phy-cells = <0>;
3283 clock-names = "iface", "ref";
3288 mdss_dp: displayport-controller@ae90000 {
3289 compatible = "qcom,sc7180-dp";
3298 interrupt-parent = <&mdss>;
3306 clock-names = "core_iface", "core_aux", "ctrl_link",
3308 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3310 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3312 phy-names = "dp";
3314 operating-points-v2 = <&dp_opp_table>;
3315 power-domains = <&rpmhpd SC7180_CX>;
3317 #sound-dai-cells = <0>;
3320 #address-cells = <1>;
3321 #size-cells = <0>;
3325 remote-endpoint = <&dpu_intf0_out>;
3335 dp_opp_table: opp-table {
3336 compatible = "operating-points-v2";
3338 opp-160000000 {
3339 opp-hz = /bits/ 64 <160000000>;
3340 required-opps = <&rpmhpd_opp_low_svs>;
3343 opp-270000000 {
3344 opp-hz = /bits/ 64 <270000000>;
3345 required-opps = <&rpmhpd_opp_svs>;
3348 opp-540000000 {
3349 opp-hz = /bits/ 64 <540000000>;
3350 required-opps = <&rpmhpd_opp_svs_l1>;
3353 opp-810000000 {
3354 opp-hz = /bits/ 64 <810000000>;
3355 required-opps = <&rpmhpd_opp_nom>;
3361 dispcc: clock-controller@af00000 {
3362 compatible = "qcom,sc7180-dispcc";
3370 clock-names = "bi_tcxo",
3376 #clock-cells = <1>;
3377 #reset-cells = <1>;
3378 #power-domain-cells = <1>;
3381 pdc: interrupt-controller@b220000 {
3382 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3384 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3385 #interrupt-cells = <2>;
3386 interrupt-parent = <&intc>;
3387 interrupt-controller;
3390 pdc_reset: reset-controller@b2e0000 {
3391 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3393 #reset-cells = <1>;
3396 tsens0: thermal-sensor@c263000 {
3397 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3403 interrupt-names = "uplow","critical";
3404 #thermal-sensor-cells = <1>;
3407 tsens1: thermal-sensor@c265000 {
3408 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3414 interrupt-names = "uplow","critical";
3415 #thermal-sensor-cells = <1>;
3418 aoss_reset: reset-controller@c2a0000 {
3419 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3421 #reset-cells = <1>;
3424 aoss_qmp: power-management@c300000 {
3425 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3430 #clock-cells = <0>;
3434 compatible = "qcom,rpmh-stats";
3439 compatible = "qcom,spmi-pmic-arb";
3445 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3446 interrupt-names = "periph_irq";
3447 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3450 #address-cells = <2>;
3451 #size-cells = <0>;
3452 interrupt-controller;
3453 #interrupt-cells = <4>;
3457 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3460 #address-cells = <1>;
3461 #size-cells = <1>;
3465 pil-reloc@94c {
3466 compatible = "qcom,pil-reloc-info";
3472 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3474 #iommu-cells = <2>;
3475 #global-interrupts = <1>;
3559 intc: interrupt-controller@17a00000 {
3560 compatible = "arm,gic-v3";
3561 #address-cells = <2>;
3562 #size-cells = <2>;
3564 #interrupt-cells = <3>;
3565 interrupt-controller;
3570 msi-controller@17a40000 {
3571 compatible = "arm,gic-v3-its";
3572 msi-controller;
3573 #msi-cells = <1>;
3580 compatible = "qcom,sc7180-apss-shared",
3581 "qcom,sdm845-apss-shared";
3583 #mbox-cells = <1>;
3587 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3594 #address-cells = <1>;
3595 #size-cells = <1>;
3597 compatible = "arm,armv7-timer-mem";
3601 frame-number = <0>;
3609 frame-number = <1>;
3616 frame-number = <2>;
3623 frame-number = <3>;
3630 frame-number = <4>;
3637 frame-number = <5>;
3644 frame-number = <6>;
3652 compatible = "qcom,rpmh-rsc";
3656 reg-names = "drv-0", "drv-1", "drv-2";
3660 qcom,tcs-offset = <0xd00>;
3661 qcom,drv-id = <2>;
3662 qcom,tcs-config = <ACTIVE_TCS 2>,
3666 power-domains = <&CLUSTER_PD>;
3668 rpmhcc: clock-controller {
3669 compatible = "qcom,sc7180-rpmh-clk";
3671 clock-names = "xo";
3672 #clock-cells = <1>;
3675 rpmhpd: power-controller {
3676 compatible = "qcom,sc7180-rpmhpd";
3677 #power-domain-cells = <1>;
3678 operating-points-v2 = <&rpmhpd_opp_table>;
3680 rpmhpd_opp_table: opp-table {
3681 compatible = "operating-points-v2";
3684 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3688 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3692 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3696 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3700 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3704 opp-level = <224>;
3708 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3712 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3716 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3720 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3724 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3729 apps_bcm_voter: bcm-voter {
3730 compatible = "qcom,bcm-voter";
3735 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3739 clock-names = "xo", "alternate";
3741 #interconnect-cells = <1>;
3745 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3747 reg-names = "freq-domain0", "freq-domain1";
3750 clock-names = "xo", "alternate";
3752 #freq-domain-cells = <1>;
3753 #clock-cells = <1>;
3757 compatible = "qcom,wcn3990-wifi";
3759 reg-names = "membase";
3774 memory-region = <&wlan_mem>;
3775 qcom,msa-fixed-perm;
3779 lpasscc: clock-controller@62d00000 {
3780 compatible = "qcom,sc7180-lpasscorecc";
3783 reg-names = "lpass_core_cc", "lpass_audio_cc";
3786 clock-names = "iface", "bi_tcxo";
3787 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3788 #clock-cells = <1>;
3789 #power-domain-cells = <1>;
3795 compatible = "qcom,sc7180-lpass-cpu";
3798 reg-names = "lpass-hdmiif", "lpass-lpaif";
3804 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3805 required-opps = <&rpmhpd_opp_nom>;
3816 clock-names = "pcnoc-sway-clk", "audio-core",
3817 "mclk0", "pcnoc-mport-clk",
3818 "mi2s-bit-clk0", "mi2s-bit-clk1";
3821 #sound-dai-cells = <1>;
3822 #address-cells = <1>;
3823 #size-cells = <0>;
3827 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3830 lpass_hm: clock-controller@63000000 {
3831 compatible = "qcom,sc7180-lpasshm";
3835 clock-names = "iface", "bi_tcxo";
3836 power-domains = <&rpmhpd SC7180_CX>;
3838 #clock-cells = <1>;
3839 #power-domain-cells = <1>;
3845 thermal-zones {
3846 cpu0_thermal: cpu0-thermal {
3847 polling-delay-passive = <250>;
3848 polling-delay = <0>;
3850 thermal-sensors = <&tsens0 1>;
3851 sustainable-power = <1052>;
3854 cpu0_alert0: trip-point0 {
3860 cpu0_alert1: trip-point1 {
3866 cpu0_crit: cpu-crit {
3873 cooling-maps {
3876 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3895 cpu1_thermal: cpu1-thermal {
3896 polling-delay-passive = <250>;
3897 polling-delay = <0>;
3899 thermal-sensors = <&tsens0 2>;
3900 sustainable-power = <1052>;
3903 cpu1_alert0: trip-point0 {
3909 cpu1_alert1: trip-point1 {
3915 cpu1_crit: cpu-crit {
3922 cooling-maps {
3925 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3934 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3944 cpu2_thermal: cpu2-thermal {
3945 polling-delay-passive = <250>;
3946 polling-delay = <0>;
3948 thermal-sensors = <&tsens0 3>;
3949 sustainable-power = <1052>;
3952 cpu2_alert0: trip-point0 {
3958 cpu2_alert1: trip-point1 {
3964 cpu2_crit: cpu-crit {
3971 cooling-maps {
3974 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3983 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3993 cpu3_thermal: cpu3-thermal {
3994 polling-delay-passive = <250>;
3995 polling-delay = <0>;
3997 thermal-sensors = <&tsens0 4>;
3998 sustainable-power = <1052>;
4001 cpu3_alert0: trip-point0 {
4007 cpu3_alert1: trip-point1 {
4013 cpu3_crit: cpu-crit {
4020 cooling-maps {
4023 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4032 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4042 cpu4_thermal: cpu4-thermal {
4043 polling-delay-passive = <250>;
4044 polling-delay = <0>;
4046 thermal-sensors = <&tsens0 5>;
4047 sustainable-power = <1052>;
4050 cpu4_alert0: trip-point0 {
4056 cpu4_alert1: trip-point1 {
4062 cpu4_crit: cpu-crit {
4069 cooling-maps {
4072 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4081 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4091 cpu5_thermal: cpu5-thermal {
4092 polling-delay-passive = <250>;
4093 polling-delay = <0>;
4095 thermal-sensors = <&tsens0 6>;
4096 sustainable-power = <1052>;
4099 cpu5_alert0: trip-point0 {
4105 cpu5_alert1: trip-point1 {
4111 cpu5_crit: cpu-crit {
4118 cooling-maps {
4121 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4130 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4140 cpu6_thermal: cpu6-thermal {
4141 polling-delay-passive = <250>;
4142 polling-delay = <0>;
4144 thermal-sensors = <&tsens0 9>;
4145 sustainable-power = <1425>;
4148 cpu6_alert0: trip-point0 {
4154 cpu6_alert1: trip-point1 {
4160 cpu6_crit: cpu-crit {
4167 cooling-maps {
4170 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4175 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4181 cpu7_thermal: cpu7-thermal {
4182 polling-delay-passive = <250>;
4183 polling-delay = <0>;
4185 thermal-sensors = <&tsens0 10>;
4186 sustainable-power = <1425>;
4189 cpu7_alert0: trip-point0 {
4195 cpu7_alert1: trip-point1 {
4201 cpu7_crit: cpu-crit {
4208 cooling-maps {
4211 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4216 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222 cpu8_thermal: cpu8-thermal {
4223 polling-delay-passive = <250>;
4224 polling-delay = <0>;
4226 thermal-sensors = <&tsens0 11>;
4227 sustainable-power = <1425>;
4230 cpu8_alert0: trip-point0 {
4236 cpu8_alert1: trip-point1 {
4242 cpu8_crit: cpu-crit {
4249 cooling-maps {
4252 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4257 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4263 cpu9_thermal: cpu9-thermal {
4264 polling-delay-passive = <250>;
4265 polling-delay = <0>;
4267 thermal-sensors = <&tsens0 12>;
4268 sustainable-power = <1425>;
4271 cpu9_alert0: trip-point0 {
4277 cpu9_alert1: trip-point1 {
4283 cpu9_crit: cpu-crit {
4290 cooling-maps {
4293 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4298 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4304 aoss0-thermal {
4305 polling-delay-passive = <250>;
4306 polling-delay = <0>;
4308 thermal-sensors = <&tsens0 0>;
4311 aoss0_alert0: trip-point0 {
4317 aoss0_crit: aoss0-crit {
4325 cpuss0-thermal {
4326 polling-delay-passive = <250>;
4327 polling-delay = <0>;
4329 thermal-sensors = <&tsens0 7>;
4332 cpuss0_alert0: trip-point0 {
4337 cpuss0_crit: cluster0-crit {
4345 cpuss1-thermal {
4346 polling-delay-passive = <250>;
4347 polling-delay = <0>;
4349 thermal-sensors = <&tsens0 8>;
4352 cpuss1_alert0: trip-point0 {
4357 cpuss1_crit: cluster0-crit {
4365 gpuss0-thermal {
4366 polling-delay-passive = <250>;
4367 polling-delay = <0>;
4369 thermal-sensors = <&tsens0 13>;
4372 gpuss0_alert0: trip-point0 {
4378 gpuss0_crit: gpuss0-crit {
4385 cooling-maps {
4388 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4393 gpuss1-thermal {
4394 polling-delay-passive = <250>;
4395 polling-delay = <0>;
4397 thermal-sensors = <&tsens0 14>;
4400 gpuss1_alert0: trip-point0 {
4406 gpuss1_crit: gpuss1-crit {
4413 cooling-maps {
4416 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4421 aoss1-thermal {
4422 polling-delay-passive = <250>;
4423 polling-delay = <0>;
4425 thermal-sensors = <&tsens1 0>;
4428 aoss1_alert0: trip-point0 {
4434 aoss1_crit: aoss1-crit {
4442 cwlan-thermal {
4443 polling-delay-passive = <250>;
4444 polling-delay = <0>;
4446 thermal-sensors = <&tsens1 1>;
4449 cwlan_alert0: trip-point0 {
4455 cwlan_crit: cwlan-crit {
4463 audio-thermal {
4464 polling-delay-passive = <250>;
4465 polling-delay = <0>;
4467 thermal-sensors = <&tsens1 2>;
4470 audio_alert0: trip-point0 {
4476 audio_crit: audio-crit {
4484 ddr-thermal {
4485 polling-delay-passive = <250>;
4486 polling-delay = <0>;
4488 thermal-sensors = <&tsens1 3>;
4491 ddr_alert0: trip-point0 {
4497 ddr_crit: ddr-crit {
4505 q6-hvx-thermal {
4506 polling-delay-passive = <250>;
4507 polling-delay = <0>;
4509 thermal-sensors = <&tsens1 4>;
4512 q6_hvx_alert0: trip-point0 {
4518 q6_hvx_crit: q6-hvx-crit {
4526 camera-thermal {
4527 polling-delay-passive = <250>;
4528 polling-delay = <0>;
4530 thermal-sensors = <&tsens1 5>;
4533 camera_alert0: trip-point0 {
4539 camera_crit: camera-crit {
4547 mdm-core-thermal {
4548 polling-delay-passive = <250>;
4549 polling-delay = <0>;
4551 thermal-sensors = <&tsens1 6>;
4554 mdm_alert0: trip-point0 {
4560 mdm_crit: mdm-crit {
4568 mdm-dsp-thermal {
4569 polling-delay-passive = <250>;
4570 polling-delay = <0>;
4572 thermal-sensors = <&tsens1 7>;
4575 mdm_dsp_alert0: trip-point0 {
4581 mdm_dsp_crit: mdm-dsp-crit {
4589 npu-thermal {
4590 polling-delay-passive = <250>;
4591 polling-delay = <0>;
4593 thermal-sensors = <&tsens1 8>;
4596 npu_alert0: trip-point0 {
4602 npu_crit: npu-crit {
4610 video-thermal {
4611 polling-delay-passive = <250>;
4612 polling-delay = <0>;
4614 thermal-sensors = <&tsens1 9>;
4617 video_alert0: trip-point0 {
4623 video_crit: video-crit {
4633 compatible = "arm,armv8-timer";